[mirror_ubuntu-zesty-kernel.git] / arch / arm / mach-integrator / integrator_cp.c

/*
 *  linux/arch/arm/mach-integrator/integrator_cp.c
 *
 *  Copyright (C) 2003 Deep Blue Solutions Ltd
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License.
 */
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/list.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/string.h>
#include <linux/device.h>
#include <linux/amba/bus.h>
#include <linux/amba/kmi.h>
#include <linux/amba/clcd.h>
#include <linux/amba/mmci.h>
#include <linux/io.h>
#include <linux/irqchip/versatile-fpga.h>
#include <linux/gfp.h>
#include <linux/mtd/physmap.h>
#include <linux/platform_data/clk-integrator.h>
#include <linux/of_irq.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/sys_soc.h>

#include <mach/hardware.h>
#include <mach/platform.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/hardware/arm_timer.h>
#include <asm/hardware/icst.h>

#include <mach/lm.h>

#include <asm/mach/arch.h>
#include <asm/mach/irq.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>

#include <asm/hardware/timer-sp.h>

#include <plat/clcd.h>
#include <plat/sched_clock.h>

#include "cm.h"
#include "common.h"

/* Base address to the CP controller */
static void __iomem *intcp_con_base;

#define INTCP_PA_FLASH_BASE		0x24000000

#define INTCP_PA_CLCD_BASE		0xc0000000

#define INTCP_FLASHPROG			0x04
#define CINTEGRATOR_FLASHPROG_FLVPPEN	(1 << 0)
#define CINTEGRATOR_FLASHPROG_FLWREN	(1 << 1)

/*
 * Logical      Physical
 * f1000000	10000000	Core module registers
 * f1100000	11000000	System controller registers
 * f1200000	12000000	EBI registers
 * f1300000	13000000	Counter/Timer
 * f1400000	14000000	Interrupt controller
 * f1600000	16000000	UART 0
 * f1700000	17000000	UART 1
 * f1a00000	1a000000	Debug LEDs
 * fc900000	c9000000	GPIO
 * fca00000	ca000000	SIC
 * fcb00000	cb000000	CP system control
 */

static struct map_desc intcp_io_desc[] __initdata __maybe_unused = {
	{
		.virtual	= IO_ADDRESS(INTEGRATOR_HDR_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_HDR_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_EBI_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_EBI_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_CT_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_CT_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_IC_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_IC_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_UART0_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_UART0_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_DBG_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_DBG_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_CP_GPIO_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_CP_GPIO_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_CP_SIC_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_CP_SIC_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}
};

static void __init intcp_map_io(void)
{
	iotable_init(intcp_io_desc, ARRAY_SIZE(intcp_io_desc));
}

/*
 * Flash handling.
 */
static int intcp_flash_init(struct platform_device *dev)
{
	u32 val;

	val = readl(intcp_con_base + INTCP_FLASHPROG);
	val |= CINTEGRATOR_FLASHPROG_FLWREN;
	writel(val, intcp_con_base + INTCP_FLASHPROG);

	return 0;
}

static void intcp_flash_exit(struct platform_device *dev)
{
	u32 val;

	val = readl(intcp_con_base + INTCP_FLASHPROG);
	val &= ~(CINTEGRATOR_FLASHPROG_FLVPPEN|CINTEGRATOR_FLASHPROG_FLWREN);
	writel(val, intcp_con_base + INTCP_FLASHPROG);
}

static void intcp_flash_set_vpp(struct platform_device *pdev, int on)
{
	u32 val;

	val = readl(intcp_con_base + INTCP_FLASHPROG);
	if (on)
		val |= CINTEGRATOR_FLASHPROG_FLVPPEN;
	else
		val &= ~CINTEGRATOR_FLASHPROG_FLVPPEN;
	writel(val, intcp_con_base + INTCP_FLASHPROG);
}

static struct physmap_flash_data intcp_flash_data = {
	.width		= 4,
	.init		= intcp_flash_init,
	.exit		= intcp_flash_exit,
	.set_vpp	= intcp_flash_set_vpp,
};

/*
 * It seems that the card insertion interrupt remains active after
 * we've acknowledged it.  We therefore ignore the interrupt, and
 * rely on reading it from the SIC.  This also means that we must
 * clear the latched interrupt.
 */
static unsigned int mmc_status(struct device *dev)
{
	unsigned int status = readl(__io_address(0xca000000 + 4));
	writel(8, intcp_con_base + 8);

	return status & 8;
}

static struct mmci_platform_data mmc_data = {
	.ocr_mask	= MMC_VDD_32_33|MMC_VDD_33_34,
	.status		= mmc_status,
	.gpio_wp	= -1,
	.gpio_cd	= -1,
};

/*
 * CLCD support
 */
/*
 * Ensure VGA is selected.
 */
static void cp_clcd_enable(struct clcd_fb *fb)
{
	struct fb_var_screeninfo *var = &fb->fb.var;
	u32 val = CM_CTRL_STATIC1 | CM_CTRL_STATIC2
			| CM_CTRL_LCDEN0 | CM_CTRL_LCDEN1;

	if (var->bits_per_pixel <= 8 ||
	    (var->bits_per_pixel == 16 && var->green.length == 5))
		/* Pseudocolor, RGB555, BGR555 */
		val |= CM_CTRL_LCDMUXSEL_VGA555_TFT555;
	else if (fb->fb.var.bits_per_pixel <= 16)
		/* truecolor RGB565 */
		val |= CM_CTRL_LCDMUXSEL_VGA565_TFT555;
	else
		val = 0; /* no idea for this, don't trust the docs */

	cm_control(CM_CTRL_LCDMUXSEL_MASK|
		   CM_CTRL_LCDEN0|
		   CM_CTRL_LCDEN1|
		   CM_CTRL_STATIC1|
		   CM_CTRL_STATIC2|
		   CM_CTRL_STATIC|
		   CM_CTRL_n24BITEN, val);
}

static int cp_clcd_setup(struct clcd_fb *fb)
{
	fb->panel = versatile_clcd_get_panel("VGA");
	if (!fb->panel)
		return -EINVAL;

	return versatile_clcd_setup_dma(fb, SZ_1M);
}

static struct clcd_board clcd_data = {
	.name		= "Integrator/CP",
	.caps		= CLCD_CAP_5551 | CLCD_CAP_RGB565 | CLCD_CAP_888,
	.check		= clcdfb_check,
	.decode		= clcdfb_decode,
	.enable		= cp_clcd_enable,
	.setup		= cp_clcd_setup,
	.mmap		= versatile_clcd_mmap_dma,
	.remove		= versatile_clcd_remove_dma,
};

#define REFCOUNTER (__io_address(INTEGRATOR_HDR_BASE) + 0x28)

static void __init intcp_init_early(void)
{
#ifdef CONFIG_PLAT_VERSATILE_SCHED_CLOCK
	versatile_sched_clock_init(REFCOUNTER, 24000000);
#endif
}

static const struct of_device_id fpga_irq_of_match[] __initconst = {
	{ .compatible = "arm,versatile-fpga-irq", .data = fpga_irq_of_init, },
	{ /* Sentinel */ }
};

static void __init intcp_init_irq_of(void)
{
	cm_init();
	of_irq_init(fpga_irq_of_match);
	integrator_clk_init(true);
}

/*
 * For the Device Tree, add in the UART, MMC and CLCD specifics as AUXDATA
 * and enforce the bus names since these are used for clock lookups.
 */
static struct of_dev_auxdata intcp_auxdata_lookup[] __initdata = {
	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_RTC_BASE,
		"rtc", NULL),
	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART0_BASE,
		"uart0", NULL),
	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART1_BASE,
		"uart1", NULL),
	OF_DEV_AUXDATA("arm,primecell", KMI0_BASE,
		"kmi0", NULL),
	OF_DEV_AUXDATA("arm,primecell", KMI1_BASE,
		"kmi1", NULL),
	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_CP_MMC_BASE,
		"mmci", &mmc_data),
	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_CP_AACI_BASE,
		"aaci", &mmc_data),
	OF_DEV_AUXDATA("arm,primecell", INTCP_PA_CLCD_BASE,
		"clcd", &clcd_data),
	OF_DEV_AUXDATA("cfi-flash", INTCP_PA_FLASH_BASE,
		"physmap-flash", &intcp_flash_data),
	{ /* sentinel */ },
};

static const struct of_device_id intcp_syscon_match[] = {
	{ .compatible = "arm,integrator-cp-syscon"},
	{ },
};

static void __init intcp_init_of(void)
{
	struct device_node *root;
	struct device_node *cpcon;
	struct device *parent;
	struct soc_device *soc_dev;
	struct soc_device_attribute *soc_dev_attr;
	u32 intcp_sc_id;
	int err;

	/* Here we create an SoC device for the root node */
	root = of_find_node_by_path("/");
	if (!root)
		return;

	cpcon = of_find_matching_node(root, intcp_syscon_match);
	if (!cpcon)
		return;

	intcp_con_base = of_iomap(cpcon, 0);
	if (!intcp_con_base)
		return;

	intcp_sc_id = readl(intcp_con_base);

	soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
	if (!soc_dev_attr)
		return;

	err = of_property_read_string(root, "compatible",
				      &soc_dev_attr->soc_id);
	if (err)
		return;
	err = of_property_read_string(root, "model", &soc_dev_attr->machine);
	if (err)
		return;
	soc_dev_attr->family = "Integrator";
	soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%c",
					   'A' + (intcp_sc_id & 0x0f));

	soc_dev = soc_device_register(soc_dev_attr);
	if (IS_ERR(soc_dev)) {
		kfree(soc_dev_attr->revision);
		kfree(soc_dev_attr);
		return;
	}

	parent = soc_device_to_device(soc_dev);
	integrator_init_sysfs(parent, intcp_sc_id);
	of_platform_populate(root, of_default_bus_match_table,
			intcp_auxdata_lookup, parent);
}

static const char * intcp_dt_board_compat[] = {
	"arm,integrator-cp",
	NULL,
};

DT_MACHINE_START(INTEGRATOR_CP_DT, "ARM Integrator/CP (Device Tree)")
	.reserve	= integrator_reserve,
	.map_io		= intcp_map_io,
	.init_early	= intcp_init_early,
	.init_irq	= intcp_init_irq_of,
	.handle_irq	= fpga_handle_irq,
	.init_machine	= intcp_init_of,
	.restart	= integrator_restart,
	.dt_compat      = intcp_dt_board_compat,
MACHINE_END
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mach-integrator/integrator_cp.c
	3	*
	4	* Copyright (C) 2003 Deep Blue Solutions Ltd
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License.
	9	*/
	10	#include <linux/types.h>
	11	#include <linux/kernel.h>
	12	#include <linux/init.h>
	13	#include <linux/list.h>
d052d1be	14	#include <linux/platform_device.h>
1da177e4	15	#include <linux/dma-mapping.h>
1da177e4	16	#include <linux/string.h>
edbaa603	17	#include <linux/device.h>
a62c80e5 RK	18	#include <linux/amba/bus.h>
	19	#include <linux/amba/kmi.h>
	20	#include <linux/amba/clcd.h>
6ef297f8	21	#include <linux/amba/mmci.h>
fced80c7	22	#include <linux/io.h>
2389d501	23	#include <linux/irqchip/versatile-fpga.h>
5a0e3ad6	24	#include <linux/gfp.h>
046dfa0a	25	#include <linux/mtd/physmap.h>
a613163d	26	#include <linux/platform_data/clk-integrator.h>
4980f9bc LW	27	#include <linux/of_irq.h>
4980f9bc LW	28	#include <linux/of_address.h>
4672cddf	29	#include <linux/of_platform.h>
64100a03	30	#include <linux/sys_soc.h>
1da177e4	31
a09e64fb	32	#include <mach/hardware.h>
a285edcf	33	#include <mach/platform.h>
1da177e4 LT	34	#include <asm/setup.h>
1da177e4 LT	35	#include <asm/mach-types.h>
5a46334a	36	#include <asm/hardware/arm_timer.h>
c5a0adb5	37	#include <asm/hardware/icst.h>
1da177e4	38
a09e64fb	39	#include <mach/lm.h>
1da177e4 LT	40
1da177e4 LT	41	#include <asm/mach/arch.h>
1da177e4	42	#include <asm/mach/irq.h>
1da177e4 LT	43	#include <asm/mach/map.h>
	44	#include <asm/mach/time.h>
	45
8a9618f5	46	#include <asm/hardware/timer-sp.h>
5a46334a	47
9dfec4fe	48	#include <plat/clcd.h>
d77e270c	49	#include <plat/sched_clock.h>
9dfec4fe	50
bb4dbefe	51	#include "cm.h"
98c672cf RK	52	#include "common.h"
98c672cf RK	53
e6fae083 LW	54	/* Base address to the CP controller */
	55	static void __iomem *intcp_con_base;
	56
1da177e4	57	#define INTCP_PA_FLASH_BASE 0x24000000
1da177e4 LT	58
	59	#define INTCP_PA_CLCD_BASE 0xc0000000
	60
1da177e4 LT	61	#define INTCP_FLASHPROG 0x04
	62	#define CINTEGRATOR_FLASHPROG_FLVPPEN (1 << 0)
	63	#define CINTEGRATOR_FLASHPROG_FLWREN (1 << 1)
	64
	65	/*
	66	* Logical Physical
	67	* f1000000 10000000 Core module registers
	68	* f1100000 11000000 System controller registers
	69	* f1200000 12000000 EBI registers
	70	* f1300000 13000000 Counter/Timer
	71	* f1400000 14000000 Interrupt controller
	72	* f1600000 16000000 UART 0
	73	* f1700000 17000000 UART 1
	74	* f1a00000 1a000000 Debug LEDs
da7ba956 RK	75	* fc900000 c9000000 GPIO
	76	* fca00000 ca000000 SIC
	77	* fcb00000 cb000000 CP system control
1da177e4 LT	78	*/
1da177e4 LT	79
060fd1be	80	static struct map_desc intcp_io_desc[] __initdata __maybe_unused = {
c8d27298 DS	81	{
	82	.virtual = IO_ADDRESS(INTEGRATOR_HDR_BASE),
	83	.pfn = __phys_to_pfn(INTEGRATOR_HDR_BASE),
	84	.length = SZ_4K,
	85	.type = MT_DEVICE
c8d27298 DS	86	}, {
	87	.virtual = IO_ADDRESS(INTEGRATOR_EBI_BASE),
	88	.pfn = __phys_to_pfn(INTEGRATOR_EBI_BASE),
	89	.length = SZ_4K,
	90	.type = MT_DEVICE
	91	}, {
	92	.virtual = IO_ADDRESS(INTEGRATOR_CT_BASE),
	93	.pfn = __phys_to_pfn(INTEGRATOR_CT_BASE),
	94	.length = SZ_4K,
	95	.type = MT_DEVICE
	96	}, {
	97	.virtual = IO_ADDRESS(INTEGRATOR_IC_BASE),
	98	.pfn = __phys_to_pfn(INTEGRATOR_IC_BASE),
	99	.length = SZ_4K,
	100	.type = MT_DEVICE
	101	}, {
	102	.virtual = IO_ADDRESS(INTEGRATOR_UART0_BASE),
	103	.pfn = __phys_to_pfn(INTEGRATOR_UART0_BASE),
	104	.length = SZ_4K,
	105	.type = MT_DEVICE
c8d27298 DS	106	}, {
	107	.virtual = IO_ADDRESS(INTEGRATOR_DBG_BASE),
	108	.pfn = __phys_to_pfn(INTEGRATOR_DBG_BASE),
	109	.length = SZ_4K,
	110	.type = MT_DEVICE
	111	}, {
da7ba956 RK	112	.virtual = IO_ADDRESS(INTEGRATOR_CP_GPIO_BASE),
da7ba956 RK	113	.pfn = __phys_to_pfn(INTEGRATOR_CP_GPIO_BASE),
c8d27298 DS	114	.length = SZ_4K,
	115	.type = MT_DEVICE
	116	}, {
da7ba956 RK	117	.virtual = IO_ADDRESS(INTEGRATOR_CP_SIC_BASE),
da7ba956 RK	118	.pfn = __phys_to_pfn(INTEGRATOR_CP_SIC_BASE),
c8d27298 DS	119	.length = SZ_4K,
c8d27298 DS	120	.type = MT_DEVICE
c8d27298	121	}
1da177e4 LT	122	};
	123
	124	static void __init intcp_map_io(void)
	125	{
	126	iotable_init(intcp_io_desc, ARRAY_SIZE(intcp_io_desc));
	127	}
	128
1da177e4 LT	129	/*
	130	* Flash handling.
	131	*/
046dfa0a	132	static int intcp_flash_init(struct platform_device *dev)
1da177e4 LT	133	{
	134	u32 val;
	135
e6fae083	136	val = readl(intcp_con_base + INTCP_FLASHPROG);
1da177e4	137	val \|= CINTEGRATOR_FLASHPROG_FLWREN;
e6fae083	138	writel(val, intcp_con_base + INTCP_FLASHPROG);
1da177e4 LT	139
	140	return 0;
	141	}
	142
046dfa0a	143	static void intcp_flash_exit(struct platform_device *dev)
1da177e4 LT	144	{
	145	u32 val;
	146
e6fae083	147	val = readl(intcp_con_base + INTCP_FLASHPROG);
1da177e4	148	val &= ~(CINTEGRATOR_FLASHPROG_FLVPPEN\|CINTEGRATOR_FLASHPROG_FLWREN);
e6fae083	149	writel(val, intcp_con_base + INTCP_FLASHPROG);
1da177e4 LT	150	}
1da177e4 LT	151
667f390b	152	static void intcp_flash_set_vpp(struct platform_device *pdev, int on)
1da177e4 LT	153	{
	154	u32 val;
	155
e6fae083	156	val = readl(intcp_con_base + INTCP_FLASHPROG);
1da177e4 LT	157	if (on)
	158	val \|= CINTEGRATOR_FLASHPROG_FLVPPEN;
	159	else
	160	val &= ~CINTEGRATOR_FLASHPROG_FLVPPEN;
e6fae083	161	writel(val, intcp_con_base + INTCP_FLASHPROG);
1da177e4 LT	162	}
1da177e4 LT	163
046dfa0a	164	static struct physmap_flash_data intcp_flash_data = {
1da177e4 LT	165	.width = 4,
	166	.init = intcp_flash_init,
	167	.exit = intcp_flash_exit,
	168	.set_vpp = intcp_flash_set_vpp,
	169	};
	170
1da177e4 LT	171	/*
	172	* It seems that the card insertion interrupt remains active after
	173	* we've acknowledged it. We therefore ignore the interrupt, and
	174	* rely on reading it from the SIC. This also means that we must
	175	* clear the latched interrupt.
	176	*/
	177	static unsigned int mmc_status(struct device *dev)
	178	{
b7a3f8db	179	unsigned int status = readl(__io_address(0xca000000 + 4));
e6fae083	180	writel(8, intcp_con_base + 8);
1da177e4 LT	181
	182	return status & 8;
	183	}
	184
6ef297f8	185	static struct mmci_platform_data mmc_data = {
1da177e4 LT	186	.ocr_mask = MMC_VDD_32_33\|MMC_VDD_33_34,
1da177e4 LT	187	.status = mmc_status,
7fb2bbf4 RK	188	.gpio_wp = -1,
7fb2bbf4 RK	189	.gpio_cd = -1,
1da177e4 LT	190	};
1da177e4 LT	191
1da177e4 LT	192	/*
	193	* CLCD support
	194	*/
1da177e4 LT	195	/*
	196	* Ensure VGA is selected.
	197	*/
	198	static void cp_clcd_enable(struct clcd_fb *fb)
	199	{
e6b9c1f8	200	struct fb_var_screeninfo *var = &fb->fb.var;
30aeadd4 JA	201	u32 val = CM_CTRL_STATIC1 \| CM_CTRL_STATIC2
30aeadd4 JA	202	\| CM_CTRL_LCDEN0 \| CM_CTRL_LCDEN1;
4774e226	203
e6b9c1f8 RK	204	if (var->bits_per_pixel <= 8 \|\|
	205	(var->bits_per_pixel == 16 && var->green.length == 5))
	206	/* Pseudocolor, RGB555, BGR555 */
	207	val \|= CM_CTRL_LCDMUXSEL_VGA555_TFT555;
4774e226	208	else if (fb->fb.var.bits_per_pixel <= 16)
e6b9c1f8 RK	209	/* truecolor RGB565 */
e6b9c1f8 RK	210	val \|= CM_CTRL_LCDMUXSEL_VGA565_TFT555;
4774e226 RK	211	else
	212	val = 0; /* no idea for this, don't trust the docs */
	213
	214	cm_control(CM_CTRL_LCDMUXSEL_MASK\|
	215	CM_CTRL_LCDEN0\|
	216	CM_CTRL_LCDEN1\|
	217	CM_CTRL_STATIC1\|
	218	CM_CTRL_STATIC2\|
	219	CM_CTRL_STATIC\|
	220	CM_CTRL_n24BITEN, val);
1da177e4 LT	221	}
1da177e4 LT	222
1da177e4 LT	223	static int cp_clcd_setup(struct clcd_fb *fb)
1da177e4 LT	224	{
9dfec4fe RK	225	fb->panel = versatile_clcd_get_panel("VGA");
	226	if (!fb->panel)
	227	return -EINVAL;
1da177e4	228
9dfec4fe	229	return versatile_clcd_setup_dma(fb, SZ_1M);
1da177e4 LT	230	}
	231
	232	static struct clcd_board clcd_data = {
	233	.name = "Integrator/CP",
9dfec4fe	234	.caps = CLCD_CAP_5551 \| CLCD_CAP_RGB565 \| CLCD_CAP_888,
1da177e4 LT	235	.check = clcdfb_check,
	236	.decode = clcdfb_decode,
	237	.enable = cp_clcd_enable,
	238	.setup = cp_clcd_setup,
9dfec4fe RK	239	.mmap = versatile_clcd_mmap_dma,
9dfec4fe RK	240	.remove = versatile_clcd_remove_dma,
1da177e4 LT	241	};
1da177e4 LT	242
d77e270c RK	243	#define REFCOUNTER (__io_address(INTEGRATOR_HDR_BASE) + 0x28)
d77e270c RK	244
c735c987 RK	245	static void __init intcp_init_early(void)
c735c987 RK	246	{
d77e270c RK	247	#ifdef CONFIG_PLAT_VERSATILE_SCHED_CLOCK
	248	versatile_sched_clock_init(REFCOUNTER, 24000000);
	249	#endif
c735c987 RK	250	}
c735c987 RK	251
4980f9bc LW	252	static const struct of_device_id fpga_irq_of_match[] __initconst = {
	253	{ .compatible = "arm,versatile-fpga-irq", .data = fpga_irq_of_init, },
	254	{ /* Sentinel */ }
	255	};
	256
	257	static void __init intcp_init_irq_of(void)
1da177e4	258	{
bb4dbefe	259	cm_init();
4980f9bc LW	260	of_irq_init(fpga_irq_of_match);
	261	integrator_clk_init(true);
	262	}
1da177e4	263
4672cddf LW	264	/*
	265	* For the Device Tree, add in the UART, MMC and CLCD specifics as AUXDATA
	266	* and enforce the bus names since these are used for clock lookups.
	267	*/
	268	static struct of_dev_auxdata intcp_auxdata_lookup[] __initdata = {
	269	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_RTC_BASE,
	270	"rtc", NULL),
	271	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART0_BASE,
379df279	272	"uart0", NULL),
4672cddf	273	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART1_BASE,
379df279	274	"uart1", NULL),
4672cddf LW	275	OF_DEV_AUXDATA("arm,primecell", KMI0_BASE,
	276	"kmi0", NULL),
	277	OF_DEV_AUXDATA("arm,primecell", KMI1_BASE,
	278	"kmi1", NULL),
	279	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_CP_MMC_BASE,
	280	"mmci", &mmc_data),
	281	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_CP_AACI_BASE,
	282	"aaci", &mmc_data),
	283	OF_DEV_AUXDATA("arm,primecell", INTCP_PA_CLCD_BASE,
	284	"clcd", &clcd_data),
73efd530 LW	285	OF_DEV_AUXDATA("cfi-flash", INTCP_PA_FLASH_BASE,
73efd530 LW	286	"physmap-flash", &intcp_flash_data),
4672cddf LW	287	{ /* sentinel */ },
	288	};
	289
df36680f LW	290	static const struct of_device_id intcp_syscon_match[] = {
	291	{ .compatible = "arm,integrator-cp-syscon"},
	292	{ },
	293	};
	294
4672cddf LW	295	static void __init intcp_init_of(void)
4672cddf LW	296	{
64100a03 LW	297	struct device_node *root;
	298	struct device_node *cpcon;
	299	struct device *parent;
	300	struct soc_device *soc_dev;
	301	struct soc_device_attribute *soc_dev_attr;
	302	u32 intcp_sc_id;
	303	int err;
	304
	305	/* Here we create an SoC device for the root node */
	306	root = of_find_node_by_path("/");
	307	if (!root)
	308	return;
df36680f LW	309
df36680f LW	310	cpcon = of_find_matching_node(root, intcp_syscon_match);
64100a03 LW	311	if (!cpcon)
	312	return;
	313
	314	intcp_con_base = of_iomap(cpcon, 0);
	315	if (!intcp_con_base)
	316	return;
	317
	318	intcp_sc_id = readl(intcp_con_base);
	319
	320	soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
	321	if (!soc_dev_attr)
	322	return;
	323
	324	err = of_property_read_string(root, "compatible",
	325	&soc_dev_attr->soc_id);
	326	if (err)
	327	return;
	328	err = of_property_read_string(root, "model", &soc_dev_attr->machine);
	329	if (err)
	330	return;
	331	soc_dev_attr->family = "Integrator";
	332	soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%c",
	333	'A' + (intcp_sc_id & 0x0f));
	334
	335	soc_dev = soc_device_register(soc_dev_attr);
b269b170	336	if (IS_ERR(soc_dev)) {
64100a03 LW	337	kfree(soc_dev_attr->revision);
	338	kfree(soc_dev_attr);
	339	return;
	340	}
	341
	342	parent = soc_device_to_device(soc_dev);
b269b170	343	integrator_init_sysfs(parent, intcp_sc_id);
64100a03 LW	344	of_platform_populate(root, of_default_bus_match_table,
64100a03 LW	345	intcp_auxdata_lookup, parent);
4672cddf LW	346	}
4672cddf LW	347
4980f9bc LW	348	static const char * intcp_dt_board_compat[] = {
	349	"arm,integrator-cp",
	350	NULL,
	351	};
1da177e4	352
4980f9bc LW	353	DT_MACHINE_START(INTEGRATOR_CP_DT, "ARM Integrator/CP (Device Tree)")
	354	.reserve = integrator_reserve,
	355	.map_io = intcp_map_io,
4980f9bc LW	356	.init_early = intcp_init_early,
	357	.init_irq = intcp_init_irq_of,
	358	.handle_irq = fpga_handle_irq,
4672cddf	359	.init_machine = intcp_init_of,
4980f9bc LW	360	.restart = integrator_restart,
	361	.dt_compat = intcp_dt_board_compat,
	362	MACHINE_END