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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/mach-integrator/integrator_cp.c | |
3 | * | |
4 | * Copyright (C) 2003 Deep Blue Solutions Ltd | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License. | |
9 | */ | |
10 | #include <linux/types.h> | |
11 | #include <linux/kernel.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/list.h> | |
d052d1be | 14 | #include <linux/platform_device.h> |
1da177e4 LT |
15 | #include <linux/dma-mapping.h> |
16 | #include <linux/slab.h> | |
17 | #include <linux/string.h> | |
18 | #include <linux/sysdev.h> | |
a62c80e5 RK |
19 | #include <linux/amba/bus.h> |
20 | #include <linux/amba/kmi.h> | |
21 | #include <linux/amba/clcd.h> | |
6ef297f8 | 22 | #include <linux/amba/mmci.h> |
fced80c7 | 23 | #include <linux/io.h> |
1da177e4 | 24 | |
d72fbdf0 RK |
25 | #include <asm/clkdev.h> |
26 | #include <mach/clkdev.h> | |
a09e64fb | 27 | #include <mach/hardware.h> |
a285edcf | 28 | #include <mach/platform.h> |
1da177e4 LT |
29 | #include <asm/irq.h> |
30 | #include <asm/setup.h> | |
31 | #include <asm/mach-types.h> | |
1da177e4 LT |
32 | #include <asm/hardware/icst525.h> |
33 | ||
a09e64fb RK |
34 | #include <mach/cm.h> |
35 | #include <mach/lm.h> | |
1da177e4 LT |
36 | |
37 | #include <asm/mach/arch.h> | |
38 | #include <asm/mach/flash.h> | |
39 | #include <asm/mach/irq.h> | |
1da177e4 LT |
40 | #include <asm/mach/map.h> |
41 | #include <asm/mach/time.h> | |
42 | ||
43 | #include "common.h" | |
1da177e4 | 44 | |
1da177e4 LT |
45 | #define INTCP_PA_FLASH_BASE 0x24000000 |
46 | #define INTCP_FLASH_SIZE SZ_32M | |
47 | ||
48 | #define INTCP_PA_CLCD_BASE 0xc0000000 | |
49 | ||
b830b9b5 | 50 | #define INTCP_VA_CIC_BASE IO_ADDRESS(INTEGRATOR_HDR_BASE + 0x40) |
365f7a43 | 51 | #define INTCP_VA_PIC_BASE IO_ADDRESS(INTEGRATOR_IC_BASE) |
da7ba956 | 52 | #define INTCP_VA_SIC_BASE IO_ADDRESS(INTEGRATOR_CP_SIC_BASE) |
1da177e4 | 53 | |
1da177e4 LT |
54 | #define INTCP_ETH_SIZE 0x10 |
55 | ||
da7ba956 | 56 | #define INTCP_VA_CTRL_BASE IO_ADDRESS(INTEGRATOR_CP_CTL_BASE) |
1da177e4 LT |
57 | #define INTCP_FLASHPROG 0x04 |
58 | #define CINTEGRATOR_FLASHPROG_FLVPPEN (1 << 0) | |
59 | #define CINTEGRATOR_FLASHPROG_FLWREN (1 << 1) | |
60 | ||
61 | /* | |
62 | * Logical Physical | |
63 | * f1000000 10000000 Core module registers | |
64 | * f1100000 11000000 System controller registers | |
65 | * f1200000 12000000 EBI registers | |
66 | * f1300000 13000000 Counter/Timer | |
67 | * f1400000 14000000 Interrupt controller | |
68 | * f1600000 16000000 UART 0 | |
69 | * f1700000 17000000 UART 1 | |
70 | * f1a00000 1a000000 Debug LEDs | |
da7ba956 RK |
71 | * fc900000 c9000000 GPIO |
72 | * fca00000 ca000000 SIC | |
73 | * fcb00000 cb000000 CP system control | |
1da177e4 LT |
74 | */ |
75 | ||
76 | static struct map_desc intcp_io_desc[] __initdata = { | |
c8d27298 DS |
77 | { |
78 | .virtual = IO_ADDRESS(INTEGRATOR_HDR_BASE), | |
79 | .pfn = __phys_to_pfn(INTEGRATOR_HDR_BASE), | |
80 | .length = SZ_4K, | |
81 | .type = MT_DEVICE | |
82 | }, { | |
83 | .virtual = IO_ADDRESS(INTEGRATOR_SC_BASE), | |
84 | .pfn = __phys_to_pfn(INTEGRATOR_SC_BASE), | |
85 | .length = SZ_4K, | |
86 | .type = MT_DEVICE | |
87 | }, { | |
88 | .virtual = IO_ADDRESS(INTEGRATOR_EBI_BASE), | |
89 | .pfn = __phys_to_pfn(INTEGRATOR_EBI_BASE), | |
90 | .length = SZ_4K, | |
91 | .type = MT_DEVICE | |
92 | }, { | |
93 | .virtual = IO_ADDRESS(INTEGRATOR_CT_BASE), | |
94 | .pfn = __phys_to_pfn(INTEGRATOR_CT_BASE), | |
95 | .length = SZ_4K, | |
96 | .type = MT_DEVICE | |
97 | }, { | |
98 | .virtual = IO_ADDRESS(INTEGRATOR_IC_BASE), | |
99 | .pfn = __phys_to_pfn(INTEGRATOR_IC_BASE), | |
100 | .length = SZ_4K, | |
101 | .type = MT_DEVICE | |
102 | }, { | |
103 | .virtual = IO_ADDRESS(INTEGRATOR_UART0_BASE), | |
104 | .pfn = __phys_to_pfn(INTEGRATOR_UART0_BASE), | |
105 | .length = SZ_4K, | |
106 | .type = MT_DEVICE | |
107 | }, { | |
108 | .virtual = IO_ADDRESS(INTEGRATOR_UART1_BASE), | |
109 | .pfn = __phys_to_pfn(INTEGRATOR_UART1_BASE), | |
110 | .length = SZ_4K, | |
111 | .type = MT_DEVICE | |
112 | }, { | |
113 | .virtual = IO_ADDRESS(INTEGRATOR_DBG_BASE), | |
114 | .pfn = __phys_to_pfn(INTEGRATOR_DBG_BASE), | |
115 | .length = SZ_4K, | |
116 | .type = MT_DEVICE | |
117 | }, { | |
da7ba956 RK |
118 | .virtual = IO_ADDRESS(INTEGRATOR_CP_GPIO_BASE), |
119 | .pfn = __phys_to_pfn(INTEGRATOR_CP_GPIO_BASE), | |
c8d27298 DS |
120 | .length = SZ_4K, |
121 | .type = MT_DEVICE | |
122 | }, { | |
da7ba956 RK |
123 | .virtual = IO_ADDRESS(INTEGRATOR_CP_SIC_BASE), |
124 | .pfn = __phys_to_pfn(INTEGRATOR_CP_SIC_BASE), | |
c8d27298 DS |
125 | .length = SZ_4K, |
126 | .type = MT_DEVICE | |
127 | }, { | |
da7ba956 RK |
128 | .virtual = IO_ADDRESS(INTEGRATOR_CP_CTL_BASE), |
129 | .pfn = __phys_to_pfn(INTEGRATOR_CP_CTL_BASE), | |
c8d27298 DS |
130 | .length = SZ_4K, |
131 | .type = MT_DEVICE | |
132 | } | |
1da177e4 LT |
133 | }; |
134 | ||
135 | static void __init intcp_map_io(void) | |
136 | { | |
137 | iotable_init(intcp_io_desc, ARRAY_SIZE(intcp_io_desc)); | |
138 | } | |
139 | ||
140 | #define cic_writel __raw_writel | |
141 | #define cic_readl __raw_readl | |
142 | #define pic_writel __raw_writel | |
143 | #define pic_readl __raw_readl | |
144 | #define sic_writel __raw_writel | |
145 | #define sic_readl __raw_readl | |
146 | ||
147 | static void cic_mask_irq(unsigned int irq) | |
148 | { | |
149 | irq -= IRQ_CIC_START; | |
150 | cic_writel(1 << irq, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR); | |
151 | } | |
152 | ||
153 | static void cic_unmask_irq(unsigned int irq) | |
154 | { | |
155 | irq -= IRQ_CIC_START; | |
156 | cic_writel(1 << irq, INTCP_VA_CIC_BASE + IRQ_ENABLE_SET); | |
157 | } | |
158 | ||
38c677cb DB |
159 | static struct irq_chip cic_chip = { |
160 | .name = "CIC", | |
1da177e4 LT |
161 | .ack = cic_mask_irq, |
162 | .mask = cic_mask_irq, | |
163 | .unmask = cic_unmask_irq, | |
164 | }; | |
165 | ||
166 | static void pic_mask_irq(unsigned int irq) | |
167 | { | |
168 | irq -= IRQ_PIC_START; | |
169 | pic_writel(1 << irq, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR); | |
170 | } | |
171 | ||
172 | static void pic_unmask_irq(unsigned int irq) | |
173 | { | |
174 | irq -= IRQ_PIC_START; | |
175 | pic_writel(1 << irq, INTCP_VA_PIC_BASE + IRQ_ENABLE_SET); | |
176 | } | |
177 | ||
38c677cb DB |
178 | static struct irq_chip pic_chip = { |
179 | .name = "PIC", | |
1da177e4 LT |
180 | .ack = pic_mask_irq, |
181 | .mask = pic_mask_irq, | |
182 | .unmask = pic_unmask_irq, | |
183 | }; | |
184 | ||
185 | static void sic_mask_irq(unsigned int irq) | |
186 | { | |
187 | irq -= IRQ_SIC_START; | |
188 | sic_writel(1 << irq, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR); | |
189 | } | |
190 | ||
191 | static void sic_unmask_irq(unsigned int irq) | |
192 | { | |
193 | irq -= IRQ_SIC_START; | |
194 | sic_writel(1 << irq, INTCP_VA_SIC_BASE + IRQ_ENABLE_SET); | |
195 | } | |
196 | ||
38c677cb DB |
197 | static struct irq_chip sic_chip = { |
198 | .name = "SIC", | |
1da177e4 LT |
199 | .ack = sic_mask_irq, |
200 | .mask = sic_mask_irq, | |
201 | .unmask = sic_unmask_irq, | |
202 | }; | |
203 | ||
204 | static void | |
10dd5ce2 | 205 | sic_handle_irq(unsigned int irq, struct irq_desc *desc) |
1da177e4 LT |
206 | { |
207 | unsigned long status = sic_readl(INTCP_VA_SIC_BASE + IRQ_STATUS); | |
208 | ||
209 | if (status == 0) { | |
0cd61b68 | 210 | do_bad_IRQ(irq, desc); |
1da177e4 LT |
211 | return; |
212 | } | |
213 | ||
214 | do { | |
215 | irq = ffs(status) - 1; | |
216 | status &= ~(1 << irq); | |
217 | ||
218 | irq += IRQ_SIC_START; | |
219 | ||
d8aa0251 | 220 | generic_handle_irq(irq); |
1da177e4 LT |
221 | } while (status); |
222 | } | |
223 | ||
224 | static void __init intcp_init_irq(void) | |
225 | { | |
226 | unsigned int i; | |
227 | ||
228 | /* | |
229 | * Disable all interrupt sources | |
230 | */ | |
231 | pic_writel(0xffffffff, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR); | |
232 | pic_writel(0xffffffff, INTCP_VA_PIC_BASE + FIQ_ENABLE_CLEAR); | |
233 | ||
234 | for (i = IRQ_PIC_START; i <= IRQ_PIC_END; i++) { | |
235 | if (i == 11) | |
236 | i = 22; | |
1da177e4 LT |
237 | if (i == 29) |
238 | break; | |
239 | set_irq_chip(i, &pic_chip); | |
10dd5ce2 | 240 | set_irq_handler(i, handle_level_irq); |
1da177e4 LT |
241 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); |
242 | } | |
243 | ||
244 | cic_writel(0xffffffff, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR); | |
245 | cic_writel(0xffffffff, INTCP_VA_CIC_BASE + FIQ_ENABLE_CLEAR); | |
246 | ||
247 | for (i = IRQ_CIC_START; i <= IRQ_CIC_END; i++) { | |
248 | set_irq_chip(i, &cic_chip); | |
10dd5ce2 | 249 | set_irq_handler(i, handle_level_irq); |
1da177e4 LT |
250 | set_irq_flags(i, IRQF_VALID); |
251 | } | |
252 | ||
253 | sic_writel(0x00000fff, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR); | |
254 | sic_writel(0x00000fff, INTCP_VA_SIC_BASE + FIQ_ENABLE_CLEAR); | |
255 | ||
256 | for (i = IRQ_SIC_START; i <= IRQ_SIC_END; i++) { | |
257 | set_irq_chip(i, &sic_chip); | |
10dd5ce2 | 258 | set_irq_handler(i, handle_level_irq); |
1da177e4 LT |
259 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); |
260 | } | |
261 | ||
56f1319e | 262 | set_irq_chained_handler(IRQ_CP_CPPLDINT, sic_handle_irq); |
1da177e4 LT |
263 | } |
264 | ||
265 | /* | |
266 | * Clock handling | |
267 | */ | |
b830b9b5 RK |
268 | #define CM_LOCK IO_ADDRESS(INTEGRATOR_HDR_LOCK) |
269 | #define CM_AUXOSC IO_ADDRESS(INTEGRATOR_HDR_BASE + 0x1c) | |
1da177e4 | 270 | |
39c0cb02 | 271 | static const struct icst_params cp_auxvco_params = { |
1da177e4 | 272 | .ref = 24000, |
4de2edbd | 273 | .vco_max = ICST525_VCO_MAX_5V, |
1da177e4 LT |
274 | .vd_min = 8, |
275 | .vd_max = 263, | |
276 | .rd_min = 3, | |
277 | .rd_max = 65, | |
278 | }; | |
279 | ||
39c0cb02 | 280 | static void cp_auxvco_set(struct clk *clk, struct icst_vco vco) |
1da177e4 LT |
281 | { |
282 | u32 val; | |
283 | ||
284 | val = readl(CM_AUXOSC) & ~0x7ffff; | |
285 | val |= vco.v | (vco.r << 9) | (vco.s << 16); | |
286 | ||
287 | writel(0xa05f, CM_LOCK); | |
288 | writel(val, CM_AUXOSC); | |
289 | writel(0, CM_LOCK); | |
290 | } | |
291 | ||
d72fbdf0 | 292 | static struct clk cp_auxclk = { |
1da177e4 LT |
293 | .params = &cp_auxvco_params, |
294 | .setvco = cp_auxvco_set, | |
295 | }; | |
296 | ||
d72fbdf0 RK |
297 | static struct clk_lookup cp_lookups[] = { |
298 | { /* CLCD */ | |
299 | .dev_id = "mb:c0", | |
300 | .clk = &cp_auxclk, | |
301 | }, | |
1da177e4 LT |
302 | }; |
303 | ||
304 | /* | |
305 | * Flash handling. | |
306 | */ | |
307 | static int intcp_flash_init(void) | |
308 | { | |
309 | u32 val; | |
310 | ||
311 | val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG); | |
312 | val |= CINTEGRATOR_FLASHPROG_FLWREN; | |
313 | writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG); | |
314 | ||
315 | return 0; | |
316 | } | |
317 | ||
318 | static void intcp_flash_exit(void) | |
319 | { | |
320 | u32 val; | |
321 | ||
322 | val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG); | |
323 | val &= ~(CINTEGRATOR_FLASHPROG_FLVPPEN|CINTEGRATOR_FLASHPROG_FLWREN); | |
324 | writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG); | |
325 | } | |
326 | ||
327 | static void intcp_flash_set_vpp(int on) | |
328 | { | |
329 | u32 val; | |
330 | ||
331 | val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG); | |
332 | if (on) | |
333 | val |= CINTEGRATOR_FLASHPROG_FLVPPEN; | |
334 | else | |
335 | val &= ~CINTEGRATOR_FLASHPROG_FLVPPEN; | |
336 | writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG); | |
337 | } | |
338 | ||
339 | static struct flash_platform_data intcp_flash_data = { | |
340 | .map_name = "cfi_probe", | |
341 | .width = 4, | |
342 | .init = intcp_flash_init, | |
343 | .exit = intcp_flash_exit, | |
344 | .set_vpp = intcp_flash_set_vpp, | |
345 | }; | |
346 | ||
347 | static struct resource intcp_flash_resource = { | |
348 | .start = INTCP_PA_FLASH_BASE, | |
349 | .end = INTCP_PA_FLASH_BASE + INTCP_FLASH_SIZE - 1, | |
350 | .flags = IORESOURCE_MEM, | |
351 | }; | |
352 | ||
353 | static struct platform_device intcp_flash_device = { | |
354 | .name = "armflash", | |
355 | .id = 0, | |
356 | .dev = { | |
357 | .platform_data = &intcp_flash_data, | |
358 | }, | |
359 | .num_resources = 1, | |
360 | .resource = &intcp_flash_resource, | |
361 | }; | |
362 | ||
363 | static struct resource smc91x_resources[] = { | |
364 | [0] = { | |
da7ba956 RK |
365 | .start = INTEGRATOR_CP_ETH_BASE, |
366 | .end = INTEGRATOR_CP_ETH_BASE + INTCP_ETH_SIZE - 1, | |
1da177e4 LT |
367 | .flags = IORESOURCE_MEM, |
368 | }, | |
369 | [1] = { | |
370 | .start = IRQ_CP_ETHINT, | |
371 | .end = IRQ_CP_ETHINT, | |
372 | .flags = IORESOURCE_IRQ, | |
373 | }, | |
374 | }; | |
375 | ||
376 | static struct platform_device smc91x_device = { | |
377 | .name = "smc91x", | |
378 | .id = 0, | |
379 | .num_resources = ARRAY_SIZE(smc91x_resources), | |
380 | .resource = smc91x_resources, | |
381 | }; | |
382 | ||
383 | static struct platform_device *intcp_devs[] __initdata = { | |
384 | &intcp_flash_device, | |
385 | &smc91x_device, | |
386 | }; | |
387 | ||
388 | /* | |
389 | * It seems that the card insertion interrupt remains active after | |
390 | * we've acknowledged it. We therefore ignore the interrupt, and | |
391 | * rely on reading it from the SIC. This also means that we must | |
392 | * clear the latched interrupt. | |
393 | */ | |
394 | static unsigned int mmc_status(struct device *dev) | |
395 | { | |
b830b9b5 RK |
396 | unsigned int status = readl(IO_ADDRESS(0xca000000 + 4)); |
397 | writel(8, IO_ADDRESS(INTEGRATOR_CP_CTL_BASE + 8)); | |
1da177e4 LT |
398 | |
399 | return status & 8; | |
400 | } | |
401 | ||
6ef297f8 | 402 | static struct mmci_platform_data mmc_data = { |
1da177e4 LT |
403 | .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, |
404 | .status = mmc_status, | |
7fb2bbf4 RK |
405 | .gpio_wp = -1, |
406 | .gpio_cd = -1, | |
1da177e4 LT |
407 | }; |
408 | ||
409 | static struct amba_device mmc_device = { | |
410 | .dev = { | |
1d559e29 | 411 | .init_name = "mb:1c", |
1da177e4 LT |
412 | .platform_data = &mmc_data, |
413 | }, | |
414 | .res = { | |
da7ba956 RK |
415 | .start = INTEGRATOR_CP_MMC_BASE, |
416 | .end = INTEGRATOR_CP_MMC_BASE + SZ_4K - 1, | |
1da177e4 LT |
417 | .flags = IORESOURCE_MEM, |
418 | }, | |
419 | .irq = { IRQ_CP_MMCIINT0, IRQ_CP_MMCIINT1 }, | |
420 | .periphid = 0, | |
421 | }; | |
422 | ||
423 | static struct amba_device aaci_device = { | |
424 | .dev = { | |
1d559e29 | 425 | .init_name = "mb:1d", |
1da177e4 LT |
426 | }, |
427 | .res = { | |
da7ba956 RK |
428 | .start = INTEGRATOR_CP_AACI_BASE, |
429 | .end = INTEGRATOR_CP_AACI_BASE + SZ_4K - 1, | |
1da177e4 LT |
430 | .flags = IORESOURCE_MEM, |
431 | }, | |
432 | .irq = { IRQ_CP_AACIINT, NO_IRQ }, | |
433 | .periphid = 0, | |
434 | }; | |
435 | ||
436 | ||
437 | /* | |
438 | * CLCD support | |
439 | */ | |
440 | static struct clcd_panel vga = { | |
441 | .mode = { | |
442 | .name = "VGA", | |
443 | .refresh = 60, | |
444 | .xres = 640, | |
445 | .yres = 480, | |
446 | .pixclock = 39721, | |
447 | .left_margin = 40, | |
448 | .right_margin = 24, | |
449 | .upper_margin = 32, | |
450 | .lower_margin = 11, | |
451 | .hsync_len = 96, | |
452 | .vsync_len = 2, | |
453 | .sync = 0, | |
454 | .vmode = FB_VMODE_NONINTERLACED, | |
455 | }, | |
456 | .width = -1, | |
457 | .height = -1, | |
458 | .tim2 = TIM2_BCD | TIM2_IPC, | |
459 | .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1), | |
460 | .bpp = 16, | |
461 | .grayscale = 0, | |
462 | }; | |
463 | ||
464 | /* | |
465 | * Ensure VGA is selected. | |
466 | */ | |
467 | static void cp_clcd_enable(struct clcd_fb *fb) | |
468 | { | |
4774e226 RK |
469 | u32 val; |
470 | ||
471 | if (fb->fb.var.bits_per_pixel <= 8) | |
472 | val = CM_CTRL_LCDMUXSEL_VGA_8421BPP; | |
473 | else if (fb->fb.var.bits_per_pixel <= 16) | |
14e54cc3 CM |
474 | val = CM_CTRL_LCDMUXSEL_VGA_16BPP |
475 | | CM_CTRL_LCDEN0 | CM_CTRL_LCDEN1 | |
476 | | CM_CTRL_STATIC1 | CM_CTRL_STATIC2; | |
4774e226 RK |
477 | else |
478 | val = 0; /* no idea for this, don't trust the docs */ | |
479 | ||
480 | cm_control(CM_CTRL_LCDMUXSEL_MASK| | |
481 | CM_CTRL_LCDEN0| | |
482 | CM_CTRL_LCDEN1| | |
483 | CM_CTRL_STATIC1| | |
484 | CM_CTRL_STATIC2| | |
485 | CM_CTRL_STATIC| | |
486 | CM_CTRL_n24BITEN, val); | |
1da177e4 LT |
487 | } |
488 | ||
489 | static unsigned long framesize = SZ_1M; | |
490 | ||
491 | static int cp_clcd_setup(struct clcd_fb *fb) | |
492 | { | |
493 | dma_addr_t dma; | |
494 | ||
495 | fb->panel = &vga; | |
496 | ||
497 | fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize, | |
498 | &dma, GFP_KERNEL); | |
499 | if (!fb->fb.screen_base) { | |
500 | printk(KERN_ERR "CLCD: unable to map framebuffer\n"); | |
501 | return -ENOMEM; | |
502 | } | |
503 | ||
504 | fb->fb.fix.smem_start = dma; | |
505 | fb->fb.fix.smem_len = framesize; | |
506 | ||
507 | return 0; | |
508 | } | |
509 | ||
510 | static int cp_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma) | |
511 | { | |
512 | return dma_mmap_writecombine(&fb->dev->dev, vma, | |
513 | fb->fb.screen_base, | |
514 | fb->fb.fix.smem_start, | |
515 | fb->fb.fix.smem_len); | |
516 | } | |
517 | ||
518 | static void cp_clcd_remove(struct clcd_fb *fb) | |
519 | { | |
520 | dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len, | |
521 | fb->fb.screen_base, fb->fb.fix.smem_start); | |
522 | } | |
523 | ||
524 | static struct clcd_board clcd_data = { | |
525 | .name = "Integrator/CP", | |
526 | .check = clcdfb_check, | |
527 | .decode = clcdfb_decode, | |
528 | .enable = cp_clcd_enable, | |
529 | .setup = cp_clcd_setup, | |
530 | .mmap = cp_clcd_mmap, | |
531 | .remove = cp_clcd_remove, | |
532 | }; | |
533 | ||
534 | static struct amba_device clcd_device = { | |
535 | .dev = { | |
1d559e29 | 536 | .init_name = "mb:c0", |
1da177e4 LT |
537 | .coherent_dma_mask = ~0, |
538 | .platform_data = &clcd_data, | |
539 | }, | |
540 | .res = { | |
541 | .start = INTCP_PA_CLCD_BASE, | |
542 | .end = INTCP_PA_CLCD_BASE + SZ_4K - 1, | |
543 | .flags = IORESOURCE_MEM, | |
544 | }, | |
545 | .dma_mask = ~0, | |
546 | .irq = { IRQ_CP_CLCDCINT, NO_IRQ }, | |
547 | .periphid = 0, | |
548 | }; | |
549 | ||
550 | static struct amba_device *amba_devs[] __initdata = { | |
551 | &mmc_device, | |
552 | &aaci_device, | |
553 | &clcd_device, | |
554 | }; | |
555 | ||
556 | static void __init intcp_init(void) | |
557 | { | |
558 | int i; | |
559 | ||
0a0300dc | 560 | clkdev_add_table(cp_lookups, ARRAY_SIZE(cp_lookups)); |
1da177e4 LT |
561 | platform_add_devices(intcp_devs, ARRAY_SIZE(intcp_devs)); |
562 | ||
563 | for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { | |
564 | struct amba_device *d = amba_devs[i]; | |
565 | amba_device_register(d, &iomem_resource); | |
566 | } | |
567 | } | |
568 | ||
569 | #define TIMER_CTRL_IE (1 << 5) /* Interrupt Enable */ | |
570 | ||
571 | static void __init intcp_timer_init(void) | |
572 | { | |
861248d1 | 573 | integrator_time_init(1000, TIMER_CTRL_IE); |
1da177e4 LT |
574 | } |
575 | ||
576 | static struct sys_timer cp_timer = { | |
577 | .init = intcp_timer_init, | |
1da177e4 LT |
578 | }; |
579 | ||
580 | MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP") | |
e9dea0c6 | 581 | /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ |
e9dea0c6 RK |
582 | .phys_io = 0x16000000, |
583 | .io_pg_offst = ((0xf1600000) >> 18) & 0xfffc, | |
584 | .boot_params = 0x00000100, | |
585 | .map_io = intcp_map_io, | |
586 | .init_irq = intcp_init_irq, | |
1da177e4 | 587 | .timer = &cp_timer, |
e9dea0c6 | 588 | .init_machine = intcp_init, |
1da177e4 | 589 | MACHINE_END |