[mirror_ubuntu-zesty-kernel.git] / arch / arm / mach-integrator / integrator_cp.c

/*
 *  linux/arch/arm/mach-integrator/integrator_cp.c
 *
 *  Copyright (C) 2003 Deep Blue Solutions Ltd
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License.
 */
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/list.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/string.h>
#include <linux/device.h>
#include <linux/amba/bus.h>
#include <linux/amba/kmi.h>
#include <linux/amba/clcd.h>
#include <linux/amba/mmci.h>
#include <linux/io.h>
#include <linux/gfp.h>
#include <linux/mtd/physmap.h>
#include <linux/platform_data/clk-integrator.h>

#include <mach/hardware.h>
#include <mach/platform.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/hardware/arm_timer.h>
#include <asm/hardware/icst.h>

#include <mach/cm.h>
#include <mach/lm.h>
#include <mach/irqs.h>

#include <asm/mach/arch.h>
#include <asm/mach/irq.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>

#include <asm/hardware/timer-sp.h>

#include <plat/clcd.h>
#include <plat/fpga-irq.h>
#include <plat/sched_clock.h>

#include "common.h"

#define INTCP_PA_FLASH_BASE		0x24000000
#define INTCP_FLASH_SIZE		SZ_32M

#define INTCP_PA_CLCD_BASE		0xc0000000

#define INTCP_VA_CIC_BASE		__io_address(INTEGRATOR_HDR_BASE + 0x40)
#define INTCP_VA_PIC_BASE		__io_address(INTEGRATOR_IC_BASE)
#define INTCP_VA_SIC_BASE		__io_address(INTEGRATOR_CP_SIC_BASE)

#define INTCP_ETH_SIZE			0x10

#define INTCP_VA_CTRL_BASE		IO_ADDRESS(INTEGRATOR_CP_CTL_BASE)
#define INTCP_FLASHPROG			0x04
#define CINTEGRATOR_FLASHPROG_FLVPPEN	(1 << 0)
#define CINTEGRATOR_FLASHPROG_FLWREN	(1 << 1)

/*
 * Logical      Physical
 * f1000000	10000000	Core module registers
 * f1100000	11000000	System controller registers
 * f1200000	12000000	EBI registers
 * f1300000	13000000	Counter/Timer
 * f1400000	14000000	Interrupt controller
 * f1600000	16000000	UART 0
 * f1700000	17000000	UART 1
 * f1a00000	1a000000	Debug LEDs
 * fc900000	c9000000	GPIO
 * fca00000	ca000000	SIC
 * fcb00000	cb000000	CP system control
 */

static struct map_desc intcp_io_desc[] __initdata = {
	{
		.virtual	= IO_ADDRESS(INTEGRATOR_HDR_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_HDR_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_SC_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_SC_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_EBI_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_EBI_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_CT_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_CT_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_IC_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_IC_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_UART0_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_UART0_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_UART1_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_UART1_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_DBG_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_DBG_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_CP_GPIO_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_CP_GPIO_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_CP_SIC_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_CP_SIC_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_CP_CTL_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_CP_CTL_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}
};

static void __init intcp_map_io(void)
{
	iotable_init(intcp_io_desc, ARRAY_SIZE(intcp_io_desc));
}

static void __init intcp_init_irq(void)
{
	u32 pic_mask, cic_mask, sic_mask;

	/* These masks are for the HW IRQ registers */
	pic_mask = ~((~0u) << (11 - IRQ_PIC_START));
	pic_mask |= (~((~0u) << (29 - 22))) << 22;
	cic_mask = ~((~0u) << (1 + IRQ_CIC_END - IRQ_CIC_START));
	sic_mask = ~((~0u) << (1 + IRQ_SIC_END - IRQ_SIC_START));

	/*
	 * Disable all interrupt sources
	 */
	writel(0xffffffff, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR);
	writel(0xffffffff, INTCP_VA_PIC_BASE + FIQ_ENABLE_CLEAR);
	writel(0xffffffff, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR);
	writel(0xffffffff, INTCP_VA_CIC_BASE + FIQ_ENABLE_CLEAR);
	writel(sic_mask, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR);
	writel(sic_mask, INTCP_VA_SIC_BASE + FIQ_ENABLE_CLEAR);

	fpga_irq_init(INTCP_VA_PIC_BASE, "PIC", IRQ_PIC_START,
		      -1, pic_mask, NULL);

	fpga_irq_init(INTCP_VA_CIC_BASE, "CIC", IRQ_CIC_START,
		      -1, cic_mask, NULL);

	fpga_irq_init(INTCP_VA_SIC_BASE, "SIC", IRQ_SIC_START,
		      IRQ_CP_CPPLDINT, sic_mask, NULL);
	integrator_clk_init(true);
}

/*
 * Flash handling.
 */
static int intcp_flash_init(struct platform_device *dev)
{
	u32 val;

	val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
	val |= CINTEGRATOR_FLASHPROG_FLWREN;
	writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);

	return 0;
}

static void intcp_flash_exit(struct platform_device *dev)
{
	u32 val;

	val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
	val &= ~(CINTEGRATOR_FLASHPROG_FLVPPEN|CINTEGRATOR_FLASHPROG_FLWREN);
	writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
}

static void intcp_flash_set_vpp(struct platform_device *pdev, int on)
{
	u32 val;

	val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
	if (on)
		val |= CINTEGRATOR_FLASHPROG_FLVPPEN;
	else
		val &= ~CINTEGRATOR_FLASHPROG_FLVPPEN;
	writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
}

static struct physmap_flash_data intcp_flash_data = {
	.width		= 4,
	.init		= intcp_flash_init,
	.exit		= intcp_flash_exit,
	.set_vpp	= intcp_flash_set_vpp,
};

static struct resource intcp_flash_resource = {
	.start		= INTCP_PA_FLASH_BASE,
	.end		= INTCP_PA_FLASH_BASE + INTCP_FLASH_SIZE - 1,
	.flags		= IORESOURCE_MEM,
};

static struct platform_device intcp_flash_device = {
	.name		= "physmap-flash",
	.id		= 0,
	.dev		= {
		.platform_data	= &intcp_flash_data,
	},
	.num_resources	= 1,
	.resource	= &intcp_flash_resource,
};

static struct resource smc91x_resources[] = {
	[0] = {
		.start	= INTEGRATOR_CP_ETH_BASE,
		.end	= INTEGRATOR_CP_ETH_BASE + INTCP_ETH_SIZE - 1,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= IRQ_CP_ETHINT,
		.end	= IRQ_CP_ETHINT,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device smc91x_device = {
	.name		= "smc91x",
	.id		= 0,
	.num_resources	= ARRAY_SIZE(smc91x_resources),
	.resource	= smc91x_resources,
};

static struct platform_device *intcp_devs[] __initdata = {
	&intcp_flash_device,
	&smc91x_device,
};

/*
 * It seems that the card insertion interrupt remains active after
 * we've acknowledged it.  We therefore ignore the interrupt, and
 * rely on reading it from the SIC.  This also means that we must
 * clear the latched interrupt.
 */
static unsigned int mmc_status(struct device *dev)
{
	unsigned int status = readl(IO_ADDRESS(0xca000000 + 4));
	writel(8, IO_ADDRESS(INTEGRATOR_CP_CTL_BASE + 8));

	return status & 8;
}

static struct mmci_platform_data mmc_data = {
	.ocr_mask	= MMC_VDD_32_33|MMC_VDD_33_34,
	.status		= mmc_status,
	.gpio_wp	= -1,
	.gpio_cd	= -1,
};

#define INTEGRATOR_CP_MMC_IRQS	{ IRQ_CP_MMCIINT0, IRQ_CP_MMCIINT1 }
#define INTEGRATOR_CP_AACI_IRQS	{ IRQ_CP_AACIINT }

static AMBA_APB_DEVICE(mmc, "mmci", 0, INTEGRATOR_CP_MMC_BASE,
	INTEGRATOR_CP_MMC_IRQS, &mmc_data);

static AMBA_APB_DEVICE(aaci, "aaci", 0, INTEGRATOR_CP_AACI_BASE,
	INTEGRATOR_CP_AACI_IRQS, NULL);


/*
 * CLCD support
 */
/*
 * Ensure VGA is selected.
 */
static void cp_clcd_enable(struct clcd_fb *fb)
{
	struct fb_var_screeninfo *var = &fb->fb.var;
	u32 val = CM_CTRL_STATIC1 | CM_CTRL_STATIC2;

	if (var->bits_per_pixel <= 8 ||
	    (var->bits_per_pixel == 16 && var->green.length == 5))
		/* Pseudocolor, RGB555, BGR555 */
		val |= CM_CTRL_LCDMUXSEL_VGA555_TFT555;
	else if (fb->fb.var.bits_per_pixel <= 16)
		/* truecolor RGB565 */
		val |= CM_CTRL_LCDMUXSEL_VGA565_TFT555;
	else
		val = 0; /* no idea for this, don't trust the docs */

	cm_control(CM_CTRL_LCDMUXSEL_MASK|
		   CM_CTRL_LCDEN0|
		   CM_CTRL_LCDEN1|
		   CM_CTRL_STATIC1|
		   CM_CTRL_STATIC2|
		   CM_CTRL_STATIC|
		   CM_CTRL_n24BITEN, val);
}

static int cp_clcd_setup(struct clcd_fb *fb)
{
	fb->panel = versatile_clcd_get_panel("VGA");
	if (!fb->panel)
		return -EINVAL;

	return versatile_clcd_setup_dma(fb, SZ_1M);
}

static struct clcd_board clcd_data = {
	.name		= "Integrator/CP",
	.caps		= CLCD_CAP_5551 | CLCD_CAP_RGB565 | CLCD_CAP_888,
	.check		= clcdfb_check,
	.decode		= clcdfb_decode,
	.enable		= cp_clcd_enable,
	.setup		= cp_clcd_setup,
	.mmap		= versatile_clcd_mmap_dma,
	.remove		= versatile_clcd_remove_dma,
};

static AMBA_AHB_DEVICE(clcd, "clcd", 0, INTCP_PA_CLCD_BASE,
	{ IRQ_CP_CLCDCINT }, &clcd_data);

static struct amba_device *amba_devs[] __initdata = {
	&mmc_device,
	&aaci_device,
	&clcd_device,
};

#define REFCOUNTER (__io_address(INTEGRATOR_HDR_BASE) + 0x28)

static void __init intcp_init_early(void)
{
#ifdef CONFIG_PLAT_VERSATILE_SCHED_CLOCK
	versatile_sched_clock_init(REFCOUNTER, 24000000);
#endif
}

static void __init intcp_init(void)
{
	int i;

	platform_add_devices(intcp_devs, ARRAY_SIZE(intcp_devs));

	for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
		struct amba_device *d = amba_devs[i];
		amba_device_register(d, &iomem_resource);
	}
	integrator_init(true);
}

#define TIMER0_VA_BASE __io_address(INTEGRATOR_TIMER0_BASE)
#define TIMER1_VA_BASE __io_address(INTEGRATOR_TIMER1_BASE)
#define TIMER2_VA_BASE __io_address(INTEGRATOR_TIMER2_BASE)

static void __init intcp_timer_init(void)
{
	writel(0, TIMER0_VA_BASE + TIMER_CTRL);
	writel(0, TIMER1_VA_BASE + TIMER_CTRL);
	writel(0, TIMER2_VA_BASE + TIMER_CTRL);

	sp804_clocksource_init(TIMER2_VA_BASE, "timer2");
	sp804_clockevents_init(TIMER1_VA_BASE, IRQ_TIMERINT1, "timer1");
}

static struct sys_timer cp_timer = {
	.init		= intcp_timer_init,
};

MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP")
	/* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
	.atag_offset	= 0x100,
	.reserve	= integrator_reserve,
	.map_io		= intcp_map_io,
	.nr_irqs	= NR_IRQS_INTEGRATOR_CP,
	.init_early	= intcp_init_early,
	.init_irq	= intcp_init_irq,
	.handle_irq	= fpga_handle_irq,
	.timer		= &cp_timer,
	.init_machine	= intcp_init,
	.restart	= integrator_restart,
MACHINE_END
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mach-integrator/integrator_cp.c
	3	*
	4	* Copyright (C) 2003 Deep Blue Solutions Ltd
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License.
	9	*/
	10	#include <linux/types.h>
	11	#include <linux/kernel.h>
	12	#include <linux/init.h>
	13	#include <linux/list.h>
d052d1be	14	#include <linux/platform_device.h>
1da177e4	15	#include <linux/dma-mapping.h>
1da177e4	16	#include <linux/string.h>
edbaa603	17	#include <linux/device.h>
a62c80e5 RK	18	#include <linux/amba/bus.h>
	19	#include <linux/amba/kmi.h>
	20	#include <linux/amba/clcd.h>
6ef297f8	21	#include <linux/amba/mmci.h>
fced80c7	22	#include <linux/io.h>
5a0e3ad6	23	#include <linux/gfp.h>
046dfa0a	24	#include <linux/mtd/physmap.h>
a613163d	25	#include <linux/platform_data/clk-integrator.h>
1da177e4	26
a09e64fb	27	#include <mach/hardware.h>
a285edcf	28	#include <mach/platform.h>
1da177e4 LT	29	#include <asm/setup.h>
1da177e4 LT	30	#include <asm/mach-types.h>
5a46334a	31	#include <asm/hardware/arm_timer.h>
c5a0adb5	32	#include <asm/hardware/icst.h>
1da177e4	33
a09e64fb RK	34	#include <mach/cm.h>
a09e64fb RK	35	#include <mach/lm.h>
695436e3	36	#include <mach/irqs.h>
1da177e4 LT	37
1da177e4 LT	38	#include <asm/mach/arch.h>
1da177e4	39	#include <asm/mach/irq.h>
1da177e4 LT	40	#include <asm/mach/map.h>
	41	#include <asm/mach/time.h>
	42
8a9618f5	43	#include <asm/hardware/timer-sp.h>
5a46334a	44
9dfec4fe	45	#include <plat/clcd.h>
c41b16f8	46	#include <plat/fpga-irq.h>
d77e270c	47	#include <plat/sched_clock.h>
9dfec4fe	48
98c672cf RK	49	#include "common.h"
98c672cf RK	50
1da177e4 LT	51	#define INTCP_PA_FLASH_BASE 0x24000000
	52	#define INTCP_FLASH_SIZE SZ_32M
	53
	54	#define INTCP_PA_CLCD_BASE 0xc0000000
	55
c41b16f8 RK	56	#define INTCP_VA_CIC_BASE __io_address(INTEGRATOR_HDR_BASE + 0x40)
	57	#define INTCP_VA_PIC_BASE __io_address(INTEGRATOR_IC_BASE)
	58	#define INTCP_VA_SIC_BASE __io_address(INTEGRATOR_CP_SIC_BASE)
1da177e4	59
1da177e4 LT	60	#define INTCP_ETH_SIZE 0x10
1da177e4 LT	61
da7ba956	62	#define INTCP_VA_CTRL_BASE IO_ADDRESS(INTEGRATOR_CP_CTL_BASE)
1da177e4 LT	63	#define INTCP_FLASHPROG 0x04
	64	#define CINTEGRATOR_FLASHPROG_FLVPPEN (1 << 0)
	65	#define CINTEGRATOR_FLASHPROG_FLWREN (1 << 1)
	66
	67	/*
	68	* Logical Physical
	69	* f1000000 10000000 Core module registers
	70	* f1100000 11000000 System controller registers
	71	* f1200000 12000000 EBI registers
	72	* f1300000 13000000 Counter/Timer
	73	* f1400000 14000000 Interrupt controller
	74	* f1600000 16000000 UART 0
	75	* f1700000 17000000 UART 1
	76	* f1a00000 1a000000 Debug LEDs
da7ba956 RK	77	* fc900000 c9000000 GPIO
	78	* fca00000 ca000000 SIC
	79	* fcb00000 cb000000 CP system control
1da177e4 LT	80	*/
	81
	82	static struct map_desc intcp_io_desc[] __initdata = {
c8d27298 DS	83	{
	84	.virtual = IO_ADDRESS(INTEGRATOR_HDR_BASE),
	85	.pfn = __phys_to_pfn(INTEGRATOR_HDR_BASE),
	86	.length = SZ_4K,
	87	.type = MT_DEVICE
	88	}, {
	89	.virtual = IO_ADDRESS(INTEGRATOR_SC_BASE),
	90	.pfn = __phys_to_pfn(INTEGRATOR_SC_BASE),
	91	.length = SZ_4K,
	92	.type = MT_DEVICE
	93	}, {
	94	.virtual = IO_ADDRESS(INTEGRATOR_EBI_BASE),
	95	.pfn = __phys_to_pfn(INTEGRATOR_EBI_BASE),
	96	.length = SZ_4K,
	97	.type = MT_DEVICE
	98	}, {
	99	.virtual = IO_ADDRESS(INTEGRATOR_CT_BASE),
	100	.pfn = __phys_to_pfn(INTEGRATOR_CT_BASE),
	101	.length = SZ_4K,
	102	.type = MT_DEVICE
	103	}, {
	104	.virtual = IO_ADDRESS(INTEGRATOR_IC_BASE),
	105	.pfn = __phys_to_pfn(INTEGRATOR_IC_BASE),
	106	.length = SZ_4K,
	107	.type = MT_DEVICE
	108	}, {
	109	.virtual = IO_ADDRESS(INTEGRATOR_UART0_BASE),
	110	.pfn = __phys_to_pfn(INTEGRATOR_UART0_BASE),
	111	.length = SZ_4K,
	112	.type = MT_DEVICE
	113	}, {
	114	.virtual = IO_ADDRESS(INTEGRATOR_UART1_BASE),
	115	.pfn = __phys_to_pfn(INTEGRATOR_UART1_BASE),
	116	.length = SZ_4K,
	117	.type = MT_DEVICE
	118	}, {
	119	.virtual = IO_ADDRESS(INTEGRATOR_DBG_BASE),
	120	.pfn = __phys_to_pfn(INTEGRATOR_DBG_BASE),
	121	.length = SZ_4K,
	122	.type = MT_DEVICE
	123	}, {
da7ba956 RK	124	.virtual = IO_ADDRESS(INTEGRATOR_CP_GPIO_BASE),
da7ba956 RK	125	.pfn = __phys_to_pfn(INTEGRATOR_CP_GPIO_BASE),
c8d27298 DS	126	.length = SZ_4K,
	127	.type = MT_DEVICE
	128	}, {
da7ba956 RK	129	.virtual = IO_ADDRESS(INTEGRATOR_CP_SIC_BASE),
da7ba956 RK	130	.pfn = __phys_to_pfn(INTEGRATOR_CP_SIC_BASE),
c8d27298 DS	131	.length = SZ_4K,
	132	.type = MT_DEVICE
	133	}, {
da7ba956 RK	134	.virtual = IO_ADDRESS(INTEGRATOR_CP_CTL_BASE),
da7ba956 RK	135	.pfn = __phys_to_pfn(INTEGRATOR_CP_CTL_BASE),
c8d27298 DS	136	.length = SZ_4K,
	137	.type = MT_DEVICE
	138	}
1da177e4 LT	139	};
	140
	141	static void __init intcp_map_io(void)
	142	{
	143	iotable_init(intcp_io_desc, ARRAY_SIZE(intcp_io_desc));
	144	}
	145
1da177e4 LT	146	static void __init intcp_init_irq(void)
1da177e4 LT	147	{
3108e6ab	148	u32 pic_mask, cic_mask, sic_mask;
c41b16f8	149
3108e6ab	150	/* These masks are for the HW IRQ registers */
c41b16f8 RK	151	pic_mask = ~((~0u) << (11 - IRQ_PIC_START));
c41b16f8 RK	152	pic_mask \|= (~((~0u) << (29 - 22))) << 22;
3108e6ab	153	cic_mask = ~((~0u) << (1 + IRQ_CIC_END - IRQ_CIC_START));
c41b16f8	154	sic_mask = ~((~0u) << (1 + IRQ_SIC_END - IRQ_SIC_START));
1da177e4 LT	155
	156	/*
	157	* Disable all interrupt sources
	158	*/
c41b16f8 RK	159	writel(0xffffffff, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR);
	160	writel(0xffffffff, INTCP_VA_PIC_BASE + FIQ_ENABLE_CLEAR);
	161	writel(0xffffffff, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR);
	162	writel(0xffffffff, INTCP_VA_CIC_BASE + FIQ_ENABLE_CLEAR);
	163	writel(sic_mask, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR);
	164	writel(sic_mask, INTCP_VA_SIC_BASE + FIQ_ENABLE_CLEAR);
1da177e4	165
3108e6ab LW	166	fpga_irq_init(INTCP_VA_PIC_BASE, "PIC", IRQ_PIC_START,
3108e6ab LW	167	-1, pic_mask, NULL);
1da177e4	168
3108e6ab LW	169	fpga_irq_init(INTCP_VA_CIC_BASE, "CIC", IRQ_CIC_START,
3108e6ab LW	170	-1, cic_mask, NULL);
1da177e4	171
3108e6ab LW	172	fpga_irq_init(INTCP_VA_SIC_BASE, "SIC", IRQ_SIC_START,
3108e6ab LW	173	IRQ_CP_CPPLDINT, sic_mask, NULL);
a613163d	174	integrator_clk_init(true);
1da177e4 LT	175	}
1da177e4 LT	176
1da177e4 LT	177	/*
	178	* Flash handling.
	179	*/
046dfa0a	180	static int intcp_flash_init(struct platform_device *dev)
1da177e4 LT	181	{
	182	u32 val;
	183
	184	val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
	185	val \|= CINTEGRATOR_FLASHPROG_FLWREN;
	186	writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
	187
	188	return 0;
	189	}
	190
046dfa0a	191	static void intcp_flash_exit(struct platform_device *dev)
1da177e4 LT	192	{
	193	u32 val;
	194
	195	val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
	196	val &= ~(CINTEGRATOR_FLASHPROG_FLVPPEN\|CINTEGRATOR_FLASHPROG_FLWREN);
	197	writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
	198	}
	199
667f390b	200	static void intcp_flash_set_vpp(struct platform_device *pdev, int on)
1da177e4 LT	201	{
	202	u32 val;
	203
	204	val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
	205	if (on)
	206	val \|= CINTEGRATOR_FLASHPROG_FLVPPEN;
	207	else
	208	val &= ~CINTEGRATOR_FLASHPROG_FLVPPEN;
	209	writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
	210	}
	211
046dfa0a	212	static struct physmap_flash_data intcp_flash_data = {
1da177e4 LT	213	.width = 4,
	214	.init = intcp_flash_init,
	215	.exit = intcp_flash_exit,
	216	.set_vpp = intcp_flash_set_vpp,
	217	};
	218
	219	static struct resource intcp_flash_resource = {
	220	.start = INTCP_PA_FLASH_BASE,
	221	.end = INTCP_PA_FLASH_BASE + INTCP_FLASH_SIZE - 1,
	222	.flags = IORESOURCE_MEM,
	223	};
	224
	225	static struct platform_device intcp_flash_device = {
046dfa0a	226	.name = "physmap-flash",
1da177e4 LT	227	.id = 0,
	228	.dev = {
	229	.platform_data = &intcp_flash_data,
	230	},
	231	.num_resources = 1,
	232	.resource = &intcp_flash_resource,
	233	};
	234
	235	static struct resource smc91x_resources[] = {
	236	[0] = {
da7ba956 RK	237	.start = INTEGRATOR_CP_ETH_BASE,
da7ba956 RK	238	.end = INTEGRATOR_CP_ETH_BASE + INTCP_ETH_SIZE - 1,
1da177e4 LT	239	.flags = IORESOURCE_MEM,
	240	},
	241	[1] = {
	242	.start = IRQ_CP_ETHINT,
	243	.end = IRQ_CP_ETHINT,
	244	.flags = IORESOURCE_IRQ,
	245	},
	246	};
	247
	248	static struct platform_device smc91x_device = {
	249	.name = "smc91x",
	250	.id = 0,
	251	.num_resources = ARRAY_SIZE(smc91x_resources),
	252	.resource = smc91x_resources,
	253	};
	254
	255	static struct platform_device *intcp_devs[] __initdata = {
	256	&intcp_flash_device,
	257	&smc91x_device,
	258	};
	259
	260	/*
	261	* It seems that the card insertion interrupt remains active after
	262	* we've acknowledged it. We therefore ignore the interrupt, and
	263	* rely on reading it from the SIC. This also means that we must
	264	* clear the latched interrupt.
	265	*/
	266	static unsigned int mmc_status(struct device *dev)
	267	{
b830b9b5 RK	268	unsigned int status = readl(IO_ADDRESS(0xca000000 + 4));
b830b9b5 RK	269	writel(8, IO_ADDRESS(INTEGRATOR_CP_CTL_BASE + 8));
1da177e4 LT	270
	271	return status & 8;
	272	}
	273
6ef297f8	274	static struct mmci_platform_data mmc_data = {
1da177e4 LT	275	.ocr_mask = MMC_VDD_32_33\|MMC_VDD_33_34,
1da177e4 LT	276	.status = mmc_status,
7fb2bbf4 RK	277	.gpio_wp = -1,
7fb2bbf4 RK	278	.gpio_cd = -1,
1da177e4 LT	279	};
1da177e4 LT	280
2f64ccd9 RK	281	#define INTEGRATOR_CP_MMC_IRQS { IRQ_CP_MMCIINT0, IRQ_CP_MMCIINT1 }
2f64ccd9 RK	282	#define INTEGRATOR_CP_AACI_IRQS { IRQ_CP_AACIINT }
1da177e4	283
d59fdcfc	284	static AMBA_APB_DEVICE(mmc, "mmci", 0, INTEGRATOR_CP_MMC_BASE,
2f64ccd9 RK	285	INTEGRATOR_CP_MMC_IRQS, &mmc_data);
2f64ccd9 RK	286
d59fdcfc	287	static AMBA_APB_DEVICE(aaci, "aaci", 0, INTEGRATOR_CP_AACI_BASE,
2f64ccd9	288	INTEGRATOR_CP_AACI_IRQS, NULL);
1da177e4 LT	289
	290
	291	/*
	292	* CLCD support
	293	*/
1da177e4 LT	294	/*
	295	* Ensure VGA is selected.
	296	*/
	297	static void cp_clcd_enable(struct clcd_fb *fb)
	298	{
e6b9c1f8 RK	299	struct fb_var_screeninfo *var = &fb->fb.var;
e6b9c1f8 RK	300	u32 val = CM_CTRL_STATIC1 \| CM_CTRL_STATIC2;
4774e226	301
e6b9c1f8 RK	302	if (var->bits_per_pixel <= 8 \|\|
	303	(var->bits_per_pixel == 16 && var->green.length == 5))
	304	/* Pseudocolor, RGB555, BGR555 */
	305	val \|= CM_CTRL_LCDMUXSEL_VGA555_TFT555;
4774e226	306	else if (fb->fb.var.bits_per_pixel <= 16)
e6b9c1f8 RK	307	/* truecolor RGB565 */
e6b9c1f8 RK	308	val \|= CM_CTRL_LCDMUXSEL_VGA565_TFT555;
4774e226 RK	309	else
	310	val = 0; /* no idea for this, don't trust the docs */
	311
	312	cm_control(CM_CTRL_LCDMUXSEL_MASK\|
	313	CM_CTRL_LCDEN0\|
	314	CM_CTRL_LCDEN1\|
	315	CM_CTRL_STATIC1\|
	316	CM_CTRL_STATIC2\|
	317	CM_CTRL_STATIC\|
	318	CM_CTRL_n24BITEN, val);
1da177e4 LT	319	}
1da177e4 LT	320
1da177e4 LT	321	static int cp_clcd_setup(struct clcd_fb *fb)
1da177e4 LT	322	{
9dfec4fe RK	323	fb->panel = versatile_clcd_get_panel("VGA");
	324	if (!fb->panel)
	325	return -EINVAL;
1da177e4	326
9dfec4fe	327	return versatile_clcd_setup_dma(fb, SZ_1M);
1da177e4 LT	328	}
	329
	330	static struct clcd_board clcd_data = {
	331	.name = "Integrator/CP",
9dfec4fe	332	.caps = CLCD_CAP_5551 \| CLCD_CAP_RGB565 \| CLCD_CAP_888,
1da177e4 LT	333	.check = clcdfb_check,
	334	.decode = clcdfb_decode,
	335	.enable = cp_clcd_enable,
	336	.setup = cp_clcd_setup,
9dfec4fe RK	337	.mmap = versatile_clcd_mmap_dma,
9dfec4fe RK	338	.remove = versatile_clcd_remove_dma,
1da177e4 LT	339	};
1da177e4 LT	340
d59fdcfc	341	static AMBA_AHB_DEVICE(clcd, "clcd", 0, INTCP_PA_CLCD_BASE,
2f64ccd9	342	{ IRQ_CP_CLCDCINT }, &clcd_data);
1da177e4 LT	343
	344	static struct amba_device *amba_devs[] __initdata = {
	345	&mmc_device,
	346	&aaci_device,
	347	&clcd_device,
	348	};
	349
d77e270c RK	350	#define REFCOUNTER (__io_address(INTEGRATOR_HDR_BASE) + 0x28)
d77e270c RK	351
c735c987 RK	352	static void __init intcp_init_early(void)
c735c987 RK	353	{
d77e270c RK	354	#ifdef CONFIG_PLAT_VERSATILE_SCHED_CLOCK
	355	versatile_sched_clock_init(REFCOUNTER, 24000000);
	356	#endif
c735c987 RK	357	}
c735c987 RK	358
1da177e4 LT	359	static void __init intcp_init(void)
	360	{
	361	int i;
	362
1da177e4 LT	363	platform_add_devices(intcp_devs, ARRAY_SIZE(intcp_devs));
	364
	365	for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
	366	struct amba_device *d = amba_devs[i];
	367	amba_device_register(d, &iomem_resource);
	368	}
9bf26a18	369	integrator_init(true);
1da177e4 LT	370	}
1da177e4 LT	371
5a46334a RK	372	#define TIMER0_VA_BASE __io_address(INTEGRATOR_TIMER0_BASE)
	373	#define TIMER1_VA_BASE __io_address(INTEGRATOR_TIMER1_BASE)
	374	#define TIMER2_VA_BASE __io_address(INTEGRATOR_TIMER2_BASE)
1da177e4 LT	375
	376	static void __init intcp_timer_init(void)
	377	{
5a46334a RK	378	writel(0, TIMER0_VA_BASE + TIMER_CTRL);
	379	writel(0, TIMER1_VA_BASE + TIMER_CTRL);
	380	writel(0, TIMER2_VA_BASE + TIMER_CTRL);
	381
fb593cf3	382	sp804_clocksource_init(TIMER2_VA_BASE, "timer2");
57cc4f7d	383	sp804_clockevents_init(TIMER1_VA_BASE, IRQ_TIMERINT1, "timer1");
1da177e4 LT	384	}
	385
	386	static struct sys_timer cp_timer = {
	387	.init = intcp_timer_init,
1da177e4 LT	388	};
	389
	390	MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP")
e9dea0c6	391	/* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
c5e587a2	392	.atag_offset = 0x100,
98c672cf	393	.reserve = integrator_reserve,
c735c987	394	.map_io = intcp_map_io,
695436e3	395	.nr_irqs = NR_IRQS_INTEGRATOR_CP,
c735c987	396	.init_early = intcp_init_early,
e9dea0c6	397	.init_irq = intcp_init_irq,
3108e6ab	398	.handle_irq = fpga_handle_irq,
1da177e4	399	.timer = &cp_timer,
e9dea0c6	400	.init_machine = intcp_init,
6338b66f	401	.restart = integrator_restart,
1da177e4	402	MACHINE_END