[mirror_ubuntu-bionic-kernel.git] / arch / arm / mach-integrator / integrator_cp.c

/*
 *  linux/arch/arm/mach-integrator/integrator_cp.c
 *
 *  Copyright (C) 2003 Deep Blue Solutions Ltd
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License.
 */
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/list.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/string.h>
#include <linux/device.h>
#include <linux/amba/bus.h>
#include <linux/amba/kmi.h>
#include <linux/amba/clcd.h>
#include <linux/amba/mmci.h>
#include <linux/io.h>
#include <linux/irqchip/versatile-fpga.h>
#include <linux/gfp.h>
#include <linux/mtd/physmap.h>
#include <linux/of_irq.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/sys_soc.h>
#include <linux/sched_clock.h>

#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/irq.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>

#include <plat/clcd.h>

#include "hardware.h"
#include "cm.h"
#include "common.h"

/* Base address to the CP controller */
static void __iomem *intcp_con_base;

#define INTCP_PA_FLASH_BASE		0x24000000

#define INTCP_PA_CLCD_BASE		0xc0000000

#define INTCP_FLASHPROG			0x04
#define CINTEGRATOR_FLASHPROG_FLVPPEN	(1 << 0)
#define CINTEGRATOR_FLASHPROG_FLWREN	(1 << 1)

/*
 * Logical      Physical
 * f1000000	10000000	Core module registers
 * f1300000	13000000	Counter/Timer
 * f1400000	14000000	Interrupt controller
 * f1600000	16000000	UART 0
 * f1700000	17000000	UART 1
 * f1a00000	1a000000	Debug LEDs
 * fc900000	c9000000	GPIO
 * fca00000	ca000000	SIC
 */

static struct map_desc intcp_io_desc[] __initdata __maybe_unused = {
	{
		.virtual	= IO_ADDRESS(INTEGRATOR_HDR_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_HDR_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_CT_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_CT_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_IC_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_IC_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_UART0_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_UART0_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_DBG_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_DBG_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_CP_GPIO_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_CP_GPIO_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_CP_SIC_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_CP_SIC_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}
};

static void __init intcp_map_io(void)
{
	iotable_init(intcp_io_desc, ARRAY_SIZE(intcp_io_desc));
}

/*
 * Flash handling.
 */
static int intcp_flash_init(struct platform_device *dev)
{
	u32 val;

	val = readl(intcp_con_base + INTCP_FLASHPROG);
	val |= CINTEGRATOR_FLASHPROG_FLWREN;
	writel(val, intcp_con_base + INTCP_FLASHPROG);

	return 0;
}

static void intcp_flash_exit(struct platform_device *dev)
{
	u32 val;

	val = readl(intcp_con_base + INTCP_FLASHPROG);
	val &= ~(CINTEGRATOR_FLASHPROG_FLVPPEN|CINTEGRATOR_FLASHPROG_FLWREN);
	writel(val, intcp_con_base + INTCP_FLASHPROG);
}

static void intcp_flash_set_vpp(struct platform_device *pdev, int on)
{
	u32 val;

	val = readl(intcp_con_base + INTCP_FLASHPROG);
	if (on)
		val |= CINTEGRATOR_FLASHPROG_FLVPPEN;
	else
		val &= ~CINTEGRATOR_FLASHPROG_FLVPPEN;
	writel(val, intcp_con_base + INTCP_FLASHPROG);
}

static struct physmap_flash_data intcp_flash_data = {
	.width		= 4,
	.init		= intcp_flash_init,
	.exit		= intcp_flash_exit,
	.set_vpp	= intcp_flash_set_vpp,
};

/*
 * It seems that the card insertion interrupt remains active after
 * we've acknowledged it.  We therefore ignore the interrupt, and
 * rely on reading it from the SIC.  This also means that we must
 * clear the latched interrupt.
 */
static unsigned int mmc_status(struct device *dev)
{
	unsigned int status = readl(__io_address(0xca000000 + 4));
	writel(8, intcp_con_base + 8);

	return status & 8;
}

static struct mmci_platform_data mmc_data = {
	.ocr_mask	= MMC_VDD_32_33|MMC_VDD_33_34,
	.status		= mmc_status,
	.gpio_wp	= -1,
	.gpio_cd	= -1,
};

/*
 * CLCD support
 */
/*
 * Ensure VGA is selected.
 */
static void cp_clcd_enable(struct clcd_fb *fb)
{
	struct fb_var_screeninfo *var = &fb->fb.var;
	u32 val = CM_CTRL_STATIC1 | CM_CTRL_STATIC2
			| CM_CTRL_LCDEN0 | CM_CTRL_LCDEN1;

	if (var->bits_per_pixel <= 8 ||
	    (var->bits_per_pixel == 16 && var->green.length == 5))
		/* Pseudocolor, RGB555, BGR555 */
		val |= CM_CTRL_LCDMUXSEL_VGA555_TFT555;
	else if (fb->fb.var.bits_per_pixel <= 16)
		/* truecolor RGB565 */
		val |= CM_CTRL_LCDMUXSEL_VGA565_TFT555;
	else
		val = 0; /* no idea for this, don't trust the docs */

	cm_control(CM_CTRL_LCDMUXSEL_MASK|
		   CM_CTRL_LCDEN0|
		   CM_CTRL_LCDEN1|
		   CM_CTRL_STATIC1|
		   CM_CTRL_STATIC2|
		   CM_CTRL_STATIC|
		   CM_CTRL_n24BITEN, val);
}

static int cp_clcd_setup(struct clcd_fb *fb)
{
	fb->panel = versatile_clcd_get_panel("VGA");
	if (!fb->panel)
		return -EINVAL;

	return versatile_clcd_setup_dma(fb, SZ_1M);
}

static struct clcd_board clcd_data = {
	.name		= "Integrator/CP",
	.caps		= CLCD_CAP_5551 | CLCD_CAP_RGB565 | CLCD_CAP_888,
	.check		= clcdfb_check,
	.decode		= clcdfb_decode,
	.enable		= cp_clcd_enable,
	.setup		= cp_clcd_setup,
	.mmap		= versatile_clcd_mmap_dma,
	.remove		= versatile_clcd_remove_dma,
};

#define REFCOUNTER (__io_address(INTEGRATOR_HDR_BASE) + 0x28)

static u64 notrace intcp_read_sched_clock(void)
{
	return readl(REFCOUNTER);
}

static void __init intcp_init_early(void)
{
	sched_clock_register(intcp_read_sched_clock, 32, 24000000);
}

static const struct of_device_id fpga_irq_of_match[] __initconst = {
	{ .compatible = "arm,versatile-fpga-irq", .data = fpga_irq_of_init, },
	{ /* Sentinel */ }
};

static void __init intcp_init_irq_of(void)
{
	cm_init();
	of_irq_init(fpga_irq_of_match);
}

/*
 * For the Device Tree, add in the UART, MMC and CLCD specifics as AUXDATA
 * and enforce the bus names since these are used for clock lookups.
 */
static struct of_dev_auxdata intcp_auxdata_lookup[] __initdata = {
	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_RTC_BASE,
		"rtc", NULL),
	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART0_BASE,
		"uart0", NULL),
	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART1_BASE,
		"uart1", NULL),
	OF_DEV_AUXDATA("arm,primecell", KMI0_BASE,
		"kmi0", NULL),
	OF_DEV_AUXDATA("arm,primecell", KMI1_BASE,
		"kmi1", NULL),
	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_CP_MMC_BASE,
		"mmci", &mmc_data),
	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_CP_AACI_BASE,
		"aaci", &mmc_data),
	OF_DEV_AUXDATA("arm,primecell", INTCP_PA_CLCD_BASE,
		"clcd", &clcd_data),
	OF_DEV_AUXDATA("cfi-flash", INTCP_PA_FLASH_BASE,
		"physmap-flash", &intcp_flash_data),
	{ /* sentinel */ },
};

static const struct of_device_id intcp_syscon_match[] = {
	{ .compatible = "arm,integrator-cp-syscon"},
	{ },
};

static void __init intcp_init_of(void)
{
	struct device_node *cpcon;
	struct device *parent;
	struct soc_device *soc_dev;
	struct soc_device_attribute *soc_dev_attr;
	u32 intcp_sc_id;

	cpcon = of_find_matching_node(NULL, intcp_syscon_match);
	if (!cpcon)
		return;

	intcp_con_base = of_iomap(cpcon, 0);
	if (!intcp_con_base)
		return;

	of_platform_populate(NULL, of_default_bus_match_table,
			     intcp_auxdata_lookup, NULL);

	intcp_sc_id = readl(intcp_con_base);

	soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
	if (!soc_dev_attr)
		return;

	soc_dev_attr->soc_id = "XCV";
	soc_dev_attr->machine = "Integrator/CP";
	soc_dev_attr->family = "Integrator";
	soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%c",
					   'A' + (intcp_sc_id & 0x0f));

	soc_dev = soc_device_register(soc_dev_attr);
	if (IS_ERR(soc_dev)) {
		kfree(soc_dev_attr->revision);
		kfree(soc_dev_attr);
		return;
	}

	parent = soc_device_to_device(soc_dev);
	integrator_init_sysfs(parent, intcp_sc_id);
}

static const char * intcp_dt_board_compat[] = {
	"arm,integrator-cp",
	NULL,
};

DT_MACHINE_START(INTEGRATOR_CP_DT, "ARM Integrator/CP (Device Tree)")
	.reserve	= integrator_reserve,
	.map_io		= intcp_map_io,
	.init_early	= intcp_init_early,
	.init_irq	= intcp_init_irq_of,
	.handle_irq	= fpga_handle_irq,
	.init_machine	= intcp_init_of,
	.restart	= integrator_restart,
	.dt_compat      = intcp_dt_board_compat,
MACHINE_END
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mach-integrator/integrator_cp.c
	3	*
	4	* Copyright (C) 2003 Deep Blue Solutions Ltd
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License.
	9	*/
	10	#include <linux/types.h>
	11	#include <linux/kernel.h>
	12	#include <linux/init.h>
	13	#include <linux/list.h>
d052d1be	14	#include <linux/platform_device.h>
1da177e4	15	#include <linux/dma-mapping.h>
1da177e4	16	#include <linux/string.h>
edbaa603	17	#include <linux/device.h>
a62c80e5 RK	18	#include <linux/amba/bus.h>
	19	#include <linux/amba/kmi.h>
	20	#include <linux/amba/clcd.h>
6ef297f8	21	#include <linux/amba/mmci.h>
fced80c7	22	#include <linux/io.h>
2389d501	23	#include <linux/irqchip/versatile-fpga.h>
5a0e3ad6	24	#include <linux/gfp.h>
046dfa0a	25	#include <linux/mtd/physmap.h>
4980f9bc LW	26	#include <linux/of_irq.h>
4980f9bc LW	27	#include <linux/of_address.h>
4672cddf	28	#include <linux/of_platform.h>
64100a03	29	#include <linux/sys_soc.h>
a79528e9	30	#include <linux/sched_clock.h>
1da177e4	31
1da177e4 LT	32	#include <asm/setup.h>
1da177e4 LT	33	#include <asm/mach-types.h>
1da177e4	34	#include <asm/mach/arch.h>
1da177e4	35	#include <asm/mach/irq.h>
1da177e4 LT	36	#include <asm/mach/map.h>
	37	#include <asm/mach/time.h>
	38
9dfec4fe RK	39	#include <plat/clcd.h>
9dfec4fe RK	40
1b1ef755	41	#include "hardware.h"
bb4dbefe	42	#include "cm.h"
98c672cf RK	43	#include "common.h"
98c672cf RK	44
e6fae083 LW	45	/* Base address to the CP controller */
	46	static void __iomem *intcp_con_base;
	47
1da177e4	48	#define INTCP_PA_FLASH_BASE 0x24000000
1da177e4 LT	49
	50	#define INTCP_PA_CLCD_BASE 0xc0000000
	51
1da177e4 LT	52	#define INTCP_FLASHPROG 0x04
	53	#define CINTEGRATOR_FLASHPROG_FLVPPEN (1 << 0)
	54	#define CINTEGRATOR_FLASHPROG_FLWREN (1 << 1)
	55
	56	/*
	57	* Logical Physical
608914b3	58	* f1000000 10000000 Core module registers
1da177e4 LT	59	* f1300000 13000000 Counter/Timer
	60	* f1400000 14000000 Interrupt controller
	61	* f1600000 16000000 UART 0
	62	* f1700000 17000000 UART 1
	63	* f1a00000 1a000000 Debug LEDs
da7ba956 RK	64	* fc900000 c9000000 GPIO
da7ba956 RK	65	* fca00000 ca000000 SIC
1da177e4 LT	66	*/
1da177e4 LT	67
060fd1be	68	static struct map_desc intcp_io_desc[] __initdata __maybe_unused = {
c8d27298	69	{
608914b3 LW	70	.virtual = IO_ADDRESS(INTEGRATOR_HDR_BASE),
	71	.pfn = __phys_to_pfn(INTEGRATOR_HDR_BASE),
	72	.length = SZ_4K,
	73	.type = MT_DEVICE
	74	}, {
c8d27298 DS	75	.virtual = IO_ADDRESS(INTEGRATOR_CT_BASE),
	76	.pfn = __phys_to_pfn(INTEGRATOR_CT_BASE),
	77	.length = SZ_4K,
	78	.type = MT_DEVICE
	79	}, {
	80	.virtual = IO_ADDRESS(INTEGRATOR_IC_BASE),
	81	.pfn = __phys_to_pfn(INTEGRATOR_IC_BASE),
	82	.length = SZ_4K,
	83	.type = MT_DEVICE
	84	}, {
	85	.virtual = IO_ADDRESS(INTEGRATOR_UART0_BASE),
	86	.pfn = __phys_to_pfn(INTEGRATOR_UART0_BASE),
	87	.length = SZ_4K,
	88	.type = MT_DEVICE
c8d27298 DS	89	}, {
	90	.virtual = IO_ADDRESS(INTEGRATOR_DBG_BASE),
	91	.pfn = __phys_to_pfn(INTEGRATOR_DBG_BASE),
	92	.length = SZ_4K,
	93	.type = MT_DEVICE
	94	}, {
da7ba956 RK	95	.virtual = IO_ADDRESS(INTEGRATOR_CP_GPIO_BASE),
da7ba956 RK	96	.pfn = __phys_to_pfn(INTEGRATOR_CP_GPIO_BASE),
c8d27298 DS	97	.length = SZ_4K,
	98	.type = MT_DEVICE
	99	}, {
da7ba956 RK	100	.virtual = IO_ADDRESS(INTEGRATOR_CP_SIC_BASE),
da7ba956 RK	101	.pfn = __phys_to_pfn(INTEGRATOR_CP_SIC_BASE),
c8d27298 DS	102	.length = SZ_4K,
c8d27298 DS	103	.type = MT_DEVICE
c8d27298	104	}
1da177e4 LT	105	};
	106
	107	static void __init intcp_map_io(void)
	108	{
	109	iotable_init(intcp_io_desc, ARRAY_SIZE(intcp_io_desc));
	110	}
	111
1da177e4 LT	112	/*
	113	* Flash handling.
	114	*/
046dfa0a	115	static int intcp_flash_init(struct platform_device *dev)
1da177e4 LT	116	{
	117	u32 val;
	118
e6fae083	119	val = readl(intcp_con_base + INTCP_FLASHPROG);
1da177e4	120	val \|= CINTEGRATOR_FLASHPROG_FLWREN;
e6fae083	121	writel(val, intcp_con_base + INTCP_FLASHPROG);
1da177e4 LT	122
	123	return 0;
	124	}
	125
046dfa0a	126	static void intcp_flash_exit(struct platform_device *dev)
1da177e4 LT	127	{
	128	u32 val;
	129
e6fae083	130	val = readl(intcp_con_base + INTCP_FLASHPROG);
1da177e4	131	val &= ~(CINTEGRATOR_FLASHPROG_FLVPPEN\|CINTEGRATOR_FLASHPROG_FLWREN);
e6fae083	132	writel(val, intcp_con_base + INTCP_FLASHPROG);
1da177e4 LT	133	}
1da177e4 LT	134
667f390b	135	static void intcp_flash_set_vpp(struct platform_device *pdev, int on)
1da177e4 LT	136	{
	137	u32 val;
	138
e6fae083	139	val = readl(intcp_con_base + INTCP_FLASHPROG);
1da177e4 LT	140	if (on)
	141	val \|= CINTEGRATOR_FLASHPROG_FLVPPEN;
	142	else
	143	val &= ~CINTEGRATOR_FLASHPROG_FLVPPEN;
e6fae083	144	writel(val, intcp_con_base + INTCP_FLASHPROG);
1da177e4 LT	145	}
1da177e4 LT	146
046dfa0a	147	static struct physmap_flash_data intcp_flash_data = {
1da177e4 LT	148	.width = 4,
	149	.init = intcp_flash_init,
	150	.exit = intcp_flash_exit,
	151	.set_vpp = intcp_flash_set_vpp,
	152	};
	153
1da177e4 LT	154	/*
	155	* It seems that the card insertion interrupt remains active after
	156	* we've acknowledged it. We therefore ignore the interrupt, and
	157	* rely on reading it from the SIC. This also means that we must
	158	* clear the latched interrupt.
	159	*/
	160	static unsigned int mmc_status(struct device *dev)
	161	{
b7a3f8db	162	unsigned int status = readl(__io_address(0xca000000 + 4));
e6fae083	163	writel(8, intcp_con_base + 8);
1da177e4 LT	164
	165	return status & 8;
	166	}
	167
6ef297f8	168	static struct mmci_platform_data mmc_data = {
1da177e4 LT	169	.ocr_mask = MMC_VDD_32_33\|MMC_VDD_33_34,
1da177e4 LT	170	.status = mmc_status,
7fb2bbf4 RK	171	.gpio_wp = -1,
7fb2bbf4 RK	172	.gpio_cd = -1,
1da177e4 LT	173	};
1da177e4 LT	174
1da177e4 LT	175	/*
	176	* CLCD support
	177	*/
1da177e4 LT	178	/*
	179	* Ensure VGA is selected.
	180	*/
	181	static void cp_clcd_enable(struct clcd_fb *fb)
	182	{
e6b9c1f8	183	struct fb_var_screeninfo *var = &fb->fb.var;
30aeadd4 JA	184	u32 val = CM_CTRL_STATIC1 \| CM_CTRL_STATIC2
30aeadd4 JA	185	\| CM_CTRL_LCDEN0 \| CM_CTRL_LCDEN1;
4774e226	186
e6b9c1f8 RK	187	if (var->bits_per_pixel <= 8 \|\|
	188	(var->bits_per_pixel == 16 && var->green.length == 5))
	189	/* Pseudocolor, RGB555, BGR555 */
	190	val \|= CM_CTRL_LCDMUXSEL_VGA555_TFT555;
4774e226	191	else if (fb->fb.var.bits_per_pixel <= 16)
e6b9c1f8 RK	192	/* truecolor RGB565 */
e6b9c1f8 RK	193	val \|= CM_CTRL_LCDMUXSEL_VGA565_TFT555;
4774e226 RK	194	else
	195	val = 0; /* no idea for this, don't trust the docs */
	196
	197	cm_control(CM_CTRL_LCDMUXSEL_MASK\|
	198	CM_CTRL_LCDEN0\|
	199	CM_CTRL_LCDEN1\|
	200	CM_CTRL_STATIC1\|
	201	CM_CTRL_STATIC2\|
	202	CM_CTRL_STATIC\|
	203	CM_CTRL_n24BITEN, val);
1da177e4 LT	204	}
1da177e4 LT	205
1da177e4 LT	206	static int cp_clcd_setup(struct clcd_fb *fb)
1da177e4 LT	207	{
9dfec4fe RK	208	fb->panel = versatile_clcd_get_panel("VGA");
	209	if (!fb->panel)
	210	return -EINVAL;
1da177e4	211
9dfec4fe	212	return versatile_clcd_setup_dma(fb, SZ_1M);
1da177e4 LT	213	}
	214
	215	static struct clcd_board clcd_data = {
	216	.name = "Integrator/CP",
9dfec4fe	217	.caps = CLCD_CAP_5551 \| CLCD_CAP_RGB565 \| CLCD_CAP_888,
1da177e4 LT	218	.check = clcdfb_check,
	219	.decode = clcdfb_decode,
	220	.enable = cp_clcd_enable,
	221	.setup = cp_clcd_setup,
9dfec4fe RK	222	.mmap = versatile_clcd_mmap_dma,
9dfec4fe RK	223	.remove = versatile_clcd_remove_dma,
1da177e4 LT	224	};
1da177e4 LT	225
d77e270c RK	226	#define REFCOUNTER (__io_address(INTEGRATOR_HDR_BASE) + 0x28)
d77e270c RK	227
a79528e9 LW	228	static u64 notrace intcp_read_sched_clock(void)
	229	{
	230	return readl(REFCOUNTER);
	231	}
	232
c735c987 RK	233	static void __init intcp_init_early(void)
c735c987 RK	234	{
a79528e9	235	sched_clock_register(intcp_read_sched_clock, 32, 24000000);
c735c987 RK	236	}
c735c987 RK	237
4980f9bc LW	238	static const struct of_device_id fpga_irq_of_match[] __initconst = {
	239	{ .compatible = "arm,versatile-fpga-irq", .data = fpga_irq_of_init, },
	240	{ /* Sentinel */ }
	241	};
	242
	243	static void __init intcp_init_irq_of(void)
1da177e4	244	{
bb4dbefe	245	cm_init();
4980f9bc	246	of_irq_init(fpga_irq_of_match);
4980f9bc	247	}
1da177e4	248
4672cddf LW	249	/*
	250	* For the Device Tree, add in the UART, MMC and CLCD specifics as AUXDATA
	251	* and enforce the bus names since these are used for clock lookups.
	252	*/
	253	static struct of_dev_auxdata intcp_auxdata_lookup[] __initdata = {
	254	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_RTC_BASE,
	255	"rtc", NULL),
	256	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART0_BASE,
379df279	257	"uart0", NULL),
4672cddf	258	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART1_BASE,
379df279	259	"uart1", NULL),
4672cddf LW	260	OF_DEV_AUXDATA("arm,primecell", KMI0_BASE,
	261	"kmi0", NULL),
	262	OF_DEV_AUXDATA("arm,primecell", KMI1_BASE,
	263	"kmi1", NULL),
	264	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_CP_MMC_BASE,
	265	"mmci", &mmc_data),
	266	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_CP_AACI_BASE,
	267	"aaci", &mmc_data),
	268	OF_DEV_AUXDATA("arm,primecell", INTCP_PA_CLCD_BASE,
	269	"clcd", &clcd_data),
73efd530 LW	270	OF_DEV_AUXDATA("cfi-flash", INTCP_PA_FLASH_BASE,
73efd530 LW	271	"physmap-flash", &intcp_flash_data),
4672cddf LW	272	{ /* sentinel */ },
	273	};
	274
df36680f LW	275	static const struct of_device_id intcp_syscon_match[] = {
	276	{ .compatible = "arm,integrator-cp-syscon"},
	277	{ },
	278	};
	279
4672cddf LW	280	static void __init intcp_init_of(void)
4672cddf LW	281	{
64100a03 LW	282	struct device_node *cpcon;
	283	struct device *parent;
	284	struct soc_device *soc_dev;
	285	struct soc_device_attribute *soc_dev_attr;
	286	u32 intcp_sc_id;
64100a03	287
11f9323a	288	cpcon = of_find_matching_node(NULL, intcp_syscon_match);
64100a03 LW	289	if (!cpcon)
	290	return;
	291
	292	intcp_con_base = of_iomap(cpcon, 0);
	293	if (!intcp_con_base)
	294	return;
	295
11f9323a LW	296	of_platform_populate(NULL, of_default_bus_match_table,
	297	intcp_auxdata_lookup, NULL);
	298
64100a03 LW	299	intcp_sc_id = readl(intcp_con_base);
	300
	301	soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
	302	if (!soc_dev_attr)
	303	return;
	304
11f9323a LW	305	soc_dev_attr->soc_id = "XCV";
11f9323a LW	306	soc_dev_attr->machine = "Integrator/CP";
64100a03 LW	307	soc_dev_attr->family = "Integrator";
	308	soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%c",
	309	'A' + (intcp_sc_id & 0x0f));
	310
	311	soc_dev = soc_device_register(soc_dev_attr);
b269b170	312	if (IS_ERR(soc_dev)) {
64100a03 LW	313	kfree(soc_dev_attr->revision);
	314	kfree(soc_dev_attr);
	315	return;
	316	}
	317
	318	parent = soc_device_to_device(soc_dev);
b269b170	319	integrator_init_sysfs(parent, intcp_sc_id);
4672cddf LW	320	}
4672cddf LW	321
4980f9bc LW	322	static const char * intcp_dt_board_compat[] = {
	323	"arm,integrator-cp",
	324	NULL,
	325	};
1da177e4	326
4980f9bc LW	327	DT_MACHINE_START(INTEGRATOR_CP_DT, "ARM Integrator/CP (Device Tree)")
	328	.reserve = integrator_reserve,
	329	.map_io = intcp_map_io,
4980f9bc LW	330	.init_early = intcp_init_early,
	331	.init_irq = intcp_init_irq_of,
	332	.handle_irq = fpga_handle_irq,
4672cddf	333	.init_machine = intcp_init_of,
4980f9bc LW	334	.restart = integrator_restart,
	335	.dt_compat = intcp_dt_board_compat,
	336	MACHINE_END