[mirror_ubuntu-jammy-kernel.git] / arch / arm / mach-iop13xx / msi.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * arch/arm/mach-iop13xx/msi.c
 *
 * PCI MSI support for the iop13xx processor
 *
 * Copyright (c) 2006, Intel Corporation.
 */
#include <linux/pci.h>
#include <linux/msi.h>
#include <asm/mach/irq.h>
#include <asm/irq.h>
#include <mach/irqs.h>

/* IMIPR0 CP6 R8 Page 1
 */
static u32 read_imipr_0(void)
{
	u32 val;
	asm volatile("mrc p6, 0, %0, c8, c1, 0":"=r" (val));
	return val;
}
static void write_imipr_0(u32 val)
{
	asm volatile("mcr p6, 0, %0, c8, c1, 0"::"r" (val));
}

/* IMIPR1 CP6 R9 Page 1
 */
static u32 read_imipr_1(void)
{
	u32 val;
	asm volatile("mrc p6, 0, %0, c9, c1, 0":"=r" (val));
	return val;
}
static void write_imipr_1(u32 val)
{
	asm volatile("mcr p6, 0, %0, c9, c1, 0"::"r" (val));
}

/* IMIPR2 CP6 R10 Page 1
 */
static u32 read_imipr_2(void)
{
	u32 val;
	asm volatile("mrc p6, 0, %0, c10, c1, 0":"=r" (val));
	return val;
}
static void write_imipr_2(u32 val)
{
	asm volatile("mcr p6, 0, %0, c10, c1, 0"::"r" (val));
}

/* IMIPR3 CP6 R11 Page 1
 */
static u32 read_imipr_3(void)
{
	u32 val;
	asm volatile("mrc p6, 0, %0, c11, c1, 0":"=r" (val));
	return val;
}
static void write_imipr_3(u32 val)
{
	asm volatile("mcr p6, 0, %0, c11, c1, 0"::"r" (val));
}

static u32 (*read_imipr[])(void) = {
	read_imipr_0,
	read_imipr_1,
	read_imipr_2,
	read_imipr_3,
};

static void (*write_imipr[])(u32) = {
	write_imipr_0,
	write_imipr_1,
	write_imipr_2,
	write_imipr_3,
};

static void iop13xx_msi_handler(struct irq_desc *desc)
{
	int i, j;
	unsigned long status;

	/* read IMIPR registers and find any active interrupts,
	 * then call ISR for each active interrupt
	 */
	for (i = 0; i < ARRAY_SIZE(read_imipr); i++) {
		status = (read_imipr[i])();
		if (!status)
			continue;

		do {
			j = find_first_bit(&status, 32);
			(write_imipr[i])(1 << j); /* write back to clear bit */
			generic_handle_irq(IRQ_IOP13XX_MSI_0 + j + (32*i));
			status = (read_imipr[i])();
		} while (status);
	}
}

void __init iop13xx_msi_init(void)
{
	irq_set_chained_handler(IRQ_IOP13XX_INBD_MSI, iop13xx_msi_handler);
}

static void iop13xx_msi_nop(struct irq_data *d)
{
	return;
}

static struct irq_chip iop13xx_msi_chip = {
	.name = "PCI-MSI",
	.irq_ack = iop13xx_msi_nop,
	.irq_enable = pci_msi_unmask_irq,
	.irq_disable = pci_msi_mask_irq,
	.irq_mask = pci_msi_mask_irq,
	.irq_unmask = pci_msi_unmask_irq,
};

int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
{
	int id, irq = irq_alloc_desc_from(IRQ_IOP13XX_MSI_0, -1);
	struct msi_msg msg;

	if (irq < 0)
		return irq;

	if (irq >= NR_IOP13XX_IRQS) {
		irq_free_desc(irq);
		return -ENOSPC;
	}

	irq_set_msi_desc(irq, desc);

	msg.address_hi = 0x0;
	msg.address_lo = IOP13XX_MU_MIMR_PCI;

	id = iop13xx_cpu_id();
	msg.data = (id << IOP13XX_MU_MIMR_CORE_SELECT) | (irq & 0x7f);

	pci_write_msi_msg(irq, &msg);
	irq_set_chip_and_handler(irq, &iop13xx_msi_chip, handle_simple_irq);

	return 0;
}

void arch_teardown_msi_irq(unsigned int irq)
{
	irq_free_desc(irq);
}
Commit	Line	Data
3b20eb23	1	// SPDX-License-Identifier: GPL-2.0-only
2fd02375 DW	2	/*
	3	* arch/arm/mach-iop13xx/msi.c
	4	*
	5	* PCI MSI support for the iop13xx processor
	6	*
	7	* Copyright (c) 2006, Intel Corporation.
2fd02375 DW	8	*/
	9	#include <linux/pci.h>
	10	#include <linux/msi.h>
	11	#include <asm/mach/irq.h>
	12	#include <asm/irq.h>
8d2af85e	13	#include <mach/irqs.h>
2fd02375	14
2fd02375 DW	15	/* IMIPR0 CP6 R8 Page 1
2fd02375 DW	16	*/
d73d8011	17	static u32 read_imipr_0(void)
2fd02375 DW	18	{
	19	u32 val;
	20	asm volatile("mrc p6, 0, %0, c8, c1, 0":"=r" (val));
	21	return val;
	22	}
d73d8011	23	static void write_imipr_0(u32 val)
2fd02375 DW	24	{
	25	asm volatile("mcr p6, 0, %0, c8, c1, 0"::"r" (val));
	26	}
	27
	28	/* IMIPR1 CP6 R9 Page 1
	29	*/
d73d8011	30	static u32 read_imipr_1(void)
2fd02375 DW	31	{
	32	u32 val;
	33	asm volatile("mrc p6, 0, %0, c9, c1, 0":"=r" (val));
	34	return val;
	35	}
d73d8011	36	static void write_imipr_1(u32 val)
2fd02375 DW	37	{
	38	asm volatile("mcr p6, 0, %0, c9, c1, 0"::"r" (val));
	39	}
	40
	41	/* IMIPR2 CP6 R10 Page 1
	42	*/
d73d8011	43	static u32 read_imipr_2(void)
2fd02375 DW	44	{
	45	u32 val;
	46	asm volatile("mrc p6, 0, %0, c10, c1, 0":"=r" (val));
	47	return val;
	48	}
d73d8011	49	static void write_imipr_2(u32 val)
2fd02375 DW	50	{
	51	asm volatile("mcr p6, 0, %0, c10, c1, 0"::"r" (val));
	52	}
	53
	54	/* IMIPR3 CP6 R11 Page 1
	55	*/
d73d8011	56	static u32 read_imipr_3(void)
2fd02375 DW	57	{
	58	u32 val;
	59	asm volatile("mrc p6, 0, %0, c11, c1, 0":"=r" (val));
	60	return val;
	61	}
d73d8011	62	static void write_imipr_3(u32 val)
2fd02375 DW	63	{
	64	asm volatile("mcr p6, 0, %0, c11, c1, 0"::"r" (val));
	65	}
	66
	67	static u32 (*read_imipr[])(void) = {
	68	read_imipr_0,
	69	read_imipr_1,
	70	read_imipr_2,
	71	read_imipr_3,
	72	};
	73
	74	static void (*write_imipr[])(u32) = {
	75	write_imipr_0,
	76	write_imipr_1,
	77	write_imipr_2,
	78	write_imipr_3,
	79	};
	80
bd0b9ac4	81	static void iop13xx_msi_handler(struct irq_desc *desc)
2fd02375 DW	82	{
	83	int i, j;
	84	unsigned long status;
	85
	86	/* read IMIPR registers and find any active interrupts,
	87	* then call ISR for each active interrupt
	88	*/
	89	for (i = 0; i < ARRAY_SIZE(read_imipr); i++) {
	90	status = (read_imipr[i])();
	91	if (!status)
	92	continue;
	93
	94	do {
	95	j = find_first_bit(&status, 32);
	96	(write_imipr[i])(1 << j); /* write back to clear bit */
d8aa0251	97	generic_handle_irq(IRQ_IOP13XX_MSI_0 + j + (32*i));
2fd02375 DW	98	status = (read_imipr[i])();
	99	} while (status);
	100	}
	101	}
	102
	103	void __init iop13xx_msi_init(void)
	104	{
6845664a	105	irq_set_chained_handler(IRQ_IOP13XX_INBD_MSI, iop13xx_msi_handler);
2fd02375 DW	106	}
2fd02375 DW	107
418c9904	108	static void iop13xx_msi_nop(struct irq_data *d)
2fd02375 DW	109	{
	110	return;
	111	}
	112
	113	static struct irq_chip iop13xx_msi_chip = {
	114	.name = "PCI-MSI",
418c9904	115	.irq_ack = iop13xx_msi_nop,
280510f1 TG	116	.irq_enable = pci_msi_unmask_irq,
	117	.irq_disable = pci_msi_mask_irq,
	118	.irq_mask = pci_msi_mask_irq,
	119	.irq_unmask = pci_msi_unmask_irq,
2fd02375 DW	120	};
	121
	122	int arch_setup_msi_irq(struct pci_dev pdev, struct msi_desc desc)
	123	{
37ebbcff	124	int id, irq = irq_alloc_desc_from(IRQ_IOP13XX_MSI_0, -1);
2fd02375 DW	125	struct msi_msg msg;
	126
	127	if (irq < 0)
	128	return irq;
	129
37ebbcff TG	130	if (irq >= NR_IOP13XX_IRQS) {
	131	irq_free_desc(irq);
	132	return -ENOSPC;
	133	}
	134
6845664a	135	irq_set_msi_desc(irq, desc);
2fd02375 DW	136
	137	msg.address_hi = 0x0;
	138	msg.address_lo = IOP13XX_MU_MIMR_PCI;
	139
	140	id = iop13xx_cpu_id();
	141	msg.data = (id << IOP13XX_MU_MIMR_CORE_SELECT) \| (irq & 0x7f);
	142
83a18912	143	pci_write_msi_msg(irq, &msg);
6845664a	144	irq_set_chip_and_handler(irq, &iop13xx_msi_chip, handle_simple_irq);
2fd02375	145
e702a715	146	return 0;
2fd02375	147	}
37ebbcff TG	148
	149	void arch_teardown_msi_irq(unsigned int irq)
	150	{
	151	irq_free_desc(irq);
	152	}