[mirror_ubuntu-hirsute-kernel.git] / arch / arm / mach-iop33x / include / mach / irqs.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * arch/arm/mach-iop33x/include/mach/irqs.h
 *
 * Author:	Dave Jiang (dave.jiang@intel.com)
 * Copyright:	(C) 2003 Intel Corp.
 */

#ifndef __IRQS_H
#define __IRQS_H

/*
 * IOP80331 chipset interrupts
 */
#define IRQ_IOP33X_DMA0_EOT	0
#define IRQ_IOP33X_DMA0_EOC	1
#define IRQ_IOP33X_DMA1_EOT	2
#define IRQ_IOP33X_DMA1_EOC	3
#define IRQ_IOP33X_AA_EOT	6
#define IRQ_IOP33X_AA_EOC	7
#define IRQ_IOP33X_TIMER0	8
#define IRQ_IOP33X_TIMER1	9
#define IRQ_IOP33X_I2C_0	10
#define IRQ_IOP33X_I2C_1	11
#define IRQ_IOP33X_MSG		12
#define IRQ_IOP33X_MSGIBQ	13
#define IRQ_IOP33X_ATU_BIST	14
#define IRQ_IOP33X_PERFMON	15
#define IRQ_IOP33X_CORE_PMU	16
#define IRQ_IOP33X_XINT0	24
#define IRQ_IOP33X_XINT1	25
#define IRQ_IOP33X_XINT2	26
#define IRQ_IOP33X_XINT3	27
#define IRQ_IOP33X_XINT8	32
#define IRQ_IOP33X_XINT9	33
#define IRQ_IOP33X_XINT10	34
#define IRQ_IOP33X_XINT11	35
#define IRQ_IOP33X_XINT12	36
#define IRQ_IOP33X_XINT13	37
#define IRQ_IOP33X_XINT14	38
#define IRQ_IOP33X_XINT15	39
#define IRQ_IOP33X_UART0	51
#define IRQ_IOP33X_UART1	52
#define IRQ_IOP33X_PBIE		53
#define IRQ_IOP33X_ATU_CRW	54
#define IRQ_IOP33X_ATU_ERR	55
#define IRQ_IOP33X_MCU_ERR	56
#define IRQ_IOP33X_DMA0_ERR	57
#define IRQ_IOP33X_DMA1_ERR	58
#define IRQ_IOP33X_AA_ERR	60
#define IRQ_IOP33X_MSG_ERR	62
#define IRQ_IOP33X_HPI		63

#define NR_IRQS			64


#endif
Commit	Line	Data
d2912cb1	1	/* SPDX-License-Identifier: GPL-2.0-only */
1da177e4	2	/*
a09e64fb	3	* arch/arm/mach-iop33x/include/mach/irqs.h
1da177e4 LT	4	*
	5	* Author: Dave Jiang (dave.jiang@intel.com)
	6	* Copyright: (C) 2003 Intel Corp.
1da177e4	7	*/
c852ac80 LB	8
	9	#ifndef __IRQS_H
	10	#define __IRQS_H
1da177e4 LT	11
	12	/*
	13	* IOP80331 chipset interrupts
	14	*/
c852ac80 LB	15	#define IRQ_IOP33X_DMA0_EOT 0
	16	#define IRQ_IOP33X_DMA0_EOC 1
	17	#define IRQ_IOP33X_DMA1_EOT 2
	18	#define IRQ_IOP33X_DMA1_EOC 3
	19	#define IRQ_IOP33X_AA_EOT 6
	20	#define IRQ_IOP33X_AA_EOC 7
	21	#define IRQ_IOP33X_TIMER0 8
	22	#define IRQ_IOP33X_TIMER1 9
	23	#define IRQ_IOP33X_I2C_0 10
	24	#define IRQ_IOP33X_I2C_1 11
	25	#define IRQ_IOP33X_MSG 12
	26	#define IRQ_IOP33X_MSGIBQ 13
	27	#define IRQ_IOP33X_ATU_BIST 14
	28	#define IRQ_IOP33X_PERFMON 15
	29	#define IRQ_IOP33X_CORE_PMU 16
	30	#define IRQ_IOP33X_XINT0 24
	31	#define IRQ_IOP33X_XINT1 25
	32	#define IRQ_IOP33X_XINT2 26
	33	#define IRQ_IOP33X_XINT3 27
	34	#define IRQ_IOP33X_XINT8 32
	35	#define IRQ_IOP33X_XINT9 33
	36	#define IRQ_IOP33X_XINT10 34
	37	#define IRQ_IOP33X_XINT11 35
	38	#define IRQ_IOP33X_XINT12 36
	39	#define IRQ_IOP33X_XINT13 37
	40	#define IRQ_IOP33X_XINT14 38
	41	#define IRQ_IOP33X_XINT15 39
	42	#define IRQ_IOP33X_UART0 51
	43	#define IRQ_IOP33X_UART1 52
	44	#define IRQ_IOP33X_PBIE 53
	45	#define IRQ_IOP33X_ATU_CRW 54
	46	#define IRQ_IOP33X_ATU_ERR 55
	47	#define IRQ_IOP33X_MCU_ERR 56
	48	#define IRQ_IOP33X_DMA0_ERR 57
	49	#define IRQ_IOP33X_DMA1_ERR 58
	50	#define IRQ_IOP33X_AA_ERR 60
	51	#define IRQ_IOP33X_MSG_ERR 62
	52	#define IRQ_IOP33X_HPI 63
1da177e4	53
610300e8	54	#define NR_IRQS 64
1da177e4 LT	55
1da177e4 LT	56
c852ac80	57	#endif