[mirror_ubuntu-eoan-kernel.git] / arch / arm / mach-iop33x / iq80332.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * arch/arm/mach-iop33x/iq80332.c
 *
 * Board support code for the Intel IQ80332 platform.
 *
 * Author: Dave Jiang <dave.jiang@intel.com>
 * Copyright (C) 2004 Intel Corp.
 */

#include <linux/mm.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/string.h>
#include <linux/serial_core.h>
#include <linux/serial_8250.h>
#include <linux/mtd/physmap.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/pci.h>
#include <asm/mach/time.h>
#include <asm/mach-types.h>
#include <asm/page.h>
#include <asm/pgtable.h>
#include <mach/time.h>

/*
 * IQ80332 timer tick configuration.
 */
static void __init iq80332_timer_init(void)
{
	/* D-Step parts and the iop333 run at a higher internal bus frequency */
	if (*IOP3XX_ATURID >= 0xa || *IOP3XX_ATUDID == 0x374)
		iop_init_time(333000000);
	else
		iop_init_time(266000000);
}


/*
 * IQ80332 PCI.
 */
static int __init
iq80332_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
	int irq;

	if (slot == 4 && pin == 1) {
		/* PCI-X Slot INTA */
		irq = IRQ_IOP33X_XINT0;
	} else if (slot == 4 && pin == 2) {
		/* PCI-X Slot INTB */
		irq = IRQ_IOP33X_XINT1;
	} else if (slot == 4 && pin == 3) {
		/* PCI-X Slot INTC */
		irq = IRQ_IOP33X_XINT2;
	} else if (slot == 4 && pin == 4) {
		/* PCI-X Slot INTD */
		irq = IRQ_IOP33X_XINT3;
	} else if (slot == 6) {
		/* GigE */
		irq = IRQ_IOP33X_XINT2;
	} else {
		printk(KERN_ERR "iq80332_pci_map_irq() called for unknown "
			"device PCI:%d:%d:%d\n", dev->bus->number,
			PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
		irq = -1;
	}

	return irq;
}

static struct hw_pci iq80332_pci __initdata = {
	.nr_controllers = 1,
	.ops		= &iop3xx_ops,
	.setup		= iop3xx_pci_setup,
	.preinit	= iop3xx_pci_preinit_cond,
	.map_irq	= iq80332_pci_map_irq,
};

static int __init iq80332_pci_init(void)
{
	if ((iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE) &&
		machine_is_iq80332())
		pci_common_init(&iq80332_pci);

	return 0;
}

subsys_initcall(iq80332_pci_init);


/*
 * IQ80332 machine initialisation.
 */
static struct physmap_flash_data iq80332_flash_data = {
	.width		= 1,
};

static struct resource iq80332_flash_resource = {
	.start		= 0xc0000000,
	.end		= 0xc07fffff,
	.flags		= IORESOURCE_MEM,
};

static struct platform_device iq80332_flash_device = {
	.name		= "physmap-flash",
	.id		= 0,
	.dev		= {
		.platform_data	= &iq80332_flash_data,
	},
	.num_resources	= 1,
	.resource	= &iq80332_flash_resource,
};

static struct resource iq80332_gpio_res[] = {
	DEFINE_RES_MEM((IOP3XX_PERIPHERAL_PHYS_BASE + 0x1780), 0x10),
};

static void __init iq80332_init_machine(void)
{
	platform_device_register_simple("gpio-iop", 0,
					iq80332_gpio_res,
					ARRAY_SIZE(iq80332_gpio_res));
	platform_device_register(&iop3xx_i2c0_device);
	platform_device_register(&iop3xx_i2c1_device);
	platform_device_register(&iop33x_uart0_device);
	platform_device_register(&iop33x_uart1_device);
	platform_device_register(&iq80332_flash_device);
	platform_device_register(&iop3xx_dma_0_channel);
	platform_device_register(&iop3xx_dma_1_channel);
	platform_device_register(&iop3xx_aau_channel);
}

MACHINE_START(IQ80332, "Intel IQ80332")
	/* Maintainer: Intel Corp. */
	.atag_offset	= 0x100,
	.map_io		= iop3xx_map_io,
	.init_irq	= iop33x_init_irq,
	.init_time	= iq80332_timer_init,
	.init_machine	= iq80332_init_machine,
	.restart	= iop3xx_restart,
MACHINE_END
Commit	Line	Data
2874c5fd	1	// SPDX-License-Identifier: GPL-2.0-or-later
c680b77e LB	2	/*
	3	* arch/arm/mach-iop33x/iq80332.c
	4	*
	5	* Board support code for the Intel IQ80332 platform.
	6	*
	7	* Author: Dave Jiang <dave.jiang@intel.com>
	8	* Copyright (C) 2004 Intel Corp.
c680b77e LB	9	*/
	10
	11	#include <linux/mm.h>
	12	#include <linux/init.h>
	13	#include <linux/kernel.h>
	14	#include <linux/pci.h>
	15	#include <linux/string.h>
c680b77e LB	16	#include <linux/serial_core.h>
	17	#include <linux/serial_8250.h>
	18	#include <linux/mtd/physmap.h>
	19	#include <linux/platform_device.h>
fced80c7	20	#include <linux/io.h>
a09e64fb	21	#include <mach/hardware.h>
c680b77e LB	22	#include <asm/irq.h>
	23	#include <asm/mach/arch.h>
	24	#include <asm/mach/map.h>
	25	#include <asm/mach/pci.h>
	26	#include <asm/mach/time.h>
	27	#include <asm/mach-types.h>
	28	#include <asm/page.h>
	29	#include <asm/pgtable.h>
a09e64fb	30	#include <mach/time.h>
c680b77e LB	31
	32	/*
	33	* IQ80332 timer tick configuration.
	34	*/
	35	static void __init iq80332_timer_init(void)
	36	{
	37	/* D-Step parts and the iop333 run at a higher internal bus frequency */
	38	if (IOP3XX_ATURID >= 0xa \|\| IOP3XX_ATUDID == 0x374)
3668b45d	39	iop_init_time(333000000);
c680b77e	40	else
3668b45d	41	iop_init_time(266000000);
c680b77e LB	42	}
c680b77e LB	43
c680b77e LB	44
	45	/*
	46	* IQ80332 PCI.
	47	*/
d73d8011	48	static int __init
d5341942	49	iq80332_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
c680b77e LB	50	{
	51	int irq;
	52
	53	if (slot == 4 && pin == 1) {
	54	/* PCI-X Slot INTA */
c852ac80	55	irq = IRQ_IOP33X_XINT0;
c680b77e LB	56	} else if (slot == 4 && pin == 2) {
c680b77e LB	57	/* PCI-X Slot INTB */
c852ac80	58	irq = IRQ_IOP33X_XINT1;
c680b77e LB	59	} else if (slot == 4 && pin == 3) {
c680b77e LB	60	/* PCI-X Slot INTC */
c852ac80	61	irq = IRQ_IOP33X_XINT2;
c680b77e LB	62	} else if (slot == 4 && pin == 4) {
c680b77e LB	63	/* PCI-X Slot INTD */
c852ac80	64	irq = IRQ_IOP33X_XINT3;
c680b77e LB	65	} else if (slot == 6) {
c680b77e LB	66	/* GigE */
c852ac80	67	irq = IRQ_IOP33X_XINT2;
c680b77e LB	68	} else {
	69	printk(KERN_ERR "iq80332_pci_map_irq() called for unknown "
	70	"device PCI:%d:%d:%d\n", dev->bus->number,
	71	PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
	72	irq = -1;
	73	}
	74
	75	return irq;
	76	}
	77
	78	static struct hw_pci iq80332_pci __initdata = {
c680b77e	79	.nr_controllers = 1,
c23bfc38	80	.ops = &iop3xx_ops,
c680b77e	81	.setup = iop3xx_pci_setup,
c34002c1	82	.preinit = iop3xx_pci_preinit_cond,
c680b77e LB	83	.map_irq = iq80332_pci_map_irq,
	84	};
	85
	86	static int __init iq80332_pci_init(void)
	87	{
e90ddd81 DW	88	if ((iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE) &&
e90ddd81 DW	89	machine_is_iq80332())
c680b77e LB	90	pci_common_init(&iq80332_pci);
	91
	92	return 0;
	93	}
	94
	95	subsys_initcall(iq80332_pci_init);
	96
	97
	98	/*
	99	* IQ80332 machine initialisation.
	100	*/
	101	static struct physmap_flash_data iq80332_flash_data = {
	102	.width = 1,
	103	};
	104
	105	static struct resource iq80332_flash_resource = {
	106	.start = 0xc0000000,
	107	.end = 0xc07fffff,
	108	.flags = IORESOURCE_MEM,
	109	};
	110
	111	static struct platform_device iq80332_flash_device = {
	112	.name = "physmap-flash",
	113	.id = 0,
	114	.dev = {
	115	.platform_data = &iq80332_flash_data,
	116	},
	117	.num_resources = 1,
	118	.resource = &iq80332_flash_resource,
	119	};
	120
7b85b867	121	static struct resource iq80332_gpio_res[] = {
e34ca9de	122	DEFINE_RES_MEM((IOP3XX_PERIPHERAL_PHYS_BASE + 0x1780), 0x10),
7b85b867 LW	123	};
7b85b867 LW	124
c680b77e LB	125	static void __init iq80332_init_machine(void)
c680b77e LB	126	{
7b85b867 LW	127	platform_device_register_simple("gpio-iop", 0,
	128	iq80332_gpio_res,
	129	ARRAY_SIZE(iq80332_gpio_res));
c680b77e LB	130	platform_device_register(&iop3xx_i2c0_device);
	131	platform_device_register(&iop3xx_i2c1_device);
	132	platform_device_register(&iop33x_uart0_device);
	133	platform_device_register(&iop33x_uart1_device);
	134	platform_device_register(&iq80332_flash_device);
2492c845 DW	135	platform_device_register(&iop3xx_dma_0_channel);
	136	platform_device_register(&iop3xx_dma_1_channel);
	137	platform_device_register(&iop3xx_aau_channel);
c680b77e LB	138	}
	139
	140	MACHINE_START(IQ80332, "Intel IQ80332")
	141	/* Maintainer: Intel Corp. */
e5c76c00	142	.atag_offset = 0x100,
c680b77e	143	.map_io = iop3xx_map_io,
c852ac80	144	.init_irq = iop33x_init_irq,
6bb27d73	145	.init_time = iq80332_timer_init,
c680b77e	146	.init_machine = iq80332_init_machine,
bec92b1e	147	.restart = iop3xx_restart,
c680b77e	148	MACHINE_END