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1 | /* |
2 | * linux/arch/arm/mach-iop3xx/iop321-irq.c | |
3 | * | |
4 | * Generic IOP321 IRQ handling functionality | |
5 | * | |
6 | * Author: Rory Bolt <rorybolt@pacbell.net> | |
7 | * Copyright (C) 2002 Rory Bolt | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * Added IOP3XX chipset and IQ80321 board masking code. | |
14 | * | |
15 | */ | |
16 | #include <linux/init.h> | |
17 | #include <linux/interrupt.h> | |
18 | #include <linux/list.h> | |
19 | ||
20 | #include <asm/mach/irq.h> | |
21 | #include <asm/irq.h> | |
22 | #include <asm/hardware.h> | |
23 | ||
24 | #include <asm/mach-types.h> | |
25 | ||
26 | static u32 iop321_mask /* = 0 */; | |
27 | ||
28 | static inline void intctl_write(u32 val) | |
29 | { | |
30 | asm volatile("mcr p6,0,%0,c0,c0,0"::"r" (val)); | |
31 | } | |
32 | ||
33 | static inline void intstr_write(u32 val) | |
34 | { | |
35 | asm volatile("mcr p6,0,%0,c4,c0,0"::"r" (val)); | |
36 | } | |
37 | ||
38 | static void | |
39 | iop321_irq_mask (unsigned int irq) | |
40 | { | |
41 | ||
42 | iop321_mask &= ~(1 << (irq - IOP321_IRQ_OFS)); | |
43 | ||
44 | intctl_write(iop321_mask); | |
45 | } | |
46 | ||
47 | static void | |
48 | iop321_irq_unmask (unsigned int irq) | |
49 | { | |
50 | iop321_mask |= (1 << (irq - IOP321_IRQ_OFS)); | |
51 | ||
52 | intctl_write(iop321_mask); | |
53 | } | |
54 | ||
38c677cb DB |
55 | struct irq_chip ext_chip = { |
56 | .name = "IOP", | |
1da177e4 LT |
57 | .ack = iop321_irq_mask, |
58 | .mask = iop321_irq_mask, | |
59 | .unmask = iop321_irq_unmask, | |
60 | }; | |
61 | ||
62 | void __init iop321_init_irq(void) | |
63 | { | |
64 | unsigned int i, tmp; | |
65 | ||
66 | /* Enable access to coprocessor 6 for dealing with IRQs. | |
67 | * From RMK: | |
68 | * Basically, the Intel documentation here is poor. It appears that | |
69 | * you need to set the bit to be able to access the coprocessor from | |
70 | * SVC mode. Whether that allows access from user space or not is | |
71 | * unclear. | |
72 | */ | |
73 | asm volatile ( | |
74 | "mrc p15, 0, %0, c15, c1, 0\n\t" | |
75 | "orr %0, %0, %1\n\t" | |
76 | "mcr p15, 0, %0, c15, c1, 0\n\t" | |
77 | /* The action is delayed, so we have to do this: */ | |
78 | "mrc p15, 0, %0, c15, c1, 0\n\t" | |
79 | "mov %0, %0\n\t" | |
80 | "sub pc, pc, #4" | |
81 | : "=r" (tmp) : "i" (1 << 6) ); | |
82 | ||
83 | intctl_write(0); // disable all interrupts | |
84 | intstr_write(0); // treat all as IRQ | |
85 | if(machine_is_iq80321() || | |
86 | machine_is_iq31244()) // all interrupts are inputs to chip | |
87 | *IOP321_PCIIRSR = 0x0f; | |
88 | ||
89 | for(i = IOP321_IRQ_OFS; i < NR_IOP321_IRQS; i++) | |
90 | { | |
91 | set_irq_chip(i, &ext_chip); | |
92 | set_irq_handler(i, do_level_IRQ); | |
93 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); | |
94 | ||
95 | } | |
96 | } | |
97 |