[mirror_ubuntu-bionic-kernel.git] / arch / arm / mach-ixp2000 / core.c

/*
 * arch/arm/mach-ixp2000/core.c
 *
 * Common routines used by all IXP2400/2800 based platforms.
 *
 * Author: Deepak Saxena <dsaxena@plexity.net>
 *
 * Copyright 2004 (C) MontaVista Software, Inc. 
 *
 * Based on work Copyright (C) 2002-2003 Intel Corporation
 * 
 * This file is licensed under the terms of the GNU General Public
 * License version 2. This program is licensed "as is" without any 
 * warranty of any kind, whether express or implied.
 */
#include <linux/gpio.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/spinlock.h>
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/serial.h>
#include <linux/tty.h>
#include <linux/bitops.h>
#include <linux/serial_8250.h>
#include <linux/mm.h>

#include <asm/types.h>
#include <asm/setup.h>
#include <asm/memory.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/system.h>
#include <asm/tlbflush.h>
#include <asm/pgtable.h>

#include <asm/mach/map.h>
#include <asm/mach/time.h>
#include <asm/mach/irq.h>

static DEFINE_SPINLOCK(ixp2000_slowport_lock);
static unsigned long ixp2000_slowport_irq_flags;

/*************************************************************************
 * Slowport access routines
 *************************************************************************/
void ixp2000_acquire_slowport(struct slowport_cfg *new_cfg, struct slowport_cfg *old_cfg)
{
	spin_lock_irqsave(&ixp2000_slowport_lock, ixp2000_slowport_irq_flags);

	old_cfg->CCR = *IXP2000_SLOWPORT_CCR;
	old_cfg->WTC = *IXP2000_SLOWPORT_WTC2;
	old_cfg->RTC = *IXP2000_SLOWPORT_RTC2;
	old_cfg->PCR = *IXP2000_SLOWPORT_PCR;
	old_cfg->ADC = *IXP2000_SLOWPORT_ADC;

	ixp2000_reg_write(IXP2000_SLOWPORT_CCR, new_cfg->CCR);
	ixp2000_reg_write(IXP2000_SLOWPORT_WTC2, new_cfg->WTC);
	ixp2000_reg_write(IXP2000_SLOWPORT_RTC2, new_cfg->RTC);
	ixp2000_reg_write(IXP2000_SLOWPORT_PCR, new_cfg->PCR);
	ixp2000_reg_wrb(IXP2000_SLOWPORT_ADC, new_cfg->ADC);
}

void ixp2000_release_slowport(struct slowport_cfg *old_cfg)
{
	ixp2000_reg_write(IXP2000_SLOWPORT_CCR, old_cfg->CCR);
	ixp2000_reg_write(IXP2000_SLOWPORT_WTC2, old_cfg->WTC);
	ixp2000_reg_write(IXP2000_SLOWPORT_RTC2, old_cfg->RTC);
	ixp2000_reg_write(IXP2000_SLOWPORT_PCR, old_cfg->PCR);
	ixp2000_reg_wrb(IXP2000_SLOWPORT_ADC, old_cfg->ADC);

	spin_unlock_irqrestore(&ixp2000_slowport_lock, 
					ixp2000_slowport_irq_flags);
}

/*************************************************************************
 * Chip specific mappings shared by all IXP2000 systems
 *************************************************************************/
static struct map_desc ixp2000_io_desc[] __initdata = {
	{
		.virtual	= IXP2000_CAP_VIRT_BASE,
		.pfn		= __phys_to_pfn(IXP2000_CAP_PHYS_BASE),
		.length		= IXP2000_CAP_SIZE,
		.type		= MT_DEVICE,
	}, {
		.virtual	= IXP2000_INTCTL_VIRT_BASE,
		.pfn		= __phys_to_pfn(IXP2000_INTCTL_PHYS_BASE),
		.length		= IXP2000_INTCTL_SIZE,
		.type		= MT_DEVICE,
	}, {
		.virtual	= IXP2000_PCI_CREG_VIRT_BASE,
		.pfn		= __phys_to_pfn(IXP2000_PCI_CREG_PHYS_BASE),
		.length		= IXP2000_PCI_CREG_SIZE,
		.type		= MT_DEVICE,
	}, {
		.virtual	= IXP2000_PCI_CSR_VIRT_BASE,
		.pfn		= __phys_to_pfn(IXP2000_PCI_CSR_PHYS_BASE),
		.length		= IXP2000_PCI_CSR_SIZE,
		.type		= MT_DEVICE,
	}, {
		.virtual	= IXP2000_MSF_VIRT_BASE,
		.pfn		= __phys_to_pfn(IXP2000_MSF_PHYS_BASE),
		.length		= IXP2000_MSF_SIZE,
		.type		= MT_DEVICE,
	}, {
		.virtual	= IXP2000_SCRATCH_RING_VIRT_BASE,
		.pfn		= __phys_to_pfn(IXP2000_SCRATCH_RING_PHYS_BASE),
		.length		= IXP2000_SCRATCH_RING_SIZE,
		.type		= MT_DEVICE,
	}, {
		.virtual	= IXP2000_SRAM0_VIRT_BASE,
		.pfn		= __phys_to_pfn(IXP2000_SRAM0_PHYS_BASE),
		.length		= IXP2000_SRAM0_SIZE,
		.type		= MT_DEVICE,
	}, {
		.virtual	= IXP2000_PCI_IO_VIRT_BASE,
		.pfn		= __phys_to_pfn(IXP2000_PCI_IO_PHYS_BASE),
		.length		= IXP2000_PCI_IO_SIZE,
		.type		= MT_DEVICE,
	}, {
		.virtual	= IXP2000_PCI_CFG0_VIRT_BASE,
		.pfn		= __phys_to_pfn(IXP2000_PCI_CFG0_PHYS_BASE),
		.length		= IXP2000_PCI_CFG0_SIZE,
		.type		= MT_DEVICE,
	}, {
		.virtual	= IXP2000_PCI_CFG1_VIRT_BASE,
		.pfn		= __phys_to_pfn(IXP2000_PCI_CFG1_PHYS_BASE),
		.length		= IXP2000_PCI_CFG1_SIZE,
		.type		= MT_DEVICE,
	}
};

void __init ixp2000_map_io(void)
{
	iotable_init(ixp2000_io_desc, ARRAY_SIZE(ixp2000_io_desc));

	/* Set slowport to 8-bit mode.  */
	ixp2000_reg_wrb(IXP2000_SLOWPORT_FRM, 1);
}


/*************************************************************************
 * Serial port support for IXP2000
 *************************************************************************/
static struct plat_serial8250_port ixp2000_serial_port[] = {
	{
		.mapbase	= IXP2000_UART_PHYS_BASE,
		.membase	= (char *)(IXP2000_UART_VIRT_BASE + 3),
		.irq		= IRQ_IXP2000_UART,
		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
		.iotype		= UPIO_MEM,
		.regshift	= 2,
		.uartclk	= 50000000,
	},
	{ },
};

static struct resource ixp2000_uart_resource = {
	.start		= IXP2000_UART_PHYS_BASE,
	.end		= IXP2000_UART_PHYS_BASE + 0x1f,
	.flags		= IORESOURCE_MEM,
};

static struct platform_device ixp2000_serial_device = {
	.name		= "serial8250",
	.id		= PLAT8250_DEV_PLATFORM,
	.dev		= {
		.platform_data		= ixp2000_serial_port,
	},
	.num_resources	= 1,
	.resource	= &ixp2000_uart_resource,
};

void __init ixp2000_uart_init(void)
{
	platform_device_register(&ixp2000_serial_device);
}


/*************************************************************************
 * Timer-tick functions for IXP2000
 *************************************************************************/
static unsigned ticks_per_jiffy;
static unsigned ticks_per_usec;
static unsigned next_jiffy_time;
static volatile unsigned long *missing_jiffy_timer_csr;

unsigned long ixp2000_gettimeoffset (void)
{
 	unsigned long offset;

	offset = next_jiffy_time - *missing_jiffy_timer_csr;

	return offset / ticks_per_usec;
}

static irqreturn_t ixp2000_timer_interrupt(int irq, void *dev_id)
{
	/* clear timer 1 */
	ixp2000_reg_wrb(IXP2000_T1_CLR, 1);

	while ((signed long)(next_jiffy_time - *missing_jiffy_timer_csr)
							>= ticks_per_jiffy) {
		timer_tick();
		next_jiffy_time -= ticks_per_jiffy;
	}

	return IRQ_HANDLED;
}

static struct irqaction ixp2000_timer_irq = {
	.name		= "IXP2000 Timer Tick",
	.flags		= IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
	.handler	= ixp2000_timer_interrupt,
};

void __init ixp2000_init_time(unsigned long tick_rate)
{
	ticks_per_jiffy = (tick_rate + HZ/2) / HZ;
	ticks_per_usec = tick_rate / 1000000;

	/*
	 * We use timer 1 as our timer interrupt.
	 */
	ixp2000_reg_write(IXP2000_T1_CLR, 0);
	ixp2000_reg_write(IXP2000_T1_CLD, ticks_per_jiffy - 1);
	ixp2000_reg_write(IXP2000_T1_CTL, (1 << 7));

	/*
	 * We use a second timer as a monotonic counter for tracking
	 * missed jiffies.  The IXP2000 has four timers, but if we're
	 * on an A-step IXP2800, timer 2 and 3 don't work, so on those
	 * chips we use timer 4.  Timer 4 is the only timer that can
	 * be used for the watchdog, so we use timer 2 if we're on a
	 * non-buggy chip.
	 */
	if ((*IXP2000_PRODUCT_ID & 0x001ffef0) == 0x00000000) {
		printk(KERN_INFO "Enabling IXP2800 erratum #25 workaround\n");

		ixp2000_reg_write(IXP2000_T4_CLR, 0);
		ixp2000_reg_write(IXP2000_T4_CLD, -1);
		ixp2000_reg_wrb(IXP2000_T4_CTL, (1 << 7));
		missing_jiffy_timer_csr = IXP2000_T4_CSR;
	} else {
		ixp2000_reg_write(IXP2000_T2_CLR, 0);
		ixp2000_reg_write(IXP2000_T2_CLD, -1);
		ixp2000_reg_wrb(IXP2000_T2_CTL, (1 << 7));
		missing_jiffy_timer_csr = IXP2000_T2_CSR;
	}
 	next_jiffy_time = 0xffffffff;

	/* register for interrupt */
	setup_irq(IRQ_IXP2000_TIMER1, &ixp2000_timer_irq);
}

/*************************************************************************
 * GPIO helpers
 *************************************************************************/
static unsigned long GPIO_IRQ_falling_edge;
static unsigned long GPIO_IRQ_rising_edge;
static unsigned long GPIO_IRQ_level_low;
static unsigned long GPIO_IRQ_level_high;

static void update_gpio_int_csrs(void)
{
	ixp2000_reg_write(IXP2000_GPIO_FEDR, GPIO_IRQ_falling_edge);
	ixp2000_reg_write(IXP2000_GPIO_REDR, GPIO_IRQ_rising_edge);
	ixp2000_reg_write(IXP2000_GPIO_LSLR, GPIO_IRQ_level_low);
	ixp2000_reg_wrb(IXP2000_GPIO_LSHR, GPIO_IRQ_level_high);
}

void gpio_line_config(int line, int direction)
{
	unsigned long flags;

	local_irq_save(flags);
	if (direction == GPIO_OUT) {
		/* if it's an output, it ain't an interrupt anymore */
		GPIO_IRQ_falling_edge &= ~(1 << line);
		GPIO_IRQ_rising_edge &= ~(1 << line);
		GPIO_IRQ_level_low &= ~(1 << line);
		GPIO_IRQ_level_high &= ~(1 << line);
		update_gpio_int_csrs();

		ixp2000_reg_wrb(IXP2000_GPIO_PDSR, 1 << line);
	} else if (direction == GPIO_IN) {
		ixp2000_reg_wrb(IXP2000_GPIO_PDCR, 1 << line);
	}
	local_irq_restore(flags);
}
EXPORT_SYMBOL(gpio_line_config);


/*************************************************************************
 * IRQ handling IXP2000
 *************************************************************************/
static void ixp2000_GPIO_irq_handler(unsigned int irq, struct irq_desc *desc)
{                               
	int i;
	unsigned long status = *IXP2000_GPIO_INST;
		   
	for (i = 0; i <= 7; i++) {
		if (status & (1<<i)) {
			generic_handle_irq(i + IRQ_IXP2000_GPIO0);
		}
	}
}

static int ixp2000_GPIO_irq_type(struct irq_data *d, unsigned int type)
{
	int line = d->irq - IRQ_IXP2000_GPIO0;

	/*
	 * First, configure this GPIO line as an input.
	 */
	ixp2000_reg_write(IXP2000_GPIO_PDCR, 1 << line);

	/*
	 * Then, set the proper trigger type.
	 */
	if (type & IRQ_TYPE_EDGE_FALLING)
		GPIO_IRQ_falling_edge |= 1 << line;
	else
		GPIO_IRQ_falling_edge &= ~(1 << line);
	if (type & IRQ_TYPE_EDGE_RISING)
		GPIO_IRQ_rising_edge |= 1 << line;
	else
		GPIO_IRQ_rising_edge &= ~(1 << line);
	if (type & IRQ_TYPE_LEVEL_LOW)
		GPIO_IRQ_level_low |= 1 << line;
	else
		GPIO_IRQ_level_low &= ~(1 << line);
	if (type & IRQ_TYPE_LEVEL_HIGH)
		GPIO_IRQ_level_high |= 1 << line;
	else
		GPIO_IRQ_level_high &= ~(1 << line);
	update_gpio_int_csrs();

	return 0;
}

static void ixp2000_GPIO_irq_mask_ack(struct irq_data *d)
{
	unsigned int irq = d->irq;

	ixp2000_reg_write(IXP2000_GPIO_INCR, (1 << (irq - IRQ_IXP2000_GPIO0)));

	ixp2000_reg_write(IXP2000_GPIO_EDSR, (1 << (irq - IRQ_IXP2000_GPIO0)));
	ixp2000_reg_write(IXP2000_GPIO_LDSR, (1 << (irq - IRQ_IXP2000_GPIO0)));
	ixp2000_reg_wrb(IXP2000_GPIO_INST, (1 << (irq - IRQ_IXP2000_GPIO0)));
}

static void ixp2000_GPIO_irq_mask(struct irq_data *d)
{
	unsigned int irq = d->irq;

	ixp2000_reg_wrb(IXP2000_GPIO_INCR, (1 << (irq - IRQ_IXP2000_GPIO0)));
}

static void ixp2000_GPIO_irq_unmask(struct irq_data *d)
{
	unsigned int irq = d->irq;

	ixp2000_reg_write(IXP2000_GPIO_INSR, (1 << (irq - IRQ_IXP2000_GPIO0)));
}

static struct irq_chip ixp2000_GPIO_irq_chip = {
	.irq_ack	= ixp2000_GPIO_irq_mask_ack,
	.irq_mask	= ixp2000_GPIO_irq_mask,
	.irq_unmask	= ixp2000_GPIO_irq_unmask,
	.irq_set_type	= ixp2000_GPIO_irq_type,
};

static void ixp2000_pci_irq_mask(struct irq_data *d)
{
	unsigned long temp = *IXP2000_PCI_XSCALE_INT_ENABLE;
	if (d->irq == IRQ_IXP2000_PCIA)
		ixp2000_reg_wrb(IXP2000_PCI_XSCALE_INT_ENABLE, (temp & ~(1 << 26)));
	else if (d->irq == IRQ_IXP2000_PCIB)
		ixp2000_reg_wrb(IXP2000_PCI_XSCALE_INT_ENABLE, (temp & ~(1 << 27)));
}

static void ixp2000_pci_irq_unmask(struct irq_data *d)
{
	unsigned long temp = *IXP2000_PCI_XSCALE_INT_ENABLE;
	if (d->irq == IRQ_IXP2000_PCIA)
		ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp | (1 << 26)));
	else if (d->irq == IRQ_IXP2000_PCIB)
		ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp | (1 << 27)));
}

/*
 * Error interrupts. These are used extensively by the microengine drivers
 */
static void ixp2000_err_irq_handler(unsigned int irq, struct irq_desc *desc)
{
	int i;
	unsigned long status = *IXP2000_IRQ_ERR_STATUS;

	for(i = 31; i >= 0; i--) {
		if(status & (1 << i)) {
			generic_handle_irq(IRQ_IXP2000_DRAM0_MIN_ERR + i);
		}
	}
}

static void ixp2000_err_irq_mask(struct irq_data *d)
{
	ixp2000_reg_write(IXP2000_IRQ_ERR_ENABLE_CLR,
			(1 << (d->irq - IRQ_IXP2000_DRAM0_MIN_ERR)));
}

static void ixp2000_err_irq_unmask(struct irq_data *d)
{
	ixp2000_reg_write(IXP2000_IRQ_ERR_ENABLE_SET,
			(1 << (d->irq - IRQ_IXP2000_DRAM0_MIN_ERR)));
}

static struct irq_chip ixp2000_err_irq_chip = {
	.irq_ack	= ixp2000_err_irq_mask,
	.irq_mask	= ixp2000_err_irq_mask,
	.irq_unmask	= ixp2000_err_irq_unmask
};

static struct irq_chip ixp2000_pci_irq_chip = {
	.irq_ack	= ixp2000_pci_irq_mask,
	.irq_mask	= ixp2000_pci_irq_mask,
	.irq_unmask	= ixp2000_pci_irq_unmask
};

static void ixp2000_irq_mask(struct irq_data *d)
{
	ixp2000_reg_wrb(IXP2000_IRQ_ENABLE_CLR, (1 << d->irq));
}

static void ixp2000_irq_unmask(struct irq_data *d)
{
	ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << d->irq));
}

static struct irq_chip ixp2000_irq_chip = {
	.irq_ack	= ixp2000_irq_mask,
	.irq_mask	= ixp2000_irq_mask,
	.irq_unmask	= ixp2000_irq_unmask
};

void __init ixp2000_init_irq(void)
{
	int irq;

	/*
	 * Mask all sources
	 */
	ixp2000_reg_write(IXP2000_IRQ_ENABLE_CLR, 0xffffffff);
	ixp2000_reg_write(IXP2000_FIQ_ENABLE_CLR, 0xffffffff);

	/* clear all GPIO edge/level detects */
	ixp2000_reg_write(IXP2000_GPIO_REDR, 0);
	ixp2000_reg_write(IXP2000_GPIO_FEDR, 0);
	ixp2000_reg_write(IXP2000_GPIO_LSHR, 0);
	ixp2000_reg_write(IXP2000_GPIO_LSLR, 0);
	ixp2000_reg_write(IXP2000_GPIO_INCR, -1);

	/* clear PCI interrupt sources */
	ixp2000_reg_wrb(IXP2000_PCI_XSCALE_INT_ENABLE, 0);

	/*
	 * Certain bits in the IRQ status register of the 
	 * IXP2000 are reserved. Instead of trying to map
	 * things non 1:1 from bit position to IRQ number,
	 * we mark the reserved IRQs as invalid. This makes
	 * our mask/unmask code much simpler.
	 */
	for (irq = IRQ_IXP2000_SOFT_INT; irq <= IRQ_IXP2000_THDB3; irq++) {
		if ((1 << irq) & IXP2000_VALID_IRQ_MASK) {
			irq_set_chip_and_handler(irq, &ixp2000_irq_chip,
						 handle_level_irq);
			set_irq_flags(irq, IRQF_VALID);
		} else set_irq_flags(irq, 0);
	}

	for (irq = IRQ_IXP2000_DRAM0_MIN_ERR; irq <= IRQ_IXP2000_SP_INT; irq++) {
		if((1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)) &
				IXP2000_VALID_ERR_IRQ_MASK) {
			irq_set_chip_and_handler(irq, &ixp2000_err_irq_chip,
						 handle_level_irq);
			set_irq_flags(irq, IRQF_VALID);
		}
		else
			set_irq_flags(irq, 0);
	}
	irq_set_chained_handler(IRQ_IXP2000_ERRSUM, ixp2000_err_irq_handler);

	for (irq = IRQ_IXP2000_GPIO0; irq <= IRQ_IXP2000_GPIO7; irq++) {
		irq_set_chip_and_handler(irq, &ixp2000_GPIO_irq_chip,
					 handle_level_irq);
		set_irq_flags(irq, IRQF_VALID);
	}
	irq_set_chained_handler(IRQ_IXP2000_GPIO, ixp2000_GPIO_irq_handler);

	/*
	 * Enable PCI irqs.  The actual PCI[AB] decoding is done in
	 * entry-macro.S, so we don't need a chained handler for the
	 * PCI interrupt source.
	 */
	ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << IRQ_IXP2000_PCI));
	for (irq = IRQ_IXP2000_PCIA; irq <= IRQ_IXP2000_PCIB; irq++) {
		irq_set_chip_and_handler(irq, &ixp2000_pci_irq_chip,
					 handle_level_irq);
		set_irq_flags(irq, IRQF_VALID);
	}
}
Commit	Line	Data
1da177e4	1	/*
fa87cedd	2	* arch/arm/mach-ixp2000/core.c
1da177e4 LT	3	*
	4	* Common routines used by all IXP2400/2800 based platforms.
	5	*
	6	* Author: Deepak Saxena <dsaxena@plexity.net>
	7	*
	8	* Copyright 2004 (C) MontaVista Software, Inc.
	9	*
	10	* Based on work Copyright (C) 2002-2003 Intel Corporation
	11	*
	12	* This file is licensed under the terms of the GNU General Public
	13	* License version 2. This program is licensed "as is" without any
	14	* warranty of any kind, whether express or implied.
	15	*/
2f8163ba	16	#include <linux/gpio.h>
1da177e4 LT	17	#include <linux/kernel.h>
	18	#include <linux/init.h>
	19	#include <linux/spinlock.h>
	20	#include <linux/sched.h>
	21	#include <linux/interrupt.h>
64ffae8a	22	#include <linux/irq.h>
1da177e4 LT	23	#include <linux/serial.h>
	24	#include <linux/tty.h>
	25	#include <linux/bitops.h>
28187f2c	26	#include <linux/serial_8250.h>
1da177e4 LT	27	#include <linux/mm.h>
	28
	29	#include <asm/types.h>
	30	#include <asm/setup.h>
	31	#include <asm/memory.h>
a09e64fb	32	#include <mach/hardware.h>
1da177e4 LT	33	#include <asm/irq.h>
	34	#include <asm/system.h>
	35	#include <asm/tlbflush.h>
	36	#include <asm/pgtable.h>
	37
	38	#include <asm/mach/map.h>
	39	#include <asm/mach/time.h>
	40	#include <asm/mach/irq.h>
	41
	42	static DEFINE_SPINLOCK(ixp2000_slowport_lock);
	43	static unsigned long ixp2000_slowport_irq_flags;
	44
	45	/*************************************************************************
	46	* Slowport access routines
	47	*************************************************************************/
	48	void ixp2000_acquire_slowport(struct slowport_cfg new_cfg, struct slowport_cfg old_cfg)
	49	{
1da177e4 LT	50	spin_lock_irqsave(&ixp2000_slowport_lock, ixp2000_slowport_irq_flags);
	51
	52	old_cfg->CCR = *IXP2000_SLOWPORT_CCR;
	53	old_cfg->WTC = *IXP2000_SLOWPORT_WTC2;
	54	old_cfg->RTC = *IXP2000_SLOWPORT_RTC2;
	55	old_cfg->PCR = *IXP2000_SLOWPORT_PCR;
	56	old_cfg->ADC = *IXP2000_SLOWPORT_ADC;
	57
	58	ixp2000_reg_write(IXP2000_SLOWPORT_CCR, new_cfg->CCR);
	59	ixp2000_reg_write(IXP2000_SLOWPORT_WTC2, new_cfg->WTC);
	60	ixp2000_reg_write(IXP2000_SLOWPORT_RTC2, new_cfg->RTC);
	61	ixp2000_reg_write(IXP2000_SLOWPORT_PCR, new_cfg->PCR);
e9b72e43	62	ixp2000_reg_wrb(IXP2000_SLOWPORT_ADC, new_cfg->ADC);
1da177e4 LT	63	}
	64
	65	void ixp2000_release_slowport(struct slowport_cfg *old_cfg)
	66	{
	67	ixp2000_reg_write(IXP2000_SLOWPORT_CCR, old_cfg->CCR);
	68	ixp2000_reg_write(IXP2000_SLOWPORT_WTC2, old_cfg->WTC);
	69	ixp2000_reg_write(IXP2000_SLOWPORT_RTC2, old_cfg->RTC);
	70	ixp2000_reg_write(IXP2000_SLOWPORT_PCR, old_cfg->PCR);
e9b72e43	71	ixp2000_reg_wrb(IXP2000_SLOWPORT_ADC, old_cfg->ADC);
1da177e4 LT	72
	73	spin_unlock_irqrestore(&ixp2000_slowport_lock,
	74	ixp2000_slowport_irq_flags);
	75	}
	76
	77	/*************************************************************************
	78	* Chip specific mappings shared by all IXP2000 systems
	79	*************************************************************************/
	80	static struct map_desc ixp2000_io_desc[] __initdata = {
	81	{
	82	.virtual = IXP2000_CAP_VIRT_BASE,
db0d087e	83	.pfn = __phys_to_pfn(IXP2000_CAP_PHYS_BASE),
1da177e4	84	.length = IXP2000_CAP_SIZE,
db5b7169	85	.type = MT_DEVICE,
1da177e4 LT	86	}, {
1da177e4 LT	87	.virtual = IXP2000_INTCTL_VIRT_BASE,
db0d087e	88	.pfn = __phys_to_pfn(IXP2000_INTCTL_PHYS_BASE),
1da177e4	89	.length = IXP2000_INTCTL_SIZE,
db5b7169	90	.type = MT_DEVICE,
1da177e4 LT	91	}, {
1da177e4 LT	92	.virtual = IXP2000_PCI_CREG_VIRT_BASE,
db0d087e	93	.pfn = __phys_to_pfn(IXP2000_PCI_CREG_PHYS_BASE),
1da177e4	94	.length = IXP2000_PCI_CREG_SIZE,
db5b7169	95	.type = MT_DEVICE,
1da177e4 LT	96	}, {
1da177e4 LT	97	.virtual = IXP2000_PCI_CSR_VIRT_BASE,
db0d087e	98	.pfn = __phys_to_pfn(IXP2000_PCI_CSR_PHYS_BASE),
1da177e4	99	.length = IXP2000_PCI_CSR_SIZE,
db5b7169	100	.type = MT_DEVICE,
baaf7ed1 LB	101	}, {
baaf7ed1 LB	102	.virtual = IXP2000_MSF_VIRT_BASE,
db0d087e	103	.pfn = __phys_to_pfn(IXP2000_MSF_PHYS_BASE),
baaf7ed1	104	.length = IXP2000_MSF_SIZE,
db5b7169	105	.type = MT_DEVICE,
dd29c727 LB	106	}, {
	107	.virtual = IXP2000_SCRATCH_RING_VIRT_BASE,
	108	.pfn = __phys_to_pfn(IXP2000_SCRATCH_RING_PHYS_BASE),
	109	.length = IXP2000_SCRATCH_RING_SIZE,
db5b7169	110	.type = MT_DEVICE,
dd29c727 LB	111	}, {
	112	.virtual = IXP2000_SRAM0_VIRT_BASE,
	113	.pfn = __phys_to_pfn(IXP2000_SRAM0_PHYS_BASE),
	114	.length = IXP2000_SRAM0_SIZE,
db5b7169	115	.type = MT_DEVICE,
1da177e4 LT	116	}, {
1da177e4 LT	117	.virtual = IXP2000_PCI_IO_VIRT_BASE,
db0d087e	118	.pfn = __phys_to_pfn(IXP2000_PCI_IO_PHYS_BASE),
1da177e4	119	.length = IXP2000_PCI_IO_SIZE,
db5b7169	120	.type = MT_DEVICE,
1da177e4 LT	121	}, {
1da177e4 LT	122	.virtual = IXP2000_PCI_CFG0_VIRT_BASE,
db0d087e	123	.pfn = __phys_to_pfn(IXP2000_PCI_CFG0_PHYS_BASE),
1da177e4	124	.length = IXP2000_PCI_CFG0_SIZE,
db5b7169	125	.type = MT_DEVICE,
1da177e4 LT	126	}, {
1da177e4 LT	127	.virtual = IXP2000_PCI_CFG1_VIRT_BASE,
db0d087e	128	.pfn = __phys_to_pfn(IXP2000_PCI_CFG1_PHYS_BASE),
1da177e4	129	.length = IXP2000_PCI_CFG1_SIZE,
db5b7169	130	.type = MT_DEVICE,
1da177e4 LT	131	}
	132	};
	133
1da177e4 LT	134	void __init ixp2000_map_io(void)
1da177e4 LT	135	{
1da177e4	136	iotable_init(ixp2000_io_desc, ARRAY_SIZE(ixp2000_io_desc));
1da177e4 LT	137
1da177e4 LT	138	/* Set slowport to 8-bit mode. */
e9b72e43	139	ixp2000_reg_wrb(IXP2000_SLOWPORT_FRM, 1);
1da177e4 LT	140	}
1da177e4 LT	141
28187f2c LB	142
	143	/*************************************************************************
	144	* Serial port support for IXP2000
	145	*************************************************************************/
	146	static struct plat_serial8250_port ixp2000_serial_port[] = {
	147	{
	148	.mapbase = IXP2000_UART_PHYS_BASE,
	149	.membase = (char *)(IXP2000_UART_VIRT_BASE + 3),
	150	.irq = IRQ_IXP2000_UART,
	151	.flags = UPF_BOOT_AUTOCONF \| UPF_SKIP_TEST,
	152	.iotype = UPIO_MEM,
	153	.regshift = 2,
	154	.uartclk = 50000000,
	155	},
	156	{ },
	157	};
	158
	159	static struct resource ixp2000_uart_resource = {
	160	.start = IXP2000_UART_PHYS_BASE,
702c96d5	161	.end = IXP2000_UART_PHYS_BASE + 0x1f,
28187f2c LB	162	.flags = IORESOURCE_MEM,
	163	};
	164
	165	static struct platform_device ixp2000_serial_device = {
	166	.name = "serial8250",
6df29deb	167	.id = PLAT8250_DEV_PLATFORM,
28187f2c LB	168	.dev = {
	169	.platform_data = ixp2000_serial_port,
	170	},
	171	.num_resources = 1,
	172	.resource = &ixp2000_uart_resource,
	173	};
	174
	175	void __init ixp2000_uart_init(void)
	176	{
	177	platform_device_register(&ixp2000_serial_device);
	178	}
	179
	180
1da177e4 LT	181	/*************************************************************************
	182	* Timer-tick functions for IXP2000
	183	*************************************************************************/
	184	static unsigned ticks_per_jiffy;
	185	static unsigned ticks_per_usec;
	186	static unsigned next_jiffy_time;
e4fe1981	187	static volatile unsigned long *missing_jiffy_timer_csr;
1da177e4 LT	188
	189	unsigned long ixp2000_gettimeoffset (void)
	190	{
	191	unsigned long offset;
	192
e4fe1981	193	offset = next_jiffy_time - *missing_jiffy_timer_csr;
1da177e4 LT	194
	195	return offset / ticks_per_usec;
	196	}
	197
d463f363	198	static irqreturn_t ixp2000_timer_interrupt(int irq, void *dev_id)
1da177e4	199	{
1da177e4	200	/* clear timer 1 */
e9b72e43	201	ixp2000_reg_wrb(IXP2000_T1_CLR, 1);
c4982887	202
f869afab LB	203	while ((signed long)(next_jiffy_time - *missing_jiffy_timer_csr)
f869afab LB	204	>= ticks_per_jiffy) {
0cd61b68	205	timer_tick();
1da177e4 LT	206	next_jiffy_time -= ticks_per_jiffy;
	207	}
	208
1da177e4 LT	209	return IRQ_HANDLED;
	210	}
	211
	212	static struct irqaction ixp2000_timer_irq = {
	213	.name = "IXP2000 Timer Tick",
b30fabad	214	.flags = IRQF_DISABLED \| IRQF_TIMER \| IRQF_IRQPOLL,
09b8b5f8	215	.handler = ixp2000_timer_interrupt,
1da177e4 LT	216	};
	217
	218	void __init ixp2000_init_time(unsigned long tick_rate)
	219	{
1da177e4 LT	220	ticks_per_jiffy = (tick_rate + HZ/2) / HZ;
	221	ticks_per_usec = tick_rate / 1000000;
	222
e4fe1981 LB	223	/*
	224	* We use timer 1 as our timer interrupt.
	225	*/
	226	ixp2000_reg_write(IXP2000_T1_CLR, 0);
1da177e4 LT	227	ixp2000_reg_write(IXP2000_T1_CLD, ticks_per_jiffy - 1);
	228	ixp2000_reg_write(IXP2000_T1_CTL, (1 << 7));
	229
	230	/*
e4fe1981 LB	231	* We use a second timer as a monotonic counter for tracking
	232	* missed jiffies. The IXP2000 has four timers, but if we're
	233	* on an A-step IXP2800, timer 2 and 3 don't work, so on those
	234	* chips we use timer 4. Timer 4 is the only timer that can
	235	* be used for the watchdog, so we use timer 2 if we're on a
	236	* non-buggy chip.
1da177e4	237	*/
e4fe1981 LB	238	if ((*IXP2000_PRODUCT_ID & 0x001ffef0) == 0x00000000) {
	239	printk(KERN_INFO "Enabling IXP2800 erratum #25 workaround\n");
	240
	241	ixp2000_reg_write(IXP2000_T4_CLR, 0);
	242	ixp2000_reg_write(IXP2000_T4_CLD, -1);
e9b72e43	243	ixp2000_reg_wrb(IXP2000_T4_CTL, (1 << 7));
e4fe1981 LB	244	missing_jiffy_timer_csr = IXP2000_T4_CSR;
	245	} else {
	246	ixp2000_reg_write(IXP2000_T2_CLR, 0);
	247	ixp2000_reg_write(IXP2000_T2_CLD, -1);
e9b72e43	248	ixp2000_reg_wrb(IXP2000_T2_CTL, (1 << 7));
e4fe1981 LB	249	missing_jiffy_timer_csr = IXP2000_T2_CSR;
e4fe1981 LB	250	}
1da177e4 LT	251	next_jiffy_time = 0xffffffff;
	252
	253	/* register for interrupt */
	254	setup_irq(IRQ_IXP2000_TIMER1, &ixp2000_timer_irq);
	255	}
	256
	257	/*************************************************************************
	258	* GPIO helpers
	259	*************************************************************************/
1da177e4	260	static unsigned long GPIO_IRQ_falling_edge;
c4982887	261	static unsigned long GPIO_IRQ_rising_edge;
1da177e4 LT	262	static unsigned long GPIO_IRQ_level_low;
	263	static unsigned long GPIO_IRQ_level_high;
	264
c4982887 LB	265	static void update_gpio_int_csrs(void)
	266	{
	267	ixp2000_reg_write(IXP2000_GPIO_FEDR, GPIO_IRQ_falling_edge);
	268	ixp2000_reg_write(IXP2000_GPIO_REDR, GPIO_IRQ_rising_edge);
	269	ixp2000_reg_write(IXP2000_GPIO_LSLR, GPIO_IRQ_level_low);
e9b72e43	270	ixp2000_reg_wrb(IXP2000_GPIO_LSHR, GPIO_IRQ_level_high);
c4982887 LB	271	}
	272
	273	void gpio_line_config(int line, int direction)
1da177e4 LT	274	{
	275	unsigned long flags;
	276
	277	local_irq_save(flags);
c4982887	278	if (direction == GPIO_OUT) {
1da177e4	279	/* if it's an output, it ain't an interrupt anymore */
1da177e4 LT	280	GPIO_IRQ_falling_edge &= ~(1 << line);
	281	GPIO_IRQ_rising_edge &= ~(1 << line);
	282	GPIO_IRQ_level_low &= ~(1 << line);
	283	GPIO_IRQ_level_high &= ~(1 << line);
c4982887 LB	284	update_gpio_int_csrs();
c4982887 LB	285
e9b72e43	286	ixp2000_reg_wrb(IXP2000_GPIO_PDSR, 1 << line);
c4982887	287	} else if (direction == GPIO_IN) {
e9b72e43	288	ixp2000_reg_wrb(IXP2000_GPIO_PDCR, 1 << line);
1da177e4	289	}
1da177e4	290	local_irq_restore(flags);
c4982887	291	}
fc8ea7a1	292	EXPORT_SYMBOL(gpio_line_config);
1da177e4 LT	293
	294
	295	/*************************************************************************
	296	* IRQ handling IXP2000
	297	*************************************************************************/
10dd5ce2	298	static void ixp2000_GPIO_irq_handler(unsigned int irq, struct irq_desc *desc)
1da177e4 LT	299	{
	300	int i;
	301	unsigned long status = *IXP2000_GPIO_INST;
	302
	303	for (i = 0; i <= 7; i++) {
	304	if (status & (1<<i)) {
d8aa0251	305	generic_handle_irq(i + IRQ_IXP2000_GPIO0);
1da177e4 LT	306	}
	307	}
	308	}
	309
6e8f54fa	310	static int ixp2000_GPIO_irq_type(struct irq_data *d, unsigned int type)
c4982887	311	{
6e8f54fa	312	int line = d->irq - IRQ_IXP2000_GPIO0;
c4982887 LB	313
	314	/*
	315	* First, configure this GPIO line as an input.
	316	*/
	317	ixp2000_reg_write(IXP2000_GPIO_PDCR, 1 << line);
	318
	319	/*
	320	* Then, set the proper trigger type.
	321	*/
6cab4860	322	if (type & IRQ_TYPE_EDGE_FALLING)
c4982887 LB	323	GPIO_IRQ_falling_edge \|= 1 << line;
	324	else
	325	GPIO_IRQ_falling_edge &= ~(1 << line);
6cab4860	326	if (type & IRQ_TYPE_EDGE_RISING)
c4982887 LB	327	GPIO_IRQ_rising_edge \|= 1 << line;
	328	else
	329	GPIO_IRQ_rising_edge &= ~(1 << line);
6cab4860	330	if (type & IRQ_TYPE_LEVEL_LOW)
c4982887 LB	331	GPIO_IRQ_level_low \|= 1 << line;
	332	else
	333	GPIO_IRQ_level_low &= ~(1 << line);
6cab4860	334	if (type & IRQ_TYPE_LEVEL_HIGH)
c4982887 LB	335	GPIO_IRQ_level_high \|= 1 << line;
	336	else
	337	GPIO_IRQ_level_high &= ~(1 << line);
	338	update_gpio_int_csrs();
	339
c4982887 LB	340	return 0;
	341	}
	342
6e8f54fa	343	static void ixp2000_GPIO_irq_mask_ack(struct irq_data *d)
1da177e4	344	{
6e8f54fa LB	345	unsigned int irq = d->irq;
6e8f54fa LB	346
1da177e4	347	ixp2000_reg_write(IXP2000_GPIO_INCR, (1 << (irq - IRQ_IXP2000_GPIO0)));
c4982887 LB	348
	349	ixp2000_reg_write(IXP2000_GPIO_EDSR, (1 << (irq - IRQ_IXP2000_GPIO0)));
	350	ixp2000_reg_write(IXP2000_GPIO_LDSR, (1 << (irq - IRQ_IXP2000_GPIO0)));
e9b72e43	351	ixp2000_reg_wrb(IXP2000_GPIO_INST, (1 << (irq - IRQ_IXP2000_GPIO0)));
1da177e4 LT	352	}
1da177e4 LT	353
6e8f54fa	354	static void ixp2000_GPIO_irq_mask(struct irq_data *d)
1da177e4	355	{
6e8f54fa LB	356	unsigned int irq = d->irq;
6e8f54fa LB	357
e9b72e43	358	ixp2000_reg_wrb(IXP2000_GPIO_INCR, (1 << (irq - IRQ_IXP2000_GPIO0)));
1da177e4 LT	359	}
1da177e4 LT	360
6e8f54fa	361	static void ixp2000_GPIO_irq_unmask(struct irq_data *d)
1da177e4	362	{
6e8f54fa LB	363	unsigned int irq = d->irq;
6e8f54fa LB	364
1da177e4 LT	365	ixp2000_reg_write(IXP2000_GPIO_INSR, (1 << (irq - IRQ_IXP2000_GPIO0)));
	366	}
	367
10dd5ce2	368	static struct irq_chip ixp2000_GPIO_irq_chip = {
6e8f54fa LB	369	.irq_ack = ixp2000_GPIO_irq_mask_ack,
	370	.irq_mask = ixp2000_GPIO_irq_mask,
	371	.irq_unmask = ixp2000_GPIO_irq_unmask,
	372	.irq_set_type = ixp2000_GPIO_irq_type,
1da177e4 LT	373	};
1da177e4 LT	374
6e8f54fa	375	static void ixp2000_pci_irq_mask(struct irq_data *d)
1da177e4 LT	376	{
1da177e4 LT	377	unsigned long temp = *IXP2000_PCI_XSCALE_INT_ENABLE;
6e8f54fa	378	if (d->irq == IRQ_IXP2000_PCIA)
e9b72e43	379	ixp2000_reg_wrb(IXP2000_PCI_XSCALE_INT_ENABLE, (temp & ~(1 << 26)));
6e8f54fa	380	else if (d->irq == IRQ_IXP2000_PCIB)
e9b72e43	381	ixp2000_reg_wrb(IXP2000_PCI_XSCALE_INT_ENABLE, (temp & ~(1 << 27)));
1da177e4 LT	382	}
1da177e4 LT	383
6e8f54fa	384	static void ixp2000_pci_irq_unmask(struct irq_data *d)
1da177e4 LT	385	{
1da177e4 LT	386	unsigned long temp = *IXP2000_PCI_XSCALE_INT_ENABLE;
6e8f54fa	387	if (d->irq == IRQ_IXP2000_PCIA)
1da177e4	388	ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp \| (1 << 26)));
6e8f54fa	389	else if (d->irq == IRQ_IXP2000_PCIB)
1da177e4 LT	390	ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp \| (1 << 27)));
	391	}
	392
7866f649 DJ	393	/*
	394	* Error interrupts. These are used extensively by the microengine drivers
	395	*/
10dd5ce2	396	static void ixp2000_err_irq_handler(unsigned int irq, struct irq_desc *desc)
7866f649 DJ	397	{
	398	int i;
	399	unsigned long status = *IXP2000_IRQ_ERR_STATUS;
	400
	401	for(i = 31; i >= 0; i--) {
	402	if(status & (1 << i)) {
d8aa0251	403	generic_handle_irq(IRQ_IXP2000_DRAM0_MIN_ERR + i);
7866f649 DJ	404	}
	405	}
	406	}
	407
6e8f54fa	408	static void ixp2000_err_irq_mask(struct irq_data *d)
7866f649 DJ	409	{
7866f649 DJ	410	ixp2000_reg_write(IXP2000_IRQ_ERR_ENABLE_CLR,
6e8f54fa	411	(1 << (d->irq - IRQ_IXP2000_DRAM0_MIN_ERR)));
7866f649 DJ	412	}
7866f649 DJ	413
6e8f54fa	414	static void ixp2000_err_irq_unmask(struct irq_data *d)
7866f649 DJ	415	{
7866f649 DJ	416	ixp2000_reg_write(IXP2000_IRQ_ERR_ENABLE_SET,
6e8f54fa	417	(1 << (d->irq - IRQ_IXP2000_DRAM0_MIN_ERR)));
7866f649 DJ	418	}
7866f649 DJ	419
10dd5ce2	420	static struct irq_chip ixp2000_err_irq_chip = {
6e8f54fa LB	421	.irq_ack = ixp2000_err_irq_mask,
	422	.irq_mask = ixp2000_err_irq_mask,
	423	.irq_unmask = ixp2000_err_irq_unmask
7866f649 DJ	424	};
7866f649 DJ	425
10dd5ce2	426	static struct irq_chip ixp2000_pci_irq_chip = {
6e8f54fa LB	427	.irq_ack = ixp2000_pci_irq_mask,
	428	.irq_mask = ixp2000_pci_irq_mask,
	429	.irq_unmask = ixp2000_pci_irq_unmask
1da177e4 LT	430	};
1da177e4 LT	431
6e8f54fa	432	static void ixp2000_irq_mask(struct irq_data *d)
1da177e4	433	{
6e8f54fa	434	ixp2000_reg_wrb(IXP2000_IRQ_ENABLE_CLR, (1 << d->irq));
1da177e4 LT	435	}
1da177e4 LT	436
6e8f54fa	437	static void ixp2000_irq_unmask(struct irq_data *d)
1da177e4	438	{
6e8f54fa	439	ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << d->irq));
1da177e4 LT	440	}
1da177e4 LT	441
10dd5ce2	442	static struct irq_chip ixp2000_irq_chip = {
6e8f54fa LB	443	.irq_ack = ixp2000_irq_mask,
	444	.irq_mask = ixp2000_irq_mask,
	445	.irq_unmask = ixp2000_irq_unmask
1da177e4 LT	446	};
	447
	448	void __init ixp2000_init_irq(void)
	449	{
	450	int irq;
	451
	452	/*
	453	* Mask all sources
	454	*/
	455	ixp2000_reg_write(IXP2000_IRQ_ENABLE_CLR, 0xffffffff);
	456	ixp2000_reg_write(IXP2000_FIQ_ENABLE_CLR, 0xffffffff);
	457
	458	/* clear all GPIO edge/level detects */
	459	ixp2000_reg_write(IXP2000_GPIO_REDR, 0);
	460	ixp2000_reg_write(IXP2000_GPIO_FEDR, 0);
	461	ixp2000_reg_write(IXP2000_GPIO_LSHR, 0);
	462	ixp2000_reg_write(IXP2000_GPIO_LSLR, 0);
	463	ixp2000_reg_write(IXP2000_GPIO_INCR, -1);
	464
	465	/* clear PCI interrupt sources */
e9b72e43	466	ixp2000_reg_wrb(IXP2000_PCI_XSCALE_INT_ENABLE, 0);
1da177e4 LT	467
	468	/*
	469	* Certain bits in the IRQ status register of the
	470	* IXP2000 are reserved. Instead of trying to map
	471	* things non 1:1 from bit position to IRQ number,
	472	* we mark the reserved IRQs as invalid. This makes
	473	* our mask/unmask code much simpler.
	474	*/
	475	for (irq = IRQ_IXP2000_SOFT_INT; irq <= IRQ_IXP2000_THDB3; irq++) {
c4982887	476	if ((1 << irq) & IXP2000_VALID_IRQ_MASK) {
f38c02f3 TG	477	irq_set_chip_and_handler(irq, &ixp2000_irq_chip,
f38c02f3 TG	478	handle_level_irq);
1da177e4 LT	479	set_irq_flags(irq, IRQF_VALID);
	480	} else set_irq_flags(irq, 0);
	481	}
c4982887	482
7866f649 DJ	483	for (irq = IRQ_IXP2000_DRAM0_MIN_ERR; irq <= IRQ_IXP2000_SP_INT; irq++) {
	484	if((1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)) &
	485	IXP2000_VALID_ERR_IRQ_MASK) {
f38c02f3 TG	486	irq_set_chip_and_handler(irq, &ixp2000_err_irq_chip,
f38c02f3 TG	487	handle_level_irq);
7866f649 DJ	488	set_irq_flags(irq, IRQF_VALID);
	489	}
	490	else
	491	set_irq_flags(irq, 0);
	492	}
6845664a	493	irq_set_chained_handler(IRQ_IXP2000_ERRSUM, ixp2000_err_irq_handler);
7866f649	494
1da177e4	495	for (irq = IRQ_IXP2000_GPIO0; irq <= IRQ_IXP2000_GPIO7; irq++) {
f38c02f3 TG	496	irq_set_chip_and_handler(irq, &ixp2000_GPIO_irq_chip,
f38c02f3 TG	497	handle_level_irq);
bd115ea0	498	set_irq_flags(irq, IRQF_VALID);
1da177e4	499	}
6845664a	500	irq_set_chained_handler(IRQ_IXP2000_GPIO, ixp2000_GPIO_irq_handler);
1da177e4 LT	501
	502	/*
	503	* Enable PCI irqs. The actual PCI[AB] decoding is done in
	504	* entry-macro.S, so we don't need a chained handler for the
	505	* PCI interrupt source.
	506	*/
	507	ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << IRQ_IXP2000_PCI));
	508	for (irq = IRQ_IXP2000_PCIA; irq <= IRQ_IXP2000_PCIB; irq++) {
f38c02f3 TG	509	irq_set_chip_and_handler(irq, &ixp2000_pci_irq_chip,
f38c02f3 TG	510	handle_level_irq);
1da177e4 LT	511	set_irq_flags(irq, IRQF_VALID);
	512	}
	513	}
	514