[mirror_ubuntu-artful-kernel.git] / arch / arm / mach-ixp2000 / core.c

/*
 * arch/arm/mach-ixp2000/core.c
 *
 * Common routines used by all IXP2400/2800 based platforms.
 *
 * Author: Deepak Saxena <dsaxena@plexity.net>
 *
 * Copyright 2004 (C) MontaVista Software, Inc. 
 *
 * Based on work Copyright (C) 2002-2003 Intel Corporation
 * 
 * This file is licensed under the terms of the GNU General Public
 * License version 2. This program is licensed "as is" without any 
 * warranty of any kind, whether express or implied.
 */

#include <linux/config.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/spinlock.h>
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/serial.h>
#include <linux/tty.h>
#include <linux/bitops.h>
#include <linux/serial_8250.h>
#include <linux/mm.h>

#include <asm/types.h>
#include <asm/setup.h>
#include <asm/memory.h>
#include <asm/hardware.h>
#include <asm/irq.h>
#include <asm/system.h>
#include <asm/tlbflush.h>
#include <asm/pgtable.h>

#include <asm/mach/map.h>
#include <asm/mach/time.h>
#include <asm/mach/irq.h>

#include <asm/arch/gpio.h>

static DEFINE_SPINLOCK(ixp2000_slowport_lock);
static unsigned long ixp2000_slowport_irq_flags;

/*************************************************************************
 * Slowport access routines
 *************************************************************************/
void ixp2000_acquire_slowport(struct slowport_cfg *new_cfg, struct slowport_cfg *old_cfg)
{
	spin_lock_irqsave(&ixp2000_slowport_lock, ixp2000_slowport_irq_flags);

	old_cfg->CCR = *IXP2000_SLOWPORT_CCR;
	old_cfg->WTC = *IXP2000_SLOWPORT_WTC2;
	old_cfg->RTC = *IXP2000_SLOWPORT_RTC2;
	old_cfg->PCR = *IXP2000_SLOWPORT_PCR;
	old_cfg->ADC = *IXP2000_SLOWPORT_ADC;

	ixp2000_reg_write(IXP2000_SLOWPORT_CCR, new_cfg->CCR);
	ixp2000_reg_write(IXP2000_SLOWPORT_WTC2, new_cfg->WTC);
	ixp2000_reg_write(IXP2000_SLOWPORT_RTC2, new_cfg->RTC);
	ixp2000_reg_write(IXP2000_SLOWPORT_PCR, new_cfg->PCR);
	ixp2000_reg_wrb(IXP2000_SLOWPORT_ADC, new_cfg->ADC);
}

void ixp2000_release_slowport(struct slowport_cfg *old_cfg)
{
	ixp2000_reg_write(IXP2000_SLOWPORT_CCR, old_cfg->CCR);
	ixp2000_reg_write(IXP2000_SLOWPORT_WTC2, old_cfg->WTC);
	ixp2000_reg_write(IXP2000_SLOWPORT_RTC2, old_cfg->RTC);
	ixp2000_reg_write(IXP2000_SLOWPORT_PCR, old_cfg->PCR);
	ixp2000_reg_wrb(IXP2000_SLOWPORT_ADC, old_cfg->ADC);

	spin_unlock_irqrestore(&ixp2000_slowport_lock, 
					ixp2000_slowport_irq_flags);
}

/*************************************************************************
 * Chip specific mappings shared by all IXP2000 systems
 *************************************************************************/
static struct map_desc ixp2000_io_desc[] __initdata = {
	{
		.virtual	= IXP2000_CAP_VIRT_BASE,
		.pfn		= __phys_to_pfn(IXP2000_CAP_PHYS_BASE),
		.length		= IXP2000_CAP_SIZE,
		.type		= MT_IXP2000_DEVICE,
	}, {
		.virtual	= IXP2000_INTCTL_VIRT_BASE,
		.pfn		= __phys_to_pfn(IXP2000_INTCTL_PHYS_BASE),
		.length		= IXP2000_INTCTL_SIZE,
		.type		= MT_IXP2000_DEVICE,
	}, {
		.virtual	= IXP2000_PCI_CREG_VIRT_BASE,
		.pfn		= __phys_to_pfn(IXP2000_PCI_CREG_PHYS_BASE),
		.length		= IXP2000_PCI_CREG_SIZE,
		.type		= MT_IXP2000_DEVICE,
	}, {
		.virtual	= IXP2000_PCI_CSR_VIRT_BASE,
		.pfn		= __phys_to_pfn(IXP2000_PCI_CSR_PHYS_BASE),
		.length		= IXP2000_PCI_CSR_SIZE,
		.type		= MT_IXP2000_DEVICE,
	}, {
		.virtual	= IXP2000_MSF_VIRT_BASE,
		.pfn		= __phys_to_pfn(IXP2000_MSF_PHYS_BASE),
		.length		= IXP2000_MSF_SIZE,
		.type		= MT_IXP2000_DEVICE,
	}, {
		.virtual	= IXP2000_PCI_IO_VIRT_BASE,
		.pfn		= __phys_to_pfn(IXP2000_PCI_IO_PHYS_BASE),
		.length		= IXP2000_PCI_IO_SIZE,
		.type		= MT_IXP2000_DEVICE,
	}, {
		.virtual	= IXP2000_PCI_CFG0_VIRT_BASE,
		.pfn		= __phys_to_pfn(IXP2000_PCI_CFG0_PHYS_BASE),
		.length		= IXP2000_PCI_CFG0_SIZE,
		.type		= MT_IXP2000_DEVICE,
	}, {
		.virtual	= IXP2000_PCI_CFG1_VIRT_BASE,
		.pfn		= __phys_to_pfn(IXP2000_PCI_CFG1_PHYS_BASE),
		.length		= IXP2000_PCI_CFG1_SIZE,
		.type		= MT_IXP2000_DEVICE,
	}
};

void __init ixp2000_map_io(void)
{
	/*
	 * On IXP2400 CPUs we need to use MT_IXP2000_DEVICE so that
	 * XCB=101 (to avoid triggering erratum #66), and given that
	 * this mode speeds up I/O accesses and we have write buffer
	 * flushes in the right places anyway, it doesn't hurt to use
	 * XCB=101 for all IXP2000s.
	 */
	iotable_init(ixp2000_io_desc, ARRAY_SIZE(ixp2000_io_desc));

	/* Set slowport to 8-bit mode.  */
	ixp2000_reg_wrb(IXP2000_SLOWPORT_FRM, 1);
}


/*************************************************************************
 * Serial port support for IXP2000
 *************************************************************************/
static struct plat_serial8250_port ixp2000_serial_port[] = {
	{
		.mapbase	= IXP2000_UART_PHYS_BASE,
		.membase	= (char *)(IXP2000_UART_VIRT_BASE + 3),
		.irq		= IRQ_IXP2000_UART,
		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
		.iotype		= UPIO_MEM,
		.regshift	= 2,
		.uartclk	= 50000000,
	},
	{ },
};

static struct resource ixp2000_uart_resource = {
	.start		= IXP2000_UART_PHYS_BASE,
	.end		= IXP2000_UART_PHYS_BASE + 0x1f,
	.flags		= IORESOURCE_MEM,
};

static struct platform_device ixp2000_serial_device = {
	.name		= "serial8250",
	.id		= PLAT8250_DEV_PLATFORM,
	.dev		= {
		.platform_data		= ixp2000_serial_port,
	},
	.num_resources	= 1,
	.resource	= &ixp2000_uart_resource,
};

void __init ixp2000_uart_init(void)
{
	platform_device_register(&ixp2000_serial_device);
}


/*************************************************************************
 * Timer-tick functions for IXP2000
 *************************************************************************/
static unsigned ticks_per_jiffy;
static unsigned ticks_per_usec;
static unsigned next_jiffy_time;
static volatile unsigned long *missing_jiffy_timer_csr;

unsigned long ixp2000_gettimeoffset (void)
{
 	unsigned long offset;

	offset = next_jiffy_time - *missing_jiffy_timer_csr;

	return offset / ticks_per_usec;
}

static int ixp2000_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
{
	write_seqlock(&xtime_lock);

	/* clear timer 1 */
	ixp2000_reg_wrb(IXP2000_T1_CLR, 1);

	while ((next_jiffy_time - *missing_jiffy_timer_csr) > ticks_per_jiffy) {
		timer_tick(regs);
		next_jiffy_time -= ticks_per_jiffy;
	}

	write_sequnlock(&xtime_lock);

	return IRQ_HANDLED;
}

static struct irqaction ixp2000_timer_irq = {
	.name		= "IXP2000 Timer Tick",
	.flags		= SA_INTERRUPT | SA_TIMER,
	.handler	= ixp2000_timer_interrupt,
};

void __init ixp2000_init_time(unsigned long tick_rate)
{
	ticks_per_jiffy = (tick_rate + HZ/2) / HZ;
	ticks_per_usec = tick_rate / 1000000;

	/*
	 * We use timer 1 as our timer interrupt.
	 */
	ixp2000_reg_write(IXP2000_T1_CLR, 0);
	ixp2000_reg_write(IXP2000_T1_CLD, ticks_per_jiffy - 1);
	ixp2000_reg_write(IXP2000_T1_CTL, (1 << 7));

	/*
	 * We use a second timer as a monotonic counter for tracking
	 * missed jiffies.  The IXP2000 has four timers, but if we're
	 * on an A-step IXP2800, timer 2 and 3 don't work, so on those
	 * chips we use timer 4.  Timer 4 is the only timer that can
	 * be used for the watchdog, so we use timer 2 if we're on a
	 * non-buggy chip.
	 */
	if ((*IXP2000_PRODUCT_ID & 0x001ffef0) == 0x00000000) {
		printk(KERN_INFO "Enabling IXP2800 erratum #25 workaround\n");

		ixp2000_reg_write(IXP2000_T4_CLR, 0);
		ixp2000_reg_write(IXP2000_T4_CLD, -1);
		ixp2000_reg_wrb(IXP2000_T4_CTL, (1 << 7));
		missing_jiffy_timer_csr = IXP2000_T4_CSR;
	} else {
		ixp2000_reg_write(IXP2000_T2_CLR, 0);
		ixp2000_reg_write(IXP2000_T2_CLD, -1);
		ixp2000_reg_wrb(IXP2000_T2_CTL, (1 << 7));
		missing_jiffy_timer_csr = IXP2000_T2_CSR;
	}
 	next_jiffy_time = 0xffffffff;

	/* register for interrupt */
	setup_irq(IRQ_IXP2000_TIMER1, &ixp2000_timer_irq);
}

/*************************************************************************
 * GPIO helpers
 *************************************************************************/
static unsigned long GPIO_IRQ_falling_edge;
static unsigned long GPIO_IRQ_rising_edge;
static unsigned long GPIO_IRQ_level_low;
static unsigned long GPIO_IRQ_level_high;

static void update_gpio_int_csrs(void)
{
	ixp2000_reg_write(IXP2000_GPIO_FEDR, GPIO_IRQ_falling_edge);
	ixp2000_reg_write(IXP2000_GPIO_REDR, GPIO_IRQ_rising_edge);
	ixp2000_reg_write(IXP2000_GPIO_LSLR, GPIO_IRQ_level_low);
	ixp2000_reg_wrb(IXP2000_GPIO_LSHR, GPIO_IRQ_level_high);
}

void gpio_line_config(int line, int direction)
{
	unsigned long flags;

	local_irq_save(flags);
	if (direction == GPIO_OUT) {
		irq_desc[line + IRQ_IXP2000_GPIO0].valid = 0;

		/* if it's an output, it ain't an interrupt anymore */
		GPIO_IRQ_falling_edge &= ~(1 << line);
		GPIO_IRQ_rising_edge &= ~(1 << line);
		GPIO_IRQ_level_low &= ~(1 << line);
		GPIO_IRQ_level_high &= ~(1 << line);
		update_gpio_int_csrs();

		ixp2000_reg_wrb(IXP2000_GPIO_PDSR, 1 << line);
	} else if (direction == GPIO_IN) {
		ixp2000_reg_wrb(IXP2000_GPIO_PDCR, 1 << line);
	}
	local_irq_restore(flags);
}


/*************************************************************************
 * IRQ handling IXP2000
 *************************************************************************/
static void ixp2000_GPIO_irq_handler(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
{                               
	int i;
	unsigned long status = *IXP2000_GPIO_INST;
		   
	for (i = 0; i <= 7; i++) {
		if (status & (1<<i)) {
			desc = irq_desc + i + IRQ_IXP2000_GPIO0;
			desc_handle_irq(i + IRQ_IXP2000_GPIO0, desc, regs);
		}
	}
}

static int ixp2000_GPIO_irq_type(unsigned int irq, unsigned int type)
{
	int line = irq - IRQ_IXP2000_GPIO0;

	/*
	 * First, configure this GPIO line as an input.
	 */
	ixp2000_reg_write(IXP2000_GPIO_PDCR, 1 << line);

	/*
	 * Then, set the proper trigger type.
	 */
	if (type & IRQT_FALLING)
		GPIO_IRQ_falling_edge |= 1 << line;
	else
		GPIO_IRQ_falling_edge &= ~(1 << line);
	if (type & IRQT_RISING)
		GPIO_IRQ_rising_edge |= 1 << line;
	else
		GPIO_IRQ_rising_edge &= ~(1 << line);
	if (type & IRQT_LOW)
		GPIO_IRQ_level_low |= 1 << line;
	else
		GPIO_IRQ_level_low &= ~(1 << line);
	if (type & IRQT_HIGH)
		GPIO_IRQ_level_high |= 1 << line;
	else
		GPIO_IRQ_level_high &= ~(1 << line);
	update_gpio_int_csrs();

	/*
	 * Finally, mark the corresponding IRQ as valid.
	 */
	irq_desc[irq].valid = 1;

	return 0;
}

static void ixp2000_GPIO_irq_mask_ack(unsigned int irq)
{
	ixp2000_reg_write(IXP2000_GPIO_INCR, (1 << (irq - IRQ_IXP2000_GPIO0)));

	ixp2000_reg_write(IXP2000_GPIO_EDSR, (1 << (irq - IRQ_IXP2000_GPIO0)));
	ixp2000_reg_write(IXP2000_GPIO_LDSR, (1 << (irq - IRQ_IXP2000_GPIO0)));
	ixp2000_reg_wrb(IXP2000_GPIO_INST, (1 << (irq - IRQ_IXP2000_GPIO0)));
}

static void ixp2000_GPIO_irq_mask(unsigned int irq)
{
	ixp2000_reg_wrb(IXP2000_GPIO_INCR, (1 << (irq - IRQ_IXP2000_GPIO0)));
}

static void ixp2000_GPIO_irq_unmask(unsigned int irq)
{
	ixp2000_reg_write(IXP2000_GPIO_INSR, (1 << (irq - IRQ_IXP2000_GPIO0)));
}

static struct irqchip ixp2000_GPIO_irq_chip = {
	.ack		= ixp2000_GPIO_irq_mask_ack,
	.mask		= ixp2000_GPIO_irq_mask,
	.unmask		= ixp2000_GPIO_irq_unmask,
	.set_type	= ixp2000_GPIO_irq_type,
};

static void ixp2000_pci_irq_mask(unsigned int irq)
{
	unsigned long temp = *IXP2000_PCI_XSCALE_INT_ENABLE;
	if (irq == IRQ_IXP2000_PCIA)
		ixp2000_reg_wrb(IXP2000_PCI_XSCALE_INT_ENABLE, (temp & ~(1 << 26)));
	else if (irq == IRQ_IXP2000_PCIB)
		ixp2000_reg_wrb(IXP2000_PCI_XSCALE_INT_ENABLE, (temp & ~(1 << 27)));
}

static void ixp2000_pci_irq_unmask(unsigned int irq)
{
	unsigned long temp = *IXP2000_PCI_XSCALE_INT_ENABLE;
	if (irq == IRQ_IXP2000_PCIA)
		ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp | (1 << 26)));
	else if (irq == IRQ_IXP2000_PCIB)
		ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp | (1 << 27)));
}

/*
 * Error interrupts. These are used extensively by the microengine drivers
 */
static void ixp2000_err_irq_handler(unsigned int irq, struct irqdesc *desc,  struct pt_regs *regs)
{
	int i;
	unsigned long status = *IXP2000_IRQ_ERR_STATUS;

	for(i = 31; i >= 0; i--) {
		if(status & (1 << i)) {
			desc = irq_desc + IRQ_IXP2000_DRAM0_MIN_ERR + i;
			desc->handle(IRQ_IXP2000_DRAM0_MIN_ERR + i, desc, regs);
		}
	}
}

static void ixp2000_err_irq_mask(unsigned int irq)
{
	ixp2000_reg_write(IXP2000_IRQ_ERR_ENABLE_CLR,
			(1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)));
}

static void ixp2000_err_irq_unmask(unsigned int irq)
{
	ixp2000_reg_write(IXP2000_IRQ_ERR_ENABLE_SET,
			(1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)));
}

static struct irqchip ixp2000_err_irq_chip = {
	.ack	= ixp2000_err_irq_mask,
	.mask	= ixp2000_err_irq_mask,
	.unmask	= ixp2000_err_irq_unmask
};

static struct irqchip ixp2000_pci_irq_chip = {
	.ack	= ixp2000_pci_irq_mask,
	.mask	= ixp2000_pci_irq_mask,
	.unmask	= ixp2000_pci_irq_unmask
};

static void ixp2000_irq_mask(unsigned int irq)
{
	ixp2000_reg_wrb(IXP2000_IRQ_ENABLE_CLR, (1 << irq));
}

static void ixp2000_irq_unmask(unsigned int irq)
{
	ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << irq));
}

static struct irqchip ixp2000_irq_chip = {
	.ack	= ixp2000_irq_mask,
	.mask	= ixp2000_irq_mask,
	.unmask	= ixp2000_irq_unmask
};

void __init ixp2000_init_irq(void)
{
	int irq;

	/*
	 * Mask all sources
	 */
	ixp2000_reg_write(IXP2000_IRQ_ENABLE_CLR, 0xffffffff);
	ixp2000_reg_write(IXP2000_FIQ_ENABLE_CLR, 0xffffffff);

	/* clear all GPIO edge/level detects */
	ixp2000_reg_write(IXP2000_GPIO_REDR, 0);
	ixp2000_reg_write(IXP2000_GPIO_FEDR, 0);
	ixp2000_reg_write(IXP2000_GPIO_LSHR, 0);
	ixp2000_reg_write(IXP2000_GPIO_LSLR, 0);
	ixp2000_reg_write(IXP2000_GPIO_INCR, -1);

	/* clear PCI interrupt sources */
	ixp2000_reg_wrb(IXP2000_PCI_XSCALE_INT_ENABLE, 0);

	/*
	 * Certain bits in the IRQ status register of the 
	 * IXP2000 are reserved. Instead of trying to map
	 * things non 1:1 from bit position to IRQ number,
	 * we mark the reserved IRQs as invalid. This makes
	 * our mask/unmask code much simpler.
	 */
	for (irq = IRQ_IXP2000_SOFT_INT; irq <= IRQ_IXP2000_THDB3; irq++) {
		if ((1 << irq) & IXP2000_VALID_IRQ_MASK) {
			set_irq_chip(irq, &ixp2000_irq_chip);
			set_irq_handler(irq, do_level_IRQ);
			set_irq_flags(irq, IRQF_VALID);
		} else set_irq_flags(irq, 0);
	}

	for (irq = IRQ_IXP2000_DRAM0_MIN_ERR; irq <= IRQ_IXP2000_SP_INT; irq++) {
		if((1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)) &
				IXP2000_VALID_ERR_IRQ_MASK) {
			set_irq_chip(irq, &ixp2000_err_irq_chip);
			set_irq_handler(irq, do_level_IRQ);
			set_irq_flags(irq, IRQF_VALID);
		}
		else
			set_irq_flags(irq, 0);
	}
	set_irq_chained_handler(IRQ_IXP2000_ERRSUM, ixp2000_err_irq_handler);

	/*
	 * GPIO IRQs are invalid until someone sets the interrupt mode
	 * by calling set_irq_type().
	 */
	for (irq = IRQ_IXP2000_GPIO0; irq <= IRQ_IXP2000_GPIO7; irq++) {
		set_irq_chip(irq, &ixp2000_GPIO_irq_chip);
		set_irq_handler(irq, do_level_IRQ);
		set_irq_flags(irq, 0);
	}
	set_irq_chained_handler(IRQ_IXP2000_GPIO, ixp2000_GPIO_irq_handler);

	/*
	 * Enable PCI irqs.  The actual PCI[AB] decoding is done in
	 * entry-macro.S, so we don't need a chained handler for the
	 * PCI interrupt source.
	 */
	ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << IRQ_IXP2000_PCI));
	for (irq = IRQ_IXP2000_PCIA; irq <= IRQ_IXP2000_PCIB; irq++) {
		set_irq_chip(irq, &ixp2000_pci_irq_chip);
		set_irq_handler(irq, do_level_IRQ);
		set_irq_flags(irq, IRQF_VALID);
	}
}
Commit	Line	Data
1da177e4	1	/*
fa87cedd	2	* arch/arm/mach-ixp2000/core.c
1da177e4 LT	3	*
	4	* Common routines used by all IXP2400/2800 based platforms.
	5	*
	6	* Author: Deepak Saxena <dsaxena@plexity.net>
	7	*
	8	* Copyright 2004 (C) MontaVista Software, Inc.
	9	*
	10	* Based on work Copyright (C) 2002-2003 Intel Corporation
	11	*
	12	* This file is licensed under the terms of the GNU General Public
	13	* License version 2. This program is licensed "as is" without any
	14	* warranty of any kind, whether express or implied.
	15	*/
	16
	17	#include <linux/config.h>
	18	#include <linux/kernel.h>
	19	#include <linux/init.h>
	20	#include <linux/spinlock.h>
	21	#include <linux/sched.h>
	22	#include <linux/interrupt.h>
	23	#include <linux/serial.h>
	24	#include <linux/tty.h>
	25	#include <linux/bitops.h>
28187f2c	26	#include <linux/serial_8250.h>
1da177e4 LT	27	#include <linux/mm.h>
	28
	29	#include <asm/types.h>
	30	#include <asm/setup.h>
	31	#include <asm/memory.h>
	32	#include <asm/hardware.h>
1da177e4 LT	33	#include <asm/irq.h>
	34	#include <asm/system.h>
	35	#include <asm/tlbflush.h>
	36	#include <asm/pgtable.h>
	37
	38	#include <asm/mach/map.h>
	39	#include <asm/mach/time.h>
	40	#include <asm/mach/irq.h>
	41
c4982887 LB	42	#include <asm/arch/gpio.h>
c4982887 LB	43
1da177e4 LT	44	static DEFINE_SPINLOCK(ixp2000_slowport_lock);
	45	static unsigned long ixp2000_slowport_irq_flags;
	46
	47	/*************************************************************************
	48	* Slowport access routines
	49	*************************************************************************/
	50	void ixp2000_acquire_slowport(struct slowport_cfg new_cfg, struct slowport_cfg old_cfg)
	51	{
1da177e4 LT	52	spin_lock_irqsave(&ixp2000_slowport_lock, ixp2000_slowport_irq_flags);
	53
	54	old_cfg->CCR = *IXP2000_SLOWPORT_CCR;
	55	old_cfg->WTC = *IXP2000_SLOWPORT_WTC2;
	56	old_cfg->RTC = *IXP2000_SLOWPORT_RTC2;
	57	old_cfg->PCR = *IXP2000_SLOWPORT_PCR;
	58	old_cfg->ADC = *IXP2000_SLOWPORT_ADC;
	59
	60	ixp2000_reg_write(IXP2000_SLOWPORT_CCR, new_cfg->CCR);
	61	ixp2000_reg_write(IXP2000_SLOWPORT_WTC2, new_cfg->WTC);
	62	ixp2000_reg_write(IXP2000_SLOWPORT_RTC2, new_cfg->RTC);
	63	ixp2000_reg_write(IXP2000_SLOWPORT_PCR, new_cfg->PCR);
e9b72e43	64	ixp2000_reg_wrb(IXP2000_SLOWPORT_ADC, new_cfg->ADC);
1da177e4 LT	65	}
	66
	67	void ixp2000_release_slowport(struct slowport_cfg *old_cfg)
	68	{
	69	ixp2000_reg_write(IXP2000_SLOWPORT_CCR, old_cfg->CCR);
	70	ixp2000_reg_write(IXP2000_SLOWPORT_WTC2, old_cfg->WTC);
	71	ixp2000_reg_write(IXP2000_SLOWPORT_RTC2, old_cfg->RTC);
	72	ixp2000_reg_write(IXP2000_SLOWPORT_PCR, old_cfg->PCR);
e9b72e43	73	ixp2000_reg_wrb(IXP2000_SLOWPORT_ADC, old_cfg->ADC);
1da177e4 LT	74
	75	spin_unlock_irqrestore(&ixp2000_slowport_lock,
	76	ixp2000_slowport_irq_flags);
	77	}
	78
	79	/*************************************************************************
	80	* Chip specific mappings shared by all IXP2000 systems
	81	*************************************************************************/
	82	static struct map_desc ixp2000_io_desc[] __initdata = {
	83	{
	84	.virtual = IXP2000_CAP_VIRT_BASE,
db0d087e	85	.pfn = __phys_to_pfn(IXP2000_CAP_PHYS_BASE),
1da177e4	86	.length = IXP2000_CAP_SIZE,
5391473f	87	.type = MT_IXP2000_DEVICE,
1da177e4 LT	88	}, {
1da177e4 LT	89	.virtual = IXP2000_INTCTL_VIRT_BASE,
db0d087e	90	.pfn = __phys_to_pfn(IXP2000_INTCTL_PHYS_BASE),
1da177e4	91	.length = IXP2000_INTCTL_SIZE,
5391473f	92	.type = MT_IXP2000_DEVICE,
1da177e4 LT	93	}, {
1da177e4 LT	94	.virtual = IXP2000_PCI_CREG_VIRT_BASE,
db0d087e	95	.pfn = __phys_to_pfn(IXP2000_PCI_CREG_PHYS_BASE),
1da177e4	96	.length = IXP2000_PCI_CREG_SIZE,
5391473f	97	.type = MT_IXP2000_DEVICE,
1da177e4 LT	98	}, {
1da177e4 LT	99	.virtual = IXP2000_PCI_CSR_VIRT_BASE,
db0d087e	100	.pfn = __phys_to_pfn(IXP2000_PCI_CSR_PHYS_BASE),
1da177e4	101	.length = IXP2000_PCI_CSR_SIZE,
5391473f	102	.type = MT_IXP2000_DEVICE,
baaf7ed1 LB	103	}, {
baaf7ed1 LB	104	.virtual = IXP2000_MSF_VIRT_BASE,
db0d087e	105	.pfn = __phys_to_pfn(IXP2000_MSF_PHYS_BASE),
baaf7ed1	106	.length = IXP2000_MSF_SIZE,
5391473f	107	.type = MT_IXP2000_DEVICE,
1da177e4 LT	108	}, {
1da177e4 LT	109	.virtual = IXP2000_PCI_IO_VIRT_BASE,
db0d087e	110	.pfn = __phys_to_pfn(IXP2000_PCI_IO_PHYS_BASE),
1da177e4	111	.length = IXP2000_PCI_IO_SIZE,
5391473f	112	.type = MT_IXP2000_DEVICE,
1da177e4 LT	113	}, {
1da177e4 LT	114	.virtual = IXP2000_PCI_CFG0_VIRT_BASE,
db0d087e	115	.pfn = __phys_to_pfn(IXP2000_PCI_CFG0_PHYS_BASE),
1da177e4	116	.length = IXP2000_PCI_CFG0_SIZE,
5391473f	117	.type = MT_IXP2000_DEVICE,
1da177e4 LT	118	}, {
1da177e4 LT	119	.virtual = IXP2000_PCI_CFG1_VIRT_BASE,
db0d087e	120	.pfn = __phys_to_pfn(IXP2000_PCI_CFG1_PHYS_BASE),
1da177e4	121	.length = IXP2000_PCI_CFG1_SIZE,
5391473f	122	.type = MT_IXP2000_DEVICE,
1da177e4 LT	123	}
	124	};
	125
1da177e4 LT	126	void __init ixp2000_map_io(void)
1da177e4 LT	127	{
1da177e4	128	/*
5391473f LB	129	* On IXP2400 CPUs we need to use MT_IXP2000_DEVICE so that
	130	* XCB=101 (to avoid triggering erratum #66), and given that
	131	* this mode speeds up I/O accesses and we have write buffer
	132	* flushes in the right places anyway, it doesn't hurt to use
	133	* XCB=101 for all IXP2000s.
1da177e4	134	*/
1da177e4	135	iotable_init(ixp2000_io_desc, ARRAY_SIZE(ixp2000_io_desc));
1da177e4 LT	136
1da177e4 LT	137	/* Set slowport to 8-bit mode. */
e9b72e43	138	ixp2000_reg_wrb(IXP2000_SLOWPORT_FRM, 1);
1da177e4 LT	139	}
1da177e4 LT	140
28187f2c LB	141
	142	/*************************************************************************
	143	* Serial port support for IXP2000
	144	*************************************************************************/
	145	static struct plat_serial8250_port ixp2000_serial_port[] = {
	146	{
	147	.mapbase = IXP2000_UART_PHYS_BASE,
	148	.membase = (char *)(IXP2000_UART_VIRT_BASE + 3),
	149	.irq = IRQ_IXP2000_UART,
	150	.flags = UPF_BOOT_AUTOCONF \| UPF_SKIP_TEST,
	151	.iotype = UPIO_MEM,
	152	.regshift = 2,
	153	.uartclk = 50000000,
	154	},
	155	{ },
	156	};
	157
	158	static struct resource ixp2000_uart_resource = {
	159	.start = IXP2000_UART_PHYS_BASE,
702c96d5	160	.end = IXP2000_UART_PHYS_BASE + 0x1f,
28187f2c LB	161	.flags = IORESOURCE_MEM,
	162	};
	163
	164	static struct platform_device ixp2000_serial_device = {
	165	.name = "serial8250",
6df29deb	166	.id = PLAT8250_DEV_PLATFORM,
28187f2c LB	167	.dev = {
	168	.platform_data = ixp2000_serial_port,
	169	},
	170	.num_resources = 1,
	171	.resource = &ixp2000_uart_resource,
	172	};
	173
	174	void __init ixp2000_uart_init(void)
	175	{
	176	platform_device_register(&ixp2000_serial_device);
	177	}
	178
	179
1da177e4 LT	180	/*************************************************************************
	181	* Timer-tick functions for IXP2000
	182	*************************************************************************/
	183	static unsigned ticks_per_jiffy;
	184	static unsigned ticks_per_usec;
	185	static unsigned next_jiffy_time;
e4fe1981	186	static volatile unsigned long *missing_jiffy_timer_csr;
1da177e4 LT	187
	188	unsigned long ixp2000_gettimeoffset (void)
	189	{
	190	unsigned long offset;
	191
e4fe1981	192	offset = next_jiffy_time - *missing_jiffy_timer_csr;
1da177e4 LT	193
	194	return offset / ticks_per_usec;
	195	}
	196
	197	static int ixp2000_timer_interrupt(int irq, void dev_id, struct pt_regs regs)
	198	{
	199	write_seqlock(&xtime_lock);
	200
	201	/* clear timer 1 */
e9b72e43	202	ixp2000_reg_wrb(IXP2000_T1_CLR, 1);
c4982887	203
e4fe1981	204	while ((next_jiffy_time - *missing_jiffy_timer_csr) > ticks_per_jiffy) {
1da177e4 LT	205	timer_tick(regs);
	206	next_jiffy_time -= ticks_per_jiffy;
	207	}
	208
	209	write_sequnlock(&xtime_lock);
	210
	211	return IRQ_HANDLED;
	212	}
	213
	214	static struct irqaction ixp2000_timer_irq = {
	215	.name = "IXP2000 Timer Tick",
09b8b5f8 RK	216	.flags = SA_INTERRUPT \| SA_TIMER,
09b8b5f8 RK	217	.handler = ixp2000_timer_interrupt,
1da177e4 LT	218	};
	219
	220	void __init ixp2000_init_time(unsigned long tick_rate)
	221	{
1da177e4 LT	222	ticks_per_jiffy = (tick_rate + HZ/2) / HZ;
	223	ticks_per_usec = tick_rate / 1000000;
	224
e4fe1981 LB	225	/*
	226	* We use timer 1 as our timer interrupt.
	227	*/
	228	ixp2000_reg_write(IXP2000_T1_CLR, 0);
1da177e4 LT	229	ixp2000_reg_write(IXP2000_T1_CLD, ticks_per_jiffy - 1);
	230	ixp2000_reg_write(IXP2000_T1_CTL, (1 << 7));
	231
	232	/*
e4fe1981 LB	233	* We use a second timer as a monotonic counter for tracking
	234	* missed jiffies. The IXP2000 has four timers, but if we're
	235	* on an A-step IXP2800, timer 2 and 3 don't work, so on those
	236	* chips we use timer 4. Timer 4 is the only timer that can
	237	* be used for the watchdog, so we use timer 2 if we're on a
	238	* non-buggy chip.
1da177e4	239	*/
e4fe1981 LB	240	if ((*IXP2000_PRODUCT_ID & 0x001ffef0) == 0x00000000) {
	241	printk(KERN_INFO "Enabling IXP2800 erratum #25 workaround\n");
	242
	243	ixp2000_reg_write(IXP2000_T4_CLR, 0);
	244	ixp2000_reg_write(IXP2000_T4_CLD, -1);
e9b72e43	245	ixp2000_reg_wrb(IXP2000_T4_CTL, (1 << 7));
e4fe1981 LB	246	missing_jiffy_timer_csr = IXP2000_T4_CSR;
	247	} else {
	248	ixp2000_reg_write(IXP2000_T2_CLR, 0);
	249	ixp2000_reg_write(IXP2000_T2_CLD, -1);
e9b72e43	250	ixp2000_reg_wrb(IXP2000_T2_CTL, (1 << 7));
e4fe1981 LB	251	missing_jiffy_timer_csr = IXP2000_T2_CSR;
e4fe1981 LB	252	}
1da177e4 LT	253	next_jiffy_time = 0xffffffff;
	254
	255	/* register for interrupt */
	256	setup_irq(IRQ_IXP2000_TIMER1, &ixp2000_timer_irq);
	257	}
	258
	259	/*************************************************************************
	260	* GPIO helpers
	261	*************************************************************************/
1da177e4	262	static unsigned long GPIO_IRQ_falling_edge;
c4982887	263	static unsigned long GPIO_IRQ_rising_edge;
1da177e4 LT	264	static unsigned long GPIO_IRQ_level_low;
	265	static unsigned long GPIO_IRQ_level_high;
	266
c4982887 LB	267	static void update_gpio_int_csrs(void)
	268	{
	269	ixp2000_reg_write(IXP2000_GPIO_FEDR, GPIO_IRQ_falling_edge);
	270	ixp2000_reg_write(IXP2000_GPIO_REDR, GPIO_IRQ_rising_edge);
	271	ixp2000_reg_write(IXP2000_GPIO_LSLR, GPIO_IRQ_level_low);
e9b72e43	272	ixp2000_reg_wrb(IXP2000_GPIO_LSHR, GPIO_IRQ_level_high);
c4982887 LB	273	}
	274
	275	void gpio_line_config(int line, int direction)
1da177e4 LT	276	{
	277	unsigned long flags;
	278
	279	local_irq_save(flags);
c4982887 LB	280	if (direction == GPIO_OUT) {
c4982887 LB	281	irq_desc[line + IRQ_IXP2000_GPIO0].valid = 0;
1da177e4	282
1da177e4	283	/* if it's an output, it ain't an interrupt anymore */
1da177e4 LT	284	GPIO_IRQ_falling_edge &= ~(1 << line);
	285	GPIO_IRQ_rising_edge &= ~(1 << line);
	286	GPIO_IRQ_level_low &= ~(1 << line);
	287	GPIO_IRQ_level_high &= ~(1 << line);
c4982887 LB	288	update_gpio_int_csrs();
c4982887 LB	289
e9b72e43	290	ixp2000_reg_wrb(IXP2000_GPIO_PDSR, 1 << line);
c4982887	291	} else if (direction == GPIO_IN) {
e9b72e43	292	ixp2000_reg_wrb(IXP2000_GPIO_PDCR, 1 << line);
1da177e4	293	}
1da177e4	294	local_irq_restore(flags);
c4982887	295	}
1da177e4 LT	296
	297
	298	/*************************************************************************
	299	* IRQ handling IXP2000
	300	*************************************************************************/
	301	static void ixp2000_GPIO_irq_handler(unsigned int irq, struct irqdesc desc, struct pt_regs regs)
	302	{
	303	int i;
	304	unsigned long status = *IXP2000_GPIO_INST;
	305
	306	for (i = 0; i <= 7; i++) {
	307	if (status & (1<<i)) {
	308	desc = irq_desc + i + IRQ_IXP2000_GPIO0;
664399e1	309	desc_handle_irq(i + IRQ_IXP2000_GPIO0, desc, regs);
1da177e4 LT	310	}
	311	}
	312	}
	313
c4982887 LB	314	static int ixp2000_GPIO_irq_type(unsigned int irq, unsigned int type)
	315	{
	316	int line = irq - IRQ_IXP2000_GPIO0;
	317
	318	/*
	319	* First, configure this GPIO line as an input.
	320	*/
	321	ixp2000_reg_write(IXP2000_GPIO_PDCR, 1 << line);
	322
	323	/*
	324	* Then, set the proper trigger type.
	325	*/
	326	if (type & IRQT_FALLING)
	327	GPIO_IRQ_falling_edge \|= 1 << line;
	328	else
	329	GPIO_IRQ_falling_edge &= ~(1 << line);
	330	if (type & IRQT_RISING)
	331	GPIO_IRQ_rising_edge \|= 1 << line;
	332	else
	333	GPIO_IRQ_rising_edge &= ~(1 << line);
	334	if (type & IRQT_LOW)
	335	GPIO_IRQ_level_low \|= 1 << line;
	336	else
	337	GPIO_IRQ_level_low &= ~(1 << line);
	338	if (type & IRQT_HIGH)
	339	GPIO_IRQ_level_high \|= 1 << line;
	340	else
	341	GPIO_IRQ_level_high &= ~(1 << line);
	342	update_gpio_int_csrs();
	343
	344	/*
	345	* Finally, mark the corresponding IRQ as valid.
	346	*/
	347	irq_desc[irq].valid = 1;
	348
	349	return 0;
	350	}
	351
1da177e4 LT	352	static void ixp2000_GPIO_irq_mask_ack(unsigned int irq)
	353	{
	354	ixp2000_reg_write(IXP2000_GPIO_INCR, (1 << (irq - IRQ_IXP2000_GPIO0)));
c4982887 LB	355
	356	ixp2000_reg_write(IXP2000_GPIO_EDSR, (1 << (irq - IRQ_IXP2000_GPIO0)));
	357	ixp2000_reg_write(IXP2000_GPIO_LDSR, (1 << (irq - IRQ_IXP2000_GPIO0)));
e9b72e43	358	ixp2000_reg_wrb(IXP2000_GPIO_INST, (1 << (irq - IRQ_IXP2000_GPIO0)));
1da177e4 LT	359	}
	360
	361	static void ixp2000_GPIO_irq_mask(unsigned int irq)
	362	{
e9b72e43	363	ixp2000_reg_wrb(IXP2000_GPIO_INCR, (1 << (irq - IRQ_IXP2000_GPIO0)));
1da177e4 LT	364	}
	365
	366	static void ixp2000_GPIO_irq_unmask(unsigned int irq)
	367	{
	368	ixp2000_reg_write(IXP2000_GPIO_INSR, (1 << (irq - IRQ_IXP2000_GPIO0)));
	369	}
	370
	371	static struct irqchip ixp2000_GPIO_irq_chip = {
7801907b RK	372	.ack = ixp2000_GPIO_irq_mask_ack,
7801907b RK	373	.mask = ixp2000_GPIO_irq_mask,
2be863c9	374	.unmask = ixp2000_GPIO_irq_unmask,
7801907b	375	.set_type = ixp2000_GPIO_irq_type,
1da177e4 LT	376	};
	377
	378	static void ixp2000_pci_irq_mask(unsigned int irq)
	379	{
	380	unsigned long temp = *IXP2000_PCI_XSCALE_INT_ENABLE;
	381	if (irq == IRQ_IXP2000_PCIA)
e9b72e43	382	ixp2000_reg_wrb(IXP2000_PCI_XSCALE_INT_ENABLE, (temp & ~(1 << 26)));
1da177e4	383	else if (irq == IRQ_IXP2000_PCIB)
e9b72e43	384	ixp2000_reg_wrb(IXP2000_PCI_XSCALE_INT_ENABLE, (temp & ~(1 << 27)));
1da177e4 LT	385	}
	386
	387	static void ixp2000_pci_irq_unmask(unsigned int irq)
	388	{
	389	unsigned long temp = *IXP2000_PCI_XSCALE_INT_ENABLE;
	390	if (irq == IRQ_IXP2000_PCIA)
	391	ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp \| (1 << 26)));
	392	else if (irq == IRQ_IXP2000_PCIB)
	393	ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp \| (1 << 27)));
	394	}
	395
7866f649 DJ	396	/*
	397	* Error interrupts. These are used extensively by the microengine drivers
	398	*/
	399	static void ixp2000_err_irq_handler(unsigned int irq, struct irqdesc desc, struct pt_regs regs)
	400	{
	401	int i;
	402	unsigned long status = *IXP2000_IRQ_ERR_STATUS;
	403
	404	for(i = 31; i >= 0; i--) {
	405	if(status & (1 << i)) {
	406	desc = irq_desc + IRQ_IXP2000_DRAM0_MIN_ERR + i;
	407	desc->handle(IRQ_IXP2000_DRAM0_MIN_ERR + i, desc, regs);
	408	}
	409	}
	410	}
	411
	412	static void ixp2000_err_irq_mask(unsigned int irq)
	413	{
	414	ixp2000_reg_write(IXP2000_IRQ_ERR_ENABLE_CLR,
	415	(1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)));
	416	}
	417
	418	static void ixp2000_err_irq_unmask(unsigned int irq)
	419	{
	420	ixp2000_reg_write(IXP2000_IRQ_ERR_ENABLE_SET,
	421	(1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)));
	422	}
	423
	424	static struct irqchip ixp2000_err_irq_chip = {
	425	.ack = ixp2000_err_irq_mask,
	426	.mask = ixp2000_err_irq_mask,
	427	.unmask = ixp2000_err_irq_unmask
	428	};
	429
1da177e4 LT	430	static struct irqchip ixp2000_pci_irq_chip = {
	431	.ack = ixp2000_pci_irq_mask,
	432	.mask = ixp2000_pci_irq_mask,
	433	.unmask = ixp2000_pci_irq_unmask
	434	};
	435
	436	static void ixp2000_irq_mask(unsigned int irq)
	437	{
e9b72e43	438	ixp2000_reg_wrb(IXP2000_IRQ_ENABLE_CLR, (1 << irq));
1da177e4 LT	439	}
	440
	441	static void ixp2000_irq_unmask(unsigned int irq)
	442	{
c4982887	443	ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << irq));
1da177e4 LT	444	}
	445
	446	static struct irqchip ixp2000_irq_chip = {
	447	.ack = ixp2000_irq_mask,
	448	.mask = ixp2000_irq_mask,
	449	.unmask = ixp2000_irq_unmask
	450	};
	451
	452	void __init ixp2000_init_irq(void)
	453	{
	454	int irq;
	455
	456	/*
	457	* Mask all sources
	458	*/
	459	ixp2000_reg_write(IXP2000_IRQ_ENABLE_CLR, 0xffffffff);
	460	ixp2000_reg_write(IXP2000_FIQ_ENABLE_CLR, 0xffffffff);
	461
	462	/* clear all GPIO edge/level detects */
	463	ixp2000_reg_write(IXP2000_GPIO_REDR, 0);
	464	ixp2000_reg_write(IXP2000_GPIO_FEDR, 0);
	465	ixp2000_reg_write(IXP2000_GPIO_LSHR, 0);
	466	ixp2000_reg_write(IXP2000_GPIO_LSLR, 0);
	467	ixp2000_reg_write(IXP2000_GPIO_INCR, -1);
	468
	469	/* clear PCI interrupt sources */
e9b72e43	470	ixp2000_reg_wrb(IXP2000_PCI_XSCALE_INT_ENABLE, 0);
1da177e4 LT	471
	472	/*
	473	* Certain bits in the IRQ status register of the
	474	* IXP2000 are reserved. Instead of trying to map
	475	* things non 1:1 from bit position to IRQ number,
	476	* we mark the reserved IRQs as invalid. This makes
	477	* our mask/unmask code much simpler.
	478	*/
	479	for (irq = IRQ_IXP2000_SOFT_INT; irq <= IRQ_IXP2000_THDB3; irq++) {
c4982887	480	if ((1 << irq) & IXP2000_VALID_IRQ_MASK) {
1da177e4 LT	481	set_irq_chip(irq, &ixp2000_irq_chip);
	482	set_irq_handler(irq, do_level_IRQ);
	483	set_irq_flags(irq, IRQF_VALID);
	484	} else set_irq_flags(irq, 0);
	485	}
c4982887	486
7866f649 DJ	487	for (irq = IRQ_IXP2000_DRAM0_MIN_ERR; irq <= IRQ_IXP2000_SP_INT; irq++) {
	488	if((1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)) &
	489	IXP2000_VALID_ERR_IRQ_MASK) {
	490	set_irq_chip(irq, &ixp2000_err_irq_chip);
	491	set_irq_handler(irq, do_level_IRQ);
	492	set_irq_flags(irq, IRQF_VALID);
	493	}
	494	else
	495	set_irq_flags(irq, 0);
	496	}
	497	set_irq_chained_handler(IRQ_IXP2000_ERRSUM, ixp2000_err_irq_handler);
	498
1da177e4 LT	499	/*
1da177e4 LT	500	* GPIO IRQs are invalid until someone sets the interrupt mode
c4982887	501	* by calling set_irq_type().
1da177e4 LT	502	*/
	503	for (irq = IRQ_IXP2000_GPIO0; irq <= IRQ_IXP2000_GPIO7; irq++) {
	504	set_irq_chip(irq, &ixp2000_GPIO_irq_chip);
	505	set_irq_handler(irq, do_level_IRQ);
	506	set_irq_flags(irq, 0);
	507	}
	508	set_irq_chained_handler(IRQ_IXP2000_GPIO, ixp2000_GPIO_irq_handler);
	509
	510	/*
	511	* Enable PCI irqs. The actual PCI[AB] decoding is done in
	512	* entry-macro.S, so we don't need a chained handler for the
	513	* PCI interrupt source.
	514	*/
	515	ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << IRQ_IXP2000_PCI));
	516	for (irq = IRQ_IXP2000_PCIA; irq <= IRQ_IXP2000_PCIB; irq++) {
	517	set_irq_chip(irq, &ixp2000_pci_irq_chip);
	518	set_irq_handler(irq, do_level_IRQ);
	519	set_irq_flags(irq, IRQF_VALID);
	520	}
	521	}
	522