[mirror_ubuntu-artful-kernel.git] / arch / arm / mach-ixp2000 / core.c

/*
 * arch/arm/mach-ixp2000/common.c
 *
 * Common routines used by all IXP2400/2800 based platforms.
 *
 * Author: Deepak Saxena <dsaxena@plexity.net>
 *
 * Copyright 2004 (C) MontaVista Software, Inc. 
 *
 * Based on work Copyright (C) 2002-2003 Intel Corporation
 * 
 * This file is licensed under the terms of the GNU General Public
 * License version 2. This program is licensed "as is" without any 
 * warranty of any kind, whether express or implied.
 */

#include <linux/config.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/spinlock.h>
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/serial.h>
#include <linux/tty.h>
#include <linux/bitops.h>
#include <linux/serial_core.h>
#include <linux/mm.h>

#include <asm/types.h>
#include <asm/setup.h>
#include <asm/memory.h>
#include <asm/hardware.h>
#include <asm/mach-types.h>
#include <asm/irq.h>
#include <asm/system.h>
#include <asm/tlbflush.h>
#include <asm/pgtable.h>

#include <asm/mach/map.h>
#include <asm/mach/time.h>
#include <asm/mach/irq.h>

static DEFINE_SPINLOCK(ixp2000_slowport_lock);
static unsigned long ixp2000_slowport_irq_flags;

/*************************************************************************
 * Slowport access routines
 *************************************************************************/
void ixp2000_acquire_slowport(struct slowport_cfg *new_cfg, struct slowport_cfg *old_cfg)
{

	spin_lock_irqsave(&ixp2000_slowport_lock, ixp2000_slowport_irq_flags);

	old_cfg->CCR = *IXP2000_SLOWPORT_CCR;
	old_cfg->WTC = *IXP2000_SLOWPORT_WTC2;
	old_cfg->RTC = *IXP2000_SLOWPORT_RTC2;
	old_cfg->PCR = *IXP2000_SLOWPORT_PCR;
	old_cfg->ADC = *IXP2000_SLOWPORT_ADC;

	ixp2000_reg_write(IXP2000_SLOWPORT_CCR, new_cfg->CCR);
	ixp2000_reg_write(IXP2000_SLOWPORT_WTC2, new_cfg->WTC);
	ixp2000_reg_write(IXP2000_SLOWPORT_RTC2, new_cfg->RTC);
	ixp2000_reg_write(IXP2000_SLOWPORT_PCR, new_cfg->PCR);
	ixp2000_reg_write(IXP2000_SLOWPORT_ADC, new_cfg->ADC);
}

void ixp2000_release_slowport(struct slowport_cfg *old_cfg)
{
	ixp2000_reg_write(IXP2000_SLOWPORT_CCR, old_cfg->CCR);
	ixp2000_reg_write(IXP2000_SLOWPORT_WTC2, old_cfg->WTC);
	ixp2000_reg_write(IXP2000_SLOWPORT_RTC2, old_cfg->RTC);
	ixp2000_reg_write(IXP2000_SLOWPORT_PCR, old_cfg->PCR);
	ixp2000_reg_write(IXP2000_SLOWPORT_ADC, old_cfg->ADC);

	spin_unlock_irqrestore(&ixp2000_slowport_lock, 
					ixp2000_slowport_irq_flags);
}

/*************************************************************************
 * Chip specific mappings shared by all IXP2000 systems
 *************************************************************************/
static struct map_desc ixp2000_io_desc[] __initdata = {
	{
		.virtual	= IXP2000_CAP_VIRT_BASE,
		.physical	= IXP2000_CAP_PHYS_BASE,
		.length		= IXP2000_CAP_SIZE,
		.type		= MT_DEVICE
	}, {
		.virtual	= IXP2000_INTCTL_VIRT_BASE,
		.physical	= IXP2000_INTCTL_PHYS_BASE,
		.length		= IXP2000_INTCTL_SIZE,
		.type		= MT_DEVICE
	}, {
		.virtual	= IXP2000_PCI_CREG_VIRT_BASE,
		.physical	= IXP2000_PCI_CREG_PHYS_BASE,
		.length		= IXP2000_PCI_CREG_SIZE,
		.type		= MT_DEVICE
	}, {
		.virtual	= IXP2000_PCI_CSR_VIRT_BASE,
		.physical	= IXP2000_PCI_CSR_PHYS_BASE,
		.length		= IXP2000_PCI_CSR_SIZE,
		.type		= MT_DEVICE
	}, {
		.virtual	= IXP2000_PCI_IO_VIRT_BASE,
		.physical	= IXP2000_PCI_IO_PHYS_BASE,
		.length		= IXP2000_PCI_IO_SIZE,
		.type		= MT_DEVICE
	}, {
		.virtual	= IXP2000_PCI_CFG0_VIRT_BASE,
		.physical	= IXP2000_PCI_CFG0_PHYS_BASE,
		.length		= IXP2000_PCI_CFG0_SIZE,
		.type		= MT_DEVICE
	}, {
		.virtual	= IXP2000_PCI_CFG1_VIRT_BASE,
		.physical	= IXP2000_PCI_CFG1_PHYS_BASE,
		.length		= IXP2000_PCI_CFG1_SIZE,
		.type		= MT_DEVICE
	}
};

static struct uart_port ixp2000_serial_port = {
	.membase	= (char *)(IXP2000_UART_VIRT_BASE + 3),
	.mapbase	= IXP2000_UART_PHYS_BASE + 3,
	.irq		= IRQ_IXP2000_UART,
	.flags		= UPF_SKIP_TEST,
	.iotype		= UPIO_MEM,
	.regshift	= 2,
	.uartclk	= 50000000,
	.line		= 0,
	.type		= PORT_XSCALE,
	.fifosize	= 16
};

void __init ixp2000_map_io(void)
{
	extern unsigned int processor_id;

	/*
	 * On IXP2400 CPUs we need to use MT_IXP2000_DEVICE for
	 * tweaking the PMDs so XCB=101. On IXP2800s we use the normal
	 * PMD flags.
	 */
	if ((processor_id & 0xfffffff0) == 0x69054190) {
		int i;

		printk(KERN_INFO "Enabling IXP2400 erratum #66 workaround\n");

		for(i=0;i<ARRAY_SIZE(ixp2000_io_desc);i++)
			ixp2000_io_desc[i].type = MT_IXP2000_DEVICE;
	}

	iotable_init(ixp2000_io_desc, ARRAY_SIZE(ixp2000_io_desc));
	early_serial_setup(&ixp2000_serial_port);

	/* Set slowport to 8-bit mode.  */
	ixp2000_reg_write(IXP2000_SLOWPORT_FRM, 1);
}

/*************************************************************************
 * Timer-tick functions for IXP2000
 *************************************************************************/
static unsigned ticks_per_jiffy;
static unsigned ticks_per_usec;
static unsigned next_jiffy_time;
static volatile unsigned long *missing_jiffy_timer_csr;

unsigned long ixp2000_gettimeoffset (void)
{
 	unsigned long offset;

	offset = next_jiffy_time - *missing_jiffy_timer_csr;

	return offset / ticks_per_usec;
}

static int ixp2000_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
{
	write_seqlock(&xtime_lock);

	/* clear timer 1 */
	ixp2000_reg_write(IXP2000_T1_CLR, 1);
	
	while ((next_jiffy_time - *missing_jiffy_timer_csr) > ticks_per_jiffy) {
		timer_tick(regs);
		next_jiffy_time -= ticks_per_jiffy;
	}

	write_sequnlock(&xtime_lock);

	return IRQ_HANDLED;
}

static struct irqaction ixp2000_timer_irq = {
	.name		= "IXP2000 Timer Tick",
	.flags		= SA_INTERRUPT,
	.handler	= ixp2000_timer_interrupt
};

void __init ixp2000_init_time(unsigned long tick_rate)
{
	ticks_per_jiffy = (tick_rate + HZ/2) / HZ;
	ticks_per_usec = tick_rate / 1000000;

	/*
	 * We use timer 1 as our timer interrupt.
	 */
	ixp2000_reg_write(IXP2000_T1_CLR, 0);
	ixp2000_reg_write(IXP2000_T1_CLD, ticks_per_jiffy - 1);
	ixp2000_reg_write(IXP2000_T1_CTL, (1 << 7));

	/*
	 * We use a second timer as a monotonic counter for tracking
	 * missed jiffies.  The IXP2000 has four timers, but if we're
	 * on an A-step IXP2800, timer 2 and 3 don't work, so on those
	 * chips we use timer 4.  Timer 4 is the only timer that can
	 * be used for the watchdog, so we use timer 2 if we're on a
	 * non-buggy chip.
	 */
	if ((*IXP2000_PRODUCT_ID & 0x001ffef0) == 0x00000000) {
		printk(KERN_INFO "Enabling IXP2800 erratum #25 workaround\n");

		ixp2000_reg_write(IXP2000_T4_CLR, 0);
		ixp2000_reg_write(IXP2000_T4_CLD, -1);
		ixp2000_reg_write(IXP2000_T4_CTL, (1 << 7));
		missing_jiffy_timer_csr = IXP2000_T4_CSR;
	} else {
		ixp2000_reg_write(IXP2000_T2_CLR, 0);
		ixp2000_reg_write(IXP2000_T2_CLD, -1);
		ixp2000_reg_write(IXP2000_T2_CTL, (1 << 7));
		missing_jiffy_timer_csr = IXP2000_T2_CSR;
	}
 	next_jiffy_time = 0xffffffff;

	/* register for interrupt */
	setup_irq(IRQ_IXP2000_TIMER1, &ixp2000_timer_irq);
}

/*************************************************************************
 * GPIO helpers
 *************************************************************************/
static unsigned long GPIO_IRQ_rising_edge;
static unsigned long GPIO_IRQ_falling_edge;
static unsigned long GPIO_IRQ_level_low;
static unsigned long GPIO_IRQ_level_high;

void gpio_line_config(int line, int style)
{
	unsigned long flags;

	local_irq_save(flags);

	if(style == GPIO_OUT) {
		/* if it's an output, it ain't an interrupt anymore */
		ixp2000_reg_write(IXP2000_GPIO_PDSR, (1 << line));
		GPIO_IRQ_falling_edge &= ~(1 << line);
		GPIO_IRQ_rising_edge &= ~(1 << line);
		GPIO_IRQ_level_low &= ~(1 << line);
		GPIO_IRQ_level_high &= ~(1 << line);
		ixp2000_reg_write(IXP2000_GPIO_FEDR, GPIO_IRQ_falling_edge);
		ixp2000_reg_write(IXP2000_GPIO_REDR, GPIO_IRQ_rising_edge);
		ixp2000_reg_write(IXP2000_GPIO_LSHR, GPIO_IRQ_level_high);
		ixp2000_reg_write(IXP2000_GPIO_LSLR, GPIO_IRQ_level_low);
		irq_desc[line+IRQ_IXP2000_GPIO0].valid = 0;
	} else if(style == GPIO_IN) {
		ixp2000_reg_write(IXP2000_GPIO_PDCR, (1 << line));
	}
		
	local_irq_restore(flags);
}	


/*************************************************************************
 * IRQ handling IXP2000
 *************************************************************************/
static void ixp2000_GPIO_irq_handler(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
{                               
	int i;
	unsigned long status = *IXP2000_GPIO_INST;
		   
	for (i = 0; i <= 7; i++) {
		if (status & (1<<i)) {
			desc = irq_desc + i + IRQ_IXP2000_GPIO0;
			desc->handle(i + IRQ_IXP2000_GPIO0, desc, regs);
		}
	}
}

static void ixp2000_GPIO_irq_mask_ack(unsigned int irq)
{
	ixp2000_reg_write(IXP2000_GPIO_INCR, (1 << (irq - IRQ_IXP2000_GPIO0)));
	ixp2000_reg_write(IXP2000_GPIO_INST, (1 << (irq - IRQ_IXP2000_GPIO0)));
}

static void ixp2000_GPIO_irq_mask(unsigned int irq)
{
	ixp2000_reg_write(IXP2000_GPIO_INCR, (1 << (irq - IRQ_IXP2000_GPIO0)));
}

static void ixp2000_GPIO_irq_unmask(unsigned int irq)
{
	ixp2000_reg_write(IXP2000_GPIO_INSR, (1 << (irq - IRQ_IXP2000_GPIO0)));
}

static struct irqchip ixp2000_GPIO_irq_chip = {
	.ack	= ixp2000_GPIO_irq_mask_ack,
	.mask	= ixp2000_GPIO_irq_mask,
	.unmask	= ixp2000_GPIO_irq_unmask
};

static void ixp2000_pci_irq_mask(unsigned int irq)
{
	unsigned long temp = *IXP2000_PCI_XSCALE_INT_ENABLE;
	if (irq == IRQ_IXP2000_PCIA)
		ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp & ~(1 << 26)));
	else if (irq == IRQ_IXP2000_PCIB)
		ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp & ~(1 << 27)));
}

static void ixp2000_pci_irq_unmask(unsigned int irq)
{
	unsigned long temp = *IXP2000_PCI_XSCALE_INT_ENABLE;
	if (irq == IRQ_IXP2000_PCIA)
		ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp | (1 << 26)));
	else if (irq == IRQ_IXP2000_PCIB)
		ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp | (1 << 27)));
}

static struct irqchip ixp2000_pci_irq_chip = {
	.ack	= ixp2000_pci_irq_mask,
	.mask	= ixp2000_pci_irq_mask,
	.unmask	= ixp2000_pci_irq_unmask
};

static void ixp2000_irq_mask(unsigned int irq)
{
	ixp2000_reg_write(IXP2000_IRQ_ENABLE_CLR, (1 << irq));
}

static void ixp2000_irq_unmask(unsigned int irq)
{
	ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET,  (1 << irq));
}

static struct irqchip ixp2000_irq_chip = {
	.ack	= ixp2000_irq_mask,
	.mask	= ixp2000_irq_mask,
	.unmask	= ixp2000_irq_unmask
};

void __init ixp2000_init_irq(void)
{
	int irq;

	/*
	 * Mask all sources
	 */
	ixp2000_reg_write(IXP2000_IRQ_ENABLE_CLR, 0xffffffff);
	ixp2000_reg_write(IXP2000_FIQ_ENABLE_CLR, 0xffffffff);

	/* clear all GPIO edge/level detects */
	ixp2000_reg_write(IXP2000_GPIO_REDR, 0);
	ixp2000_reg_write(IXP2000_GPIO_FEDR, 0);
	ixp2000_reg_write(IXP2000_GPIO_LSHR, 0);
	ixp2000_reg_write(IXP2000_GPIO_LSLR, 0);
	ixp2000_reg_write(IXP2000_GPIO_INCR, -1);

	/* clear PCI interrupt sources */
	ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, 0);

	/*
	 * Certain bits in the IRQ status register of the 
	 * IXP2000 are reserved. Instead of trying to map
	 * things non 1:1 from bit position to IRQ number,
	 * we mark the reserved IRQs as invalid. This makes
	 * our mask/unmask code much simpler.
	 */
	for (irq = IRQ_IXP2000_SOFT_INT; irq <= IRQ_IXP2000_THDB3; irq++) {
		if((1 << irq) & IXP2000_VALID_IRQ_MASK) {
			set_irq_chip(irq, &ixp2000_irq_chip);
			set_irq_handler(irq, do_level_IRQ);
			set_irq_flags(irq, IRQF_VALID);
		} else set_irq_flags(irq, 0);
	}
	
	/*
	 * GPIO IRQs are invalid until someone sets the interrupt mode
	 * by calling gpio_line_set();
	 */
	for (irq = IRQ_IXP2000_GPIO0; irq <= IRQ_IXP2000_GPIO7; irq++) {
		set_irq_chip(irq, &ixp2000_GPIO_irq_chip);
		set_irq_handler(irq, do_level_IRQ);
		set_irq_flags(irq, 0);
	}
	set_irq_chained_handler(IRQ_IXP2000_GPIO, ixp2000_GPIO_irq_handler);

	/*
	 * Enable PCI irqs.  The actual PCI[AB] decoding is done in
	 * entry-macro.S, so we don't need a chained handler for the
	 * PCI interrupt source.
	 */
	ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << IRQ_IXP2000_PCI));
	for (irq = IRQ_IXP2000_PCIA; irq <= IRQ_IXP2000_PCIB; irq++) {
		set_irq_chip(irq, &ixp2000_pci_irq_chip);
		set_irq_handler(irq, do_level_IRQ);
		set_irq_flags(irq, IRQF_VALID);
	}
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* arch/arm/mach-ixp2000/common.c
	3	*
	4	* Common routines used by all IXP2400/2800 based platforms.
	5	*
	6	* Author: Deepak Saxena <dsaxena@plexity.net>
	7	*
	8	* Copyright 2004 (C) MontaVista Software, Inc.
	9	*
	10	* Based on work Copyright (C) 2002-2003 Intel Corporation
	11	*
	12	* This file is licensed under the terms of the GNU General Public
	13	* License version 2. This program is licensed "as is" without any
	14	* warranty of any kind, whether express or implied.
	15	*/
	16
	17	#include <linux/config.h>
	18	#include <linux/kernel.h>
	19	#include <linux/init.h>
	20	#include <linux/spinlock.h>
	21	#include <linux/sched.h>
	22	#include <linux/interrupt.h>
	23	#include <linux/serial.h>
	24	#include <linux/tty.h>
	25	#include <linux/bitops.h>
	26	#include <linux/serial_core.h>
	27	#include <linux/mm.h>
	28
	29	#include <asm/types.h>
	30	#include <asm/setup.h>
	31	#include <asm/memory.h>
	32	#include <asm/hardware.h>
	33	#include <asm/mach-types.h>
	34	#include <asm/irq.h>
	35	#include <asm/system.h>
	36	#include <asm/tlbflush.h>
	37	#include <asm/pgtable.h>
	38
	39	#include <asm/mach/map.h>
	40	#include <asm/mach/time.h>
	41	#include <asm/mach/irq.h>
	42
	43	static DEFINE_SPINLOCK(ixp2000_slowport_lock);
	44	static unsigned long ixp2000_slowport_irq_flags;
	45
	46	/*************************************************************************
	47	* Slowport access routines
	48	*************************************************************************/
	49	void ixp2000_acquire_slowport(struct slowport_cfg new_cfg, struct slowport_cfg old_cfg)
	50	{
	51
	52	spin_lock_irqsave(&ixp2000_slowport_lock, ixp2000_slowport_irq_flags);
	53
	54	old_cfg->CCR = *IXP2000_SLOWPORT_CCR;
	55	old_cfg->WTC = *IXP2000_SLOWPORT_WTC2;
	56	old_cfg->RTC = *IXP2000_SLOWPORT_RTC2;
	57	old_cfg->PCR = *IXP2000_SLOWPORT_PCR;
	58	old_cfg->ADC = *IXP2000_SLOWPORT_ADC;
	59
	60	ixp2000_reg_write(IXP2000_SLOWPORT_CCR, new_cfg->CCR);
	61	ixp2000_reg_write(IXP2000_SLOWPORT_WTC2, new_cfg->WTC);
	62	ixp2000_reg_write(IXP2000_SLOWPORT_RTC2, new_cfg->RTC);
	63	ixp2000_reg_write(IXP2000_SLOWPORT_PCR, new_cfg->PCR);
	64	ixp2000_reg_write(IXP2000_SLOWPORT_ADC, new_cfg->ADC);
65	}
66
67	void ixp2000_release_slowport(struct slowport_cfg *old_cfg)
68	{
69	ixp2000_reg_write(IXP2000_SLOWPORT_CCR, old_cfg->CCR);
70	ixp2000_reg_write(IXP2000_SLOWPORT_WTC2, old_cfg->WTC);
71	ixp2000_reg_write(IXP2000_SLOWPORT_RTC2, old_cfg->RTC);
72	ixp2000_reg_write(IXP2000_SLOWPORT_PCR, old_cfg->PCR);
73	ixp2000_reg_write(IXP2000_SLOWPORT_ADC, old_cfg->ADC);
74
75	spin_unlock_irqrestore(&ixp2000_slowport_lock,
76	ixp2000_slowport_irq_flags);
77	}
78
79	/*************************************************************************
80	* Chip specific mappings shared by all IXP2000 systems
81	*************************************************************************/
82	static struct map_desc ixp2000_io_desc[] __initdata = {
83	{
84	.virtual = IXP2000_CAP_VIRT_BASE,
85	.physical = IXP2000_CAP_PHYS_BASE,
86	.length = IXP2000_CAP_SIZE,
87	.type = MT_DEVICE
88	}, {
89	.virtual = IXP2000_INTCTL_VIRT_BASE,
90	.physical = IXP2000_INTCTL_PHYS_BASE,
91	.length = IXP2000_INTCTL_SIZE,
92	.type = MT_DEVICE
93	}, {
94	.virtual = IXP2000_PCI_CREG_VIRT_BASE,
95	.physical = IXP2000_PCI_CREG_PHYS_BASE,
96	.length = IXP2000_PCI_CREG_SIZE,
97	.type = MT_DEVICE
98	}, {
99	.virtual = IXP2000_PCI_CSR_VIRT_BASE,
100	.physical = IXP2000_PCI_CSR_PHYS_BASE,
101	.length = IXP2000_PCI_CSR_SIZE,
102	.type = MT_DEVICE
103	}, {
104	.virtual = IXP2000_PCI_IO_VIRT_BASE,
105	.physical = IXP2000_PCI_IO_PHYS_BASE,
106	.length = IXP2000_PCI_IO_SIZE,
107	.type = MT_DEVICE
108	}, {
109	.virtual = IXP2000_PCI_CFG0_VIRT_BASE,
110	.physical = IXP2000_PCI_CFG0_PHYS_BASE,
111	.length = IXP2000_PCI_CFG0_SIZE,
112	.type = MT_DEVICE
113	}, {
114	.virtual = IXP2000_PCI_CFG1_VIRT_BASE,
115	.physical = IXP2000_PCI_CFG1_PHYS_BASE,
116	.length = IXP2000_PCI_CFG1_SIZE,
117	.type = MT_DEVICE
118	}
119	};
120
121	static struct uart_port ixp2000_serial_port = {
122	.membase = (char *)(IXP2000_UART_VIRT_BASE + 3),
123	.mapbase = IXP2000_UART_PHYS_BASE + 3,
124	.irq = IRQ_IXP2000_UART,
125	.flags = UPF_SKIP_TEST,
126	.iotype = UPIO_MEM,
127	.regshift = 2,
128	.uartclk = 50000000,
129	.line = 0,
130	.type = PORT_XSCALE,
131	.fifosize = 16
132	};
133
134	void __init ixp2000_map_io(void)
135	{
136	extern unsigned int processor_id;
137
138	/*
139	* On IXP2400 CPUs we need to use MT_IXP2000_DEVICE for
140	* tweaking the PMDs so XCB=101. On IXP2800s we use the normal
141	* PMD flags.
142	*/
143	if ((processor_id & 0xfffffff0) == 0x69054190) {
144	int i;
145
146	printk(KERN_INFO "Enabling IXP2400 erratum #66 workaround\n");
147
148	for(i=0;i<ARRAY_SIZE(ixp2000_io_desc);i++)
149	ixp2000_io_desc[i].type = MT_IXP2000_DEVICE;
150	}
151
152	iotable_init(ixp2000_io_desc, ARRAY_SIZE(ixp2000_io_desc));
153	early_serial_setup(&ixp2000_serial_port);
154
155	/* Set slowport to 8-bit mode. */
156	ixp2000_reg_write(IXP2000_SLOWPORT_FRM, 1);
157	}
158
159	/*************************************************************************
160	* Timer-tick functions for IXP2000
161	*************************************************************************/
162	static unsigned ticks_per_jiffy;
163	static unsigned ticks_per_usec;
164	static unsigned next_jiffy_time;
e4fe1981	165	static volatile unsigned long *missing_jiffy_timer_csr;
1da177e4 LT	166
	167	unsigned long ixp2000_gettimeoffset (void)
	168	{
	169	unsigned long offset;
	170
e4fe1981	171	offset = next_jiffy_time - *missing_jiffy_timer_csr;
1da177e4 LT	172
	173	return offset / ticks_per_usec;
	174	}
	175
	176	static int ixp2000_timer_interrupt(int irq, void dev_id, struct pt_regs regs)
	177	{
	178	write_seqlock(&xtime_lock);
	179
	180	/* clear timer 1 */
	181	ixp2000_reg_write(IXP2000_T1_CLR, 1);
	182
e4fe1981	183	while ((next_jiffy_time - *missing_jiffy_timer_csr) > ticks_per_jiffy) {
1da177e4 LT	184	timer_tick(regs);
	185	next_jiffy_time -= ticks_per_jiffy;
	186	}
	187
	188	write_sequnlock(&xtime_lock);
	189
	190	return IRQ_HANDLED;
	191	}
	192
	193	static struct irqaction ixp2000_timer_irq = {
	194	.name = "IXP2000 Timer Tick",
	195	.flags = SA_INTERRUPT,
	196	.handler = ixp2000_timer_interrupt
	197	};
	198
	199	void __init ixp2000_init_time(unsigned long tick_rate)
	200	{
1da177e4 LT	201	ticks_per_jiffy = (tick_rate + HZ/2) / HZ;
	202	ticks_per_usec = tick_rate / 1000000;
	203
e4fe1981 LB	204	/*
	205	* We use timer 1 as our timer interrupt.
	206	*/
	207	ixp2000_reg_write(IXP2000_T1_CLR, 0);
1da177e4 LT	208	ixp2000_reg_write(IXP2000_T1_CLD, ticks_per_jiffy - 1);
	209	ixp2000_reg_write(IXP2000_T1_CTL, (1 << 7));
	210
	211	/*
e4fe1981 LB	212	* We use a second timer as a monotonic counter for tracking
	213	* missed jiffies. The IXP2000 has four timers, but if we're
	214	* on an A-step IXP2800, timer 2 and 3 don't work, so on those
	215	* chips we use timer 4. Timer 4 is the only timer that can
	216	* be used for the watchdog, so we use timer 2 if we're on a
	217	* non-buggy chip.
1da177e4	218	*/
e4fe1981 LB	219	if ((*IXP2000_PRODUCT_ID & 0x001ffef0) == 0x00000000) {
	220	printk(KERN_INFO "Enabling IXP2800 erratum #25 workaround\n");
	221
	222	ixp2000_reg_write(IXP2000_T4_CLR, 0);
	223	ixp2000_reg_write(IXP2000_T4_CLD, -1);
	224	ixp2000_reg_write(IXP2000_T4_CTL, (1 << 7));
	225	missing_jiffy_timer_csr = IXP2000_T4_CSR;
	226	} else {
	227	ixp2000_reg_write(IXP2000_T2_CLR, 0);
	228	ixp2000_reg_write(IXP2000_T2_CLD, -1);
	229	ixp2000_reg_write(IXP2000_T2_CTL, (1 << 7));
	230	missing_jiffy_timer_csr = IXP2000_T2_CSR;
	231	}
1da177e4 LT	232	next_jiffy_time = 0xffffffff;
	233
	234	/* register for interrupt */
	235	setup_irq(IRQ_IXP2000_TIMER1, &ixp2000_timer_irq);
	236	}
	237
	238	/*************************************************************************
	239	* GPIO helpers
	240	*************************************************************************/
	241	static unsigned long GPIO_IRQ_rising_edge;
	242	static unsigned long GPIO_IRQ_falling_edge;
	243	static unsigned long GPIO_IRQ_level_low;
	244	static unsigned long GPIO_IRQ_level_high;
	245
	246	void gpio_line_config(int line, int style)
	247	{
	248	unsigned long flags;
	249
	250	local_irq_save(flags);
	251
	252	if(style == GPIO_OUT) {
	253	/* if it's an output, it ain't an interrupt anymore */
	254	ixp2000_reg_write(IXP2000_GPIO_PDSR, (1 << line));
	255	GPIO_IRQ_falling_edge &= ~(1 << line);
	256	GPIO_IRQ_rising_edge &= ~(1 << line);
	257	GPIO_IRQ_level_low &= ~(1 << line);
	258	GPIO_IRQ_level_high &= ~(1 << line);
	259	ixp2000_reg_write(IXP2000_GPIO_FEDR, GPIO_IRQ_falling_edge);
	260	ixp2000_reg_write(IXP2000_GPIO_REDR, GPIO_IRQ_rising_edge);
	261	ixp2000_reg_write(IXP2000_GPIO_LSHR, GPIO_IRQ_level_high);
	262	ixp2000_reg_write(IXP2000_GPIO_LSLR, GPIO_IRQ_level_low);
	263	irq_desc[line+IRQ_IXP2000_GPIO0].valid = 0;
	264	} else if(style == GPIO_IN) {
	265	ixp2000_reg_write(IXP2000_GPIO_PDCR, (1 << line));
	266	}
	267
	268	local_irq_restore(flags);
	269	}
	270
	271
	272	/*************************************************************************
	273	* IRQ handling IXP2000
	274	*************************************************************************/
	275	static void ixp2000_GPIO_irq_handler(unsigned int irq, struct irqdesc desc, struct pt_regs regs)
	276	{
	277	int i;
	278	unsigned long status = *IXP2000_GPIO_INST;
	279
	280	for (i = 0; i <= 7; i++) {
	281	if (status & (1<<i)) {
	282	desc = irq_desc + i + IRQ_IXP2000_GPIO0;
	283	desc->handle(i + IRQ_IXP2000_GPIO0, desc, regs);
	284	}
	285	}
	286	}
	287
	288	static void ixp2000_GPIO_irq_mask_ack(unsigned int irq)
	289	{
	290	ixp2000_reg_write(IXP2000_GPIO_INCR, (1 << (irq - IRQ_IXP2000_GPIO0)));
	291	ixp2000_reg_write(IXP2000_GPIO_INST, (1 << (irq - IRQ_IXP2000_GPIO0)));
	292	}
	293
	294	static void ixp2000_GPIO_irq_mask(unsigned int irq)
	295	{
296	ixp2000_reg_write(IXP2000_GPIO_INCR, (1 << (irq - IRQ_IXP2000_GPIO0)));
297	}
298
299	static void ixp2000_GPIO_irq_unmask(unsigned int irq)
300	{
301	ixp2000_reg_write(IXP2000_GPIO_INSR, (1 << (irq - IRQ_IXP2000_GPIO0)));
302	}
303
304	static struct irqchip ixp2000_GPIO_irq_chip = {
305	.ack = ixp2000_GPIO_irq_mask_ack,
306	.mask = ixp2000_GPIO_irq_mask,
307	.unmask = ixp2000_GPIO_irq_unmask
308	};
309
310	static void ixp2000_pci_irq_mask(unsigned int irq)
311	{
312	unsigned long temp = *IXP2000_PCI_XSCALE_INT_ENABLE;
313	if (irq == IRQ_IXP2000_PCIA)
314	ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp & ~(1 << 26)));
315	else if (irq == IRQ_IXP2000_PCIB)
316	ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp & ~(1 << 27)));
317	}
318
319	static void ixp2000_pci_irq_unmask(unsigned int irq)
320	{
321	unsigned long temp = *IXP2000_PCI_XSCALE_INT_ENABLE;
322	if (irq == IRQ_IXP2000_PCIA)
323	ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp \| (1 << 26)));
324	else if (irq == IRQ_IXP2000_PCIB)
325	ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp \| (1 << 27)));
326	}
327
328	static struct irqchip ixp2000_pci_irq_chip = {
329	.ack = ixp2000_pci_irq_mask,
330	.mask = ixp2000_pci_irq_mask,
331	.unmask = ixp2000_pci_irq_unmask
332	};
333
334	static void ixp2000_irq_mask(unsigned int irq)
335	{
336	ixp2000_reg_write(IXP2000_IRQ_ENABLE_CLR, (1 << irq));
337	}
338
339	static void ixp2000_irq_unmask(unsigned int irq)
340	{
341	ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << irq));
342	}
343
344	static struct irqchip ixp2000_irq_chip = {
345	.ack = ixp2000_irq_mask,
346	.mask = ixp2000_irq_mask,
347	.unmask = ixp2000_irq_unmask
348	};
349
350	void __init ixp2000_init_irq(void)
351	{
352	int irq;
353
354	/*
355	* Mask all sources
356	*/
357	ixp2000_reg_write(IXP2000_IRQ_ENABLE_CLR, 0xffffffff);
358	ixp2000_reg_write(IXP2000_FIQ_ENABLE_CLR, 0xffffffff);
359
360	/* clear all GPIO edge/level detects */
361	ixp2000_reg_write(IXP2000_GPIO_REDR, 0);
362	ixp2000_reg_write(IXP2000_GPIO_FEDR, 0);
363	ixp2000_reg_write(IXP2000_GPIO_LSHR, 0);
364	ixp2000_reg_write(IXP2000_GPIO_LSLR, 0);
365	ixp2000_reg_write(IXP2000_GPIO_INCR, -1);
366
367	/* clear PCI interrupt sources */
368	ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, 0);
369
370	/*
371	* Certain bits in the IRQ status register of the
372	* IXP2000 are reserved. Instead of trying to map
373	* things non 1:1 from bit position to IRQ number,
374	* we mark the reserved IRQs as invalid. This makes
375	* our mask/unmask code much simpler.
376	*/
377	for (irq = IRQ_IXP2000_SOFT_INT; irq <= IRQ_IXP2000_THDB3; irq++) {
378	if((1 << irq) & IXP2000_VALID_IRQ_MASK) {
379	set_irq_chip(irq, &ixp2000_irq_chip);
380	set_irq_handler(irq, do_level_IRQ);
381	set_irq_flags(irq, IRQF_VALID);
382	} else set_irq_flags(irq, 0);
383	}
384
385	/*
386	* GPIO IRQs are invalid until someone sets the interrupt mode
387	* by calling gpio_line_set();
388	*/
389	for (irq = IRQ_IXP2000_GPIO0; irq <= IRQ_IXP2000_GPIO7; irq++) {
390	set_irq_chip(irq, &ixp2000_GPIO_irq_chip);
391	set_irq_handler(irq, do_level_IRQ);
392	set_irq_flags(irq, 0);
393	}
394	set_irq_chained_handler(IRQ_IXP2000_GPIO, ixp2000_GPIO_irq_handler);
395
396	/*
397	* Enable PCI irqs. The actual PCI[AB] decoding is done in
398	* entry-macro.S, so we don't need a chained handler for the
399	* PCI interrupt source.
400	*/
401	ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << IRQ_IXP2000_PCI));
402	for (irq = IRQ_IXP2000_PCIA; irq <= IRQ_IXP2000_PCIB; irq++) {
403	set_irq_chip(irq, &ixp2000_pci_irq_chip);
404	set_irq_handler(irq, do_level_IRQ);
405	set_irq_flags(irq, IRQF_VALID);
406	}
407	}
408