]>
Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * arch/arm/mach-ixp2000/ixdp2800.c | |
3 | * | |
4 | * IXDP2800 platform support | |
5 | * | |
6 | * Original Author: Jeffrey Daly <jeffrey.daly@intel.com> | |
7 | * Maintainer: Deepak Saxena <dsaxena@plexity.net> | |
8 | * | |
9 | * Copyright (C) 2002 Intel Corp. | |
10 | * Copyright (C) 2003-2004 MontaVista Software, Inc. | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify it | |
13 | * under the terms of the GNU General Public License as published by the | |
14 | * Free Software Foundation; either version 2 of the License, or (at your | |
15 | * option) any later version. | |
16 | */ | |
1da177e4 LT |
17 | #include <linux/kernel.h> |
18 | #include <linux/init.h> | |
19 | #include <linux/mm.h> | |
20 | #include <linux/sched.h> | |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/device.h> | |
23 | #include <linux/bitops.h> | |
24 | #include <linux/pci.h> | |
25 | #include <linux/ioport.h> | |
26 | #include <linux/slab.h> | |
27 | #include <linux/delay.h> | |
fced80c7 | 28 | #include <linux/io.h> |
1da177e4 | 29 | |
1da177e4 LT |
30 | #include <asm/irq.h> |
31 | #include <asm/pgtable.h> | |
32 | #include <asm/page.h> | |
33 | #include <asm/system.h> | |
a09e64fb | 34 | #include <mach/hardware.h> |
1da177e4 LT |
35 | #include <asm/mach-types.h> |
36 | ||
37 | #include <asm/mach/pci.h> | |
38 | #include <asm/mach/map.h> | |
39 | #include <asm/mach/irq.h> | |
40 | #include <asm/mach/time.h> | |
41 | #include <asm/mach/flash.h> | |
42 | #include <asm/mach/arch.h> | |
43 | ||
1da177e4 LT |
44 | /************************************************************************* |
45 | * IXDP2800 timer tick | |
46 | *************************************************************************/ | |
47 | ||
48 | static void __init ixdp2800_timer_init(void) | |
49 | { | |
50 | ixp2000_init_time(50000000); | |
51 | } | |
52 | ||
53 | static struct sys_timer ixdp2800_timer = { | |
54 | .init = ixdp2800_timer_init, | |
55 | .offset = ixp2000_gettimeoffset, | |
56 | }; | |
57 | ||
58 | /************************************************************************* | |
59 | * IXDP2800 PCI | |
60 | *************************************************************************/ | |
53e173f6 LB |
61 | static void __init ixdp2800_slave_disable_pci_master(void) |
62 | { | |
63 | *IXP2000_PCI_CMDSTAT &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); | |
64 | } | |
65 | ||
66 | static void __init ixdp2800_master_wait_for_slave(void) | |
67 | { | |
68 | volatile u32 *addr; | |
69 | ||
70 | printk(KERN_INFO "IXDP2800: waiting for slave NPU to configure " | |
71 | "its BAR sizes\n"); | |
72 | ||
73 | addr = ixp2000_pci_config_addr(0, IXDP2X00_SLAVE_NPU_DEVFN, | |
74 | PCI_BASE_ADDRESS_1); | |
75 | do { | |
76 | *addr = 0xffffffff; | |
77 | cpu_relax(); | |
78 | } while (*addr != 0xfe000008); | |
79 | ||
80 | addr = ixp2000_pci_config_addr(0, IXDP2X00_SLAVE_NPU_DEVFN, | |
81 | PCI_BASE_ADDRESS_2); | |
82 | do { | |
83 | *addr = 0xffffffff; | |
84 | cpu_relax(); | |
85 | } while (*addr != 0xc0000008); | |
86 | ||
87 | /* | |
88 | * Configure the slave's SDRAM BAR by hand. | |
89 | */ | |
90 | *addr = 0x40000008; | |
91 | } | |
92 | ||
93 | static void __init ixdp2800_slave_wait_for_master_enable(void) | |
94 | { | |
95 | printk(KERN_INFO "IXDP2800: waiting for master NPU to enable us\n"); | |
96 | ||
97 | while ((*IXP2000_PCI_CMDSTAT & PCI_COMMAND_MASTER) == 0) | |
98 | cpu_relax(); | |
99 | } | |
100 | ||
1da177e4 LT |
101 | void __init ixdp2800_pci_preinit(void) |
102 | { | |
103 | printk("ixdp2x00_pci_preinit called\n"); | |
104 | ||
53e173f6 LB |
105 | *IXP2000_PCI_ADDR_EXT = 0x0001e000; |
106 | ||
107 | if (!ixdp2x00_master_npu()) | |
108 | ixdp2800_slave_disable_pci_master(); | |
1da177e4 | 109 | |
1da177e4 | 110 | *IXP2000_PCI_SRAM_BASE_ADDR_MASK = (0x2000000 - 1) & ~0x3ffff; |
53e173f6 | 111 | *IXP2000_PCI_DRAM_BASE_ADDR_MASK = (0x40000000 - 1) & ~0xfffff; |
1da177e4 LT |
112 | |
113 | ixp2000_pci_preinit(); | |
53e173f6 LB |
114 | |
115 | if (ixdp2x00_master_npu()) { | |
116 | /* | |
117 | * Wait until the slave set its SRAM/SDRAM BAR sizes | |
118 | * correctly before we proceed to scan and enumerate | |
119 | * the bus. | |
120 | */ | |
121 | ixdp2800_master_wait_for_slave(); | |
122 | ||
123 | /* | |
124 | * We configure the SDRAM BARs by hand because they | |
125 | * are 1G and fall outside of the regular allocated | |
126 | * PCI address space. | |
127 | */ | |
128 | *IXP2000_PCI_SDRAM_BAR = 0x00000008; | |
129 | } else { | |
130 | /* | |
131 | * Wait for the master to complete scanning the bus | |
132 | * and assigning resources before we proceed to scan | |
133 | * the bus ourselves. Set pci=firmware to honor the | |
134 | * master's resource assignment. | |
135 | */ | |
136 | ixdp2800_slave_wait_for_master_enable(); | |
137 | pcibios_setup("firmware"); | |
138 | } | |
1da177e4 LT |
139 | } |
140 | ||
53e173f6 LB |
141 | /* |
142 | * We assign the SDRAM BARs for the two IXP2800 CPUs by hand, outside | |
143 | * of the regular PCI window, because there's only 512M of outbound PCI | |
144 | * memory window on each IXP, while we need 1G for each of the BARs. | |
145 | */ | |
146 | static void __devinit ixp2800_pci_fixup(struct pci_dev *dev) | |
147 | { | |
148 | if (machine_is_ixdp2800()) { | |
149 | dev->resource[2].start = 0; | |
150 | dev->resource[2].end = 0; | |
151 | dev->resource[2].flags = 0; | |
152 | } | |
153 | } | |
154 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IXP2800, ixp2800_pci_fixup); | |
155 | ||
156 | static int __init ixdp2800_pci_setup(int nr, struct pci_sys_data *sys) | |
1da177e4 LT |
157 | { |
158 | sys->mem_offset = 0x00000000; | |
159 | ||
160 | ixp2000_pci_setup(nr, sys); | |
161 | ||
162 | return 1; | |
163 | } | |
164 | ||
165 | static int __init ixdp2800_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) | |
166 | { | |
167 | if (ixdp2x00_master_npu()) { | |
168 | ||
169 | /* | |
170 | * Root bus devices. Slave NPU is only one with interrupt. | |
171 | * Everything else, we just return -1 which is invalid. | |
172 | */ | |
173 | if(!dev->bus->self) { | |
174 | if(dev->devfn == IXDP2X00_SLAVE_NPU_DEVFN ) | |
175 | return IRQ_IXDP2800_INGRESS_NPU; | |
176 | ||
177 | return -1; | |
178 | } | |
179 | ||
180 | /* | |
181 | * Bridge behind the PMC slot. | |
182 | */ | |
183 | if(dev->bus->self->devfn == IXDP2X00_PMC_DEVFN && | |
184 | dev->bus->parent->self->devfn == IXDP2X00_P2P_DEVFN && | |
185 | !dev->bus->parent->self->bus->parent) | |
186 | return IRQ_IXDP2800_PMC; | |
187 | ||
188 | /* | |
189 | * Device behind the first bridge | |
190 | */ | |
191 | if(dev->bus->self->devfn == IXDP2X00_P2P_DEVFN) { | |
192 | switch(dev->devfn) { | |
193 | case IXDP2X00_PMC_DEVFN: | |
194 | return IRQ_IXDP2800_PMC; | |
195 | ||
196 | case IXDP2800_MASTER_ENET_DEVFN: | |
197 | return IRQ_IXDP2800_EGRESS_ENET; | |
198 | ||
199 | case IXDP2800_SWITCH_FABRIC_DEVFN: | |
200 | return IRQ_IXDP2800_FABRIC; | |
201 | } | |
202 | } | |
203 | ||
204 | return -1; | |
205 | } else return IRQ_IXP2000_PCIB; /* Slave NIC interrupt */ | |
206 | } | |
207 | ||
53e173f6 | 208 | static void __init ixdp2800_master_enable_slave(void) |
1da177e4 | 209 | { |
53e173f6 | 210 | volatile u32 *addr; |
1da177e4 | 211 | |
53e173f6 LB |
212 | printk(KERN_INFO "IXDP2800: enabling slave NPU\n"); |
213 | ||
214 | addr = (volatile u32 *)ixp2000_pci_config_addr(0, | |
215 | IXDP2X00_SLAVE_NPU_DEVFN, | |
216 | PCI_COMMAND); | |
217 | ||
218 | *addr |= PCI_COMMAND_MASTER; | |
219 | } | |
1da177e4 | 220 | |
53e173f6 LB |
221 | static void __init ixdp2800_master_wait_for_slave_bus_scan(void) |
222 | { | |
223 | volatile u32 *addr; | |
224 | ||
225 | printk(KERN_INFO "IXDP2800: waiting for slave to finish bus scan\n"); | |
226 | ||
227 | addr = (volatile u32 *)ixp2000_pci_config_addr(0, | |
228 | IXDP2X00_SLAVE_NPU_DEVFN, | |
229 | PCI_COMMAND); | |
230 | while ((*addr & PCI_COMMAND_MEMORY) == 0) | |
231 | cpu_relax(); | |
232 | } | |
233 | ||
234 | static void __init ixdp2800_slave_signal_bus_scan_completion(void) | |
235 | { | |
236 | printk(KERN_INFO "IXDP2800: bus scan done, signaling master\n"); | |
237 | *IXP2000_PCI_CMDSTAT |= PCI_COMMAND_MEMORY; | |
238 | } | |
239 | ||
240 | static void __init ixdp2800_pci_postinit(void) | |
241 | { | |
242 | if (!ixdp2x00_master_npu()) { | |
1da177e4 | 243 | ixdp2x00_slave_pci_postinit(); |
53e173f6 | 244 | ixdp2800_slave_signal_bus_scan_completion(); |
1da177e4 LT |
245 | } |
246 | } | |
247 | ||
53e173f6 | 248 | struct __initdata hw_pci ixdp2800_pci __initdata = { |
1da177e4 LT |
249 | .nr_controllers = 1, |
250 | .setup = ixdp2800_pci_setup, | |
251 | .preinit = ixdp2800_pci_preinit, | |
252 | .postinit = ixdp2800_pci_postinit, | |
253 | .scan = ixp2000_pci_scan_bus, | |
254 | .map_irq = ixdp2800_pci_map_irq, | |
255 | }; | |
256 | ||
257 | int __init ixdp2800_pci_init(void) | |
258 | { | |
53e173f6 LB |
259 | if (machine_is_ixdp2800()) { |
260 | struct pci_dev *dev; | |
261 | ||
1da177e4 | 262 | pci_common_init(&ixdp2800_pci); |
53e173f6 | 263 | if (ixdp2x00_master_npu()) { |
7281c248 | 264 | dev = pci_get_bus_and_slot(1, IXDP2800_SLAVE_ENET_DEVFN); |
53e173f6 | 265 | pci_remove_bus_device(dev); |
7281c248 | 266 | pci_dev_put(dev); |
53e173f6 LB |
267 | |
268 | ixdp2800_master_enable_slave(); | |
269 | ixdp2800_master_wait_for_slave_bus_scan(); | |
270 | } else { | |
7281c248 | 271 | dev = pci_get_bus_and_slot(1, IXDP2800_MASTER_ENET_DEVFN); |
53e173f6 | 272 | pci_remove_bus_device(dev); |
7281c248 | 273 | pci_dev_put(dev); |
53e173f6 LB |
274 | } |
275 | } | |
1da177e4 LT |
276 | |
277 | return 0; | |
278 | } | |
279 | ||
280 | subsys_initcall(ixdp2800_pci_init); | |
281 | ||
cdea4606 | 282 | void __init ixdp2800_init_irq(void) |
1da177e4 LT |
283 | { |
284 | ixdp2x00_init_irq(IXDP2800_CPLD_INT_STAT, IXDP2800_CPLD_INT_MASK, IXDP2800_NR_IRQS); | |
285 | } | |
286 | ||
287 | MACHINE_START(IXDP2800, "Intel IXDP2800 Development Platform") | |
e9dea0c6 | 288 | /* Maintainer: MontaVista Software, Inc. */ |
e9dea0c6 RK |
289 | .phys_io = IXP2000_UART_PHYS_BASE, |
290 | .io_pg_offst = ((IXP2000_UART_VIRT_BASE) >> 18) & 0xfffc, | |
291 | .boot_params = 0x00000100, | |
292 | .map_io = ixdp2x00_map_io, | |
293 | .init_irq = ixdp2800_init_irq, | |
1da177e4 | 294 | .timer = &ixdp2800_timer, |
e9dea0c6 | 295 | .init_machine = ixdp2x00_init_machine, |
1da177e4 LT |
296 | MACHINE_END |
297 |