[mirror_ubuntu-hirsute-kernel.git] / arch / arm / mach-ixp4xx / common-pci.c

/*
 * arch/arm/mach-ixp4xx/common-pci.c 
 *
 * IXP4XX PCI routines for all platforms
 *
 * Maintainer: Deepak Saxena <dsaxena@plexity.net>
 *
 * Copyright (C) 2002 Intel Corporation.
 * Copyright (C) 2003 Greg Ungerer <gerg@snapgear.com>
 * Copyright (C) 2003-2004 MontaVista Software, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 */

#include <linux/sched.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/interrupt.h>
#include <linux/mm.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/io.h>
#include <linux/export.h>
#include <asm/dma-mapping.h>

#include <asm/cputype.h>
#include <asm/irq.h>
#include <linux/sizes.h>
#include <asm/mach/pci.h>
#include <mach/hardware.h>


/*
 * IXP4xx PCI read function is dependent on whether we are 
 * running A0 or B0 (AppleGate) silicon.
 */
int (*ixp4xx_pci_read)(u32 addr, u32 cmd, u32* data);

/*
 * Base address for PCI register region
 */
unsigned long ixp4xx_pci_reg_base = 0;

/*
 * PCI cfg an I/O routines are done by programming a 
 * command/byte enable register, and then read/writing
 * the data from a data register. We need to ensure
 * these transactions are atomic or we will end up
 * with corrupt data on the bus or in a driver.
 */
static DEFINE_RAW_SPINLOCK(ixp4xx_pci_lock);

/*
 * Read from PCI config space
 */
static void crp_read(u32 ad_cbe, u32 *data)
{
	unsigned long flags;
	raw_spin_lock_irqsave(&ixp4xx_pci_lock, flags);
	*PCI_CRP_AD_CBE = ad_cbe;
	*data = *PCI_CRP_RDATA;
	raw_spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
}

/*
 * Write to PCI config space
 */
static void crp_write(u32 ad_cbe, u32 data)
{ 
	unsigned long flags;
	raw_spin_lock_irqsave(&ixp4xx_pci_lock, flags);
	*PCI_CRP_AD_CBE = CRP_AD_CBE_WRITE | ad_cbe;
	*PCI_CRP_WDATA = data;
	raw_spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
}

static inline int check_master_abort(void)
{
	/* check Master Abort bit after access */
	unsigned long isr = *PCI_ISR;

	if (isr & PCI_ISR_PFE) {
		/* make sure the Master Abort bit is reset */    
		*PCI_ISR = PCI_ISR_PFE;
		pr_debug("%s failed\n", __func__);
		return 1;
	}

	return 0;
}

int ixp4xx_pci_read_errata(u32 addr, u32 cmd, u32* data)
{
	unsigned long flags;
	int retval = 0;
	int i;

	raw_spin_lock_irqsave(&ixp4xx_pci_lock, flags);

	*PCI_NP_AD = addr;

	/* 
	 * PCI workaround  - only works if NP PCI space reads have 
	 * no side effects!!! Read 8 times. last one will be good.
	 */
	for (i = 0; i < 8; i++) {
		*PCI_NP_CBE = cmd;
		*data = *PCI_NP_RDATA;
		*data = *PCI_NP_RDATA;
	}

	if(check_master_abort())
		retval = 1;

	raw_spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
	return retval;
}

int ixp4xx_pci_read_no_errata(u32 addr, u32 cmd, u32* data)
{
	unsigned long flags;
	int retval = 0;

	raw_spin_lock_irqsave(&ixp4xx_pci_lock, flags);

	*PCI_NP_AD = addr;

	/* set up and execute the read */    
	*PCI_NP_CBE = cmd;

	/* the result of the read is now in NP_RDATA */
	*data = *PCI_NP_RDATA; 

	if(check_master_abort())
		retval = 1;

	raw_spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
	return retval;
}

int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data)
{    
	unsigned long flags;
	int retval = 0;

	raw_spin_lock_irqsave(&ixp4xx_pci_lock, flags);

	*PCI_NP_AD = addr;

	/* set up the write */
	*PCI_NP_CBE = cmd;

	/* execute the write by writing to NP_WDATA */
	*PCI_NP_WDATA = data;

	if(check_master_abort())
		retval = 1;

	raw_spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
	return retval;
}

static u32 ixp4xx_config_addr(u8 bus_num, u16 devfn, int where)
{
	u32 addr;
	if (!bus_num) {
		/* type 0 */
		addr = BIT(32-PCI_SLOT(devfn)) | ((PCI_FUNC(devfn)) << 8) | 
		    (where & ~3);	
	} else {
		/* type 1 */
		addr = (bus_num << 16) | ((PCI_SLOT(devfn)) << 11) | 
			((PCI_FUNC(devfn)) << 8) | (where & ~3) | 1;
	}
	return addr;
}

/*
 * Mask table, bits to mask for quantity of size 1, 2 or 4 bytes.
 * 0 and 3 are not valid indexes...
 */
static u32 bytemask[] = {
	/*0*/	0,
	/*1*/	0xff,
	/*2*/	0xffff,
	/*3*/	0,
	/*4*/	0xffffffff,
};

static u32 local_byte_lane_enable_bits(u32 n, int size)
{
	if (size == 1)
		return (0xf & ~BIT(n)) << CRP_AD_CBE_BESL;
	if (size == 2)
		return (0xf & ~(BIT(n) | BIT(n+1))) << CRP_AD_CBE_BESL;
	if (size == 4)
		return 0;
	return 0xffffffff;
}

static int local_read_config(int where, int size, u32 *value)
{ 
	u32 n, data;
	pr_debug("local_read_config from %d size %d\n", where, size);
	n = where % 4;
	crp_read(where & ~3, &data);
	*value = (data >> (8*n)) & bytemask[size];
	pr_debug("local_read_config read %#x\n", *value);
	return PCIBIOS_SUCCESSFUL;
}

static int local_write_config(int where, int size, u32 value)
{
	u32 n, byte_enables, data;
	pr_debug("local_write_config %#x to %d size %d\n", value, where, size);
	n = where % 4;
	byte_enables = local_byte_lane_enable_bits(n, size);
	if (byte_enables == 0xffffffff)
		return PCIBIOS_BAD_REGISTER_NUMBER;
	data = value << (8*n);
	crp_write((where & ~3) | byte_enables, data);
	return PCIBIOS_SUCCESSFUL;
}

static u32 byte_lane_enable_bits(u32 n, int size)
{
	if (size == 1)
		return (0xf & ~BIT(n)) << 4;
	if (size == 2)
		return (0xf & ~(BIT(n) | BIT(n+1))) << 4;
	if (size == 4)
		return 0;
	return 0xffffffff;
}

static int ixp4xx_pci_read_config(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value)
{
	u32 n, byte_enables, addr, data;
	u8 bus_num = bus->number;

	pr_debug("read_config from %d size %d dev %d:%d:%d\n", where, size,
		bus_num, PCI_SLOT(devfn), PCI_FUNC(devfn));

	*value = 0xffffffff;
	n = where % 4;
	byte_enables = byte_lane_enable_bits(n, size);
	if (byte_enables == 0xffffffff)
		return PCIBIOS_BAD_REGISTER_NUMBER;

	addr = ixp4xx_config_addr(bus_num, devfn, where);
	if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_CONFIGREAD, &data))
		return PCIBIOS_DEVICE_NOT_FOUND;

	*value = (data >> (8*n)) & bytemask[size];
	pr_debug("read_config_byte read %#x\n", *value);
	return PCIBIOS_SUCCESSFUL;
}

static int ixp4xx_pci_write_config(struct pci_bus *bus,  unsigned int devfn, int where, int size, u32 value)
{
	u32 n, byte_enables, addr, data;
	u8 bus_num = bus->number;

	pr_debug("write_config_byte %#x to %d size %d dev %d:%d:%d\n", value, where,
		size, bus_num, PCI_SLOT(devfn), PCI_FUNC(devfn));

	n = where % 4;
	byte_enables = byte_lane_enable_bits(n, size);
	if (byte_enables == 0xffffffff)
		return PCIBIOS_BAD_REGISTER_NUMBER;

	addr = ixp4xx_config_addr(bus_num, devfn, where);
	data = value << (8*n);
	if (ixp4xx_pci_write(addr, byte_enables | NP_CMD_CONFIGWRITE, data))
		return PCIBIOS_DEVICE_NOT_FOUND;

	return PCIBIOS_SUCCESSFUL;
}

struct pci_ops ixp4xx_ops = {
	.read =  ixp4xx_pci_read_config,
	.write = ixp4xx_pci_write_config,
};

/*
 * PCI abort handler
 */
static int abort_handler(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
{
	u32 isr, status;

	isr = *PCI_ISR;
	local_read_config(PCI_STATUS, 2, &status);
	pr_debug("PCI: abort_handler addr = %#lx, isr = %#x, "
		"status = %#x\n", addr, isr, status);

	/* make sure the Master Abort bit is reset */    
	*PCI_ISR = PCI_ISR_PFE;
	status |= PCI_STATUS_REC_MASTER_ABORT;
	local_write_config(PCI_STATUS, 2, status);

	/*
	 * If it was an imprecise abort, then we need to correct the
	 * return address to be _after_ the instruction.
	 */
	if (fsr & (1 << 10))
		regs->ARM_pc += 4;

	return 0;
}

void __init ixp4xx_pci_preinit(void)
{
	unsigned long cpuid = read_cpuid_id();

#ifdef CONFIG_IXP4XX_INDIRECT_PCI
	pcibios_min_mem = 0x10000000; /* 1 GB of indirect PCI MMIO space */
#else
	pcibios_min_mem = 0x48000000; /* 64 MB of PCI MMIO space */
#endif
	/*
	 * Determine which PCI read method to use.
	 * Rev 0 IXP425 requires workaround.
	 */
	if (!(cpuid & 0xf) && cpu_is_ixp42x()) {
		printk("PCI: IXP42x A0 silicon detected - "
			"PCI Non-Prefetch Workaround Enabled\n");
		ixp4xx_pci_read = ixp4xx_pci_read_errata;
	} else
		ixp4xx_pci_read = ixp4xx_pci_read_no_errata;


	/* hook in our fault handler for PCI errors */
	hook_fault_code(16+6, abort_handler, SIGBUS, 0,
			"imprecise external abort");

	pr_debug("setup PCI-AHB(inbound) and AHB-PCI(outbound) address mappings\n");

	/*
	 * We use identity AHB->PCI address translation
	 * in the 0x48000000 to 0x4bffffff address space
	 */
	*PCI_PCIMEMBASE = 0x48494A4B;

	/*
	 * We also use identity PCI->AHB address translation
	 * in 4 16MB BARs that begin at the physical memory start
	 */
	*PCI_AHBMEMBASE = (PHYS_OFFSET & 0xFF000000) +
		((PHYS_OFFSET & 0xFF000000) >> 8) +
		((PHYS_OFFSET & 0xFF000000) >> 16) +
		((PHYS_OFFSET & 0xFF000000) >> 24) +
		0x00010203;

	if (*PCI_CSR & PCI_CSR_HOST) {
		printk("PCI: IXP4xx is host\n");

		pr_debug("setup BARs in controller\n");

		/*
		 * We configure the PCI inbound memory windows to be
		 * 1:1 mapped to SDRAM
		 */
		local_write_config(PCI_BASE_ADDRESS_0, 4, PHYS_OFFSET);
		local_write_config(PCI_BASE_ADDRESS_1, 4, PHYS_OFFSET + SZ_16M);
		local_write_config(PCI_BASE_ADDRESS_2, 4, PHYS_OFFSET + SZ_32M);
		local_write_config(PCI_BASE_ADDRESS_3, 4,
					PHYS_OFFSET + SZ_32M + SZ_16M);

		/*
		 * Enable CSR window at 64 MiB to allow PCI masters
		 * to continue prefetching past 64 MiB boundary.
		 */
		local_write_config(PCI_BASE_ADDRESS_4, 4, PHYS_OFFSET + SZ_64M);

		/*
		 * Enable the IO window to be way up high, at 0xfffffc00
		 */
		local_write_config(PCI_BASE_ADDRESS_5, 4, 0xfffffc01);
		local_write_config(0x40, 4, 0x000080FF); /* No TRDY time limit */
	} else {
		printk("PCI: IXP4xx is target - No bus scan performed\n");
	}

	printk("PCI: IXP4xx Using %s access for memory space\n",
#ifndef CONFIG_IXP4XX_INDIRECT_PCI
			"direct"
#else
			"indirect"
#endif
		);

	pr_debug("clear error bits in ISR\n");
	*PCI_ISR = PCI_ISR_PSE | PCI_ISR_PFE | PCI_ISR_PPE | PCI_ISR_AHBE;

	/*
	 * Set Initialize Complete in PCI Control Register: allow IXP4XX to
	 * respond to PCI configuration cycles. Specify that the AHB bus is
	 * operating in big endian mode. Set up byte lane swapping between 
	 * little-endian PCI and the big-endian AHB bus 
	 */
#ifdef __ARMEB__
	*PCI_CSR = PCI_CSR_IC | PCI_CSR_ABE | PCI_CSR_PDS | PCI_CSR_ADS;
#else
	*PCI_CSR = PCI_CSR_IC | PCI_CSR_ABE;
#endif

	pr_debug("DONE\n");
}

int ixp4xx_setup(int nr, struct pci_sys_data *sys)
{
	struct resource *res;

	if (nr >= 1)
		return 0;

	res = kcalloc(2, sizeof(*res), GFP_KERNEL);
	if (res == NULL) {
		/* 
		 * If we're out of memory this early, something is wrong,
		 * so we might as well catch it here.
		 */
		panic("PCI: unable to allocate resources?\n");
	}

	local_write_config(PCI_COMMAND, 2, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);

	res[0].name = "PCI I/O Space";
	res[0].start = 0x00000000;
	res[0].end = 0x0000ffff;
	res[0].flags = IORESOURCE_IO;

	res[1].name = "PCI Memory Space";
	res[1].start = PCIBIOS_MIN_MEM;
	res[1].end = PCIBIOS_MAX_MEM;
	res[1].flags = IORESOURCE_MEM;

	request_resource(&ioport_resource, &res[0]);
	request_resource(&iomem_resource, &res[1]);

	pci_add_resource_offset(&sys->resources, &res[0], sys->io_offset);
	pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset);

	return 1;
}

EXPORT_SYMBOL(ixp4xx_pci_read);
EXPORT_SYMBOL(ixp4xx_pci_write);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* arch/arm/mach-ixp4xx/common-pci.c
	3	*
	4	* IXP4XX PCI routines for all platforms
	5	*
	6	* Maintainer: Deepak Saxena <dsaxena@plexity.net>
	7	*
	8	* Copyright (C) 2002 Intel Corporation.
	9	* Copyright (C) 2003 Greg Ungerer <gerg@snapgear.com>
	10	* Copyright (C) 2003-2004 MontaVista Software, Inc.
	11	*
	12	* This program is free software; you can redistribute it and/or modify
	13	* it under the terms of the GNU General Public License version 2 as
	14	* published by the Free Software Foundation.
	15	*
	16	*/
	17
	18	#include <linux/sched.h>
	19	#include <linux/kernel.h>
	20	#include <linux/pci.h>
	21	#include <linux/interrupt.h>
	22	#include <linux/mm.h>
	23	#include <linux/init.h>
	24	#include <linux/ioport.h>
	25	#include <linux/slab.h>
	26	#include <linux/delay.h>
	27	#include <linux/device.h>
fced80c7	28	#include <linux/io.h>
dc28094b	29	#include <linux/export.h>
1da177e4 LT	30	#include <asm/dma-mapping.h>
1da177e4 LT	31
0ba8b9b2	32	#include <asm/cputype.h>
1da177e4	33	#include <asm/irq.h>
87dfb311	34	#include <linux/sizes.h>
1da177e4	35	#include <asm/mach/pci.h>
a09e64fb	36	#include <mach/hardware.h>
1da177e4 LT	37
	38
	39	/*
	40	* IXP4xx PCI read function is dependent on whether we are
	41	* running A0 or B0 (AppleGate) silicon.
	42	*/
	43	int (ixp4xx_pci_read)(u32 addr, u32 cmd, u32 data);
	44
	45	/*
ad61dd30	46	* Base address for PCI register region
1da177e4 LT	47	*/
	48	unsigned long ixp4xx_pci_reg_base = 0;
	49
	50	/*
	51	* PCI cfg an I/O routines are done by programming a
	52	* command/byte enable register, and then read/writing
ad61dd30	53	* the data from a data register. We need to ensure
1da177e4 LT	54	* these transactions are atomic or we will end up
	55	* with corrupt data on the bus or in a driver.
	56	*/
bd31b859	57	static DEFINE_RAW_SPINLOCK(ixp4xx_pci_lock);
1da177e4 LT	58
	59	/*
	60	* Read from PCI config space
	61	*/
	62	static void crp_read(u32 ad_cbe, u32 *data)
	63	{
	64	unsigned long flags;
bd31b859	65	raw_spin_lock_irqsave(&ixp4xx_pci_lock, flags);
1da177e4 LT	66	*PCI_CRP_AD_CBE = ad_cbe;
1da177e4 LT	67	data = PCI_CRP_RDATA;
bd31b859	68	raw_spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
1da177e4 LT	69	}
	70
	71	/*
	72	* Write to PCI config space
	73	*/
	74	static void crp_write(u32 ad_cbe, u32 data)
	75	{
	76	unsigned long flags;
bd31b859	77	raw_spin_lock_irqsave(&ixp4xx_pci_lock, flags);
1da177e4 LT	78	*PCI_CRP_AD_CBE = CRP_AD_CBE_WRITE \| ad_cbe;
1da177e4 LT	79	*PCI_CRP_WDATA = data;
bd31b859	80	raw_spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
1da177e4 LT	81	}
	82
	83	static inline int check_master_abort(void)
	84	{
	85	/* check Master Abort bit after access */
	86	unsigned long isr = *PCI_ISR;
	87
	88	if (isr & PCI_ISR_PFE) {
	89	/* make sure the Master Abort bit is reset */
	90	*PCI_ISR = PCI_ISR_PFE;
8e86f427	91	pr_debug("%s failed\n", __func__);
1da177e4 LT	92	return 1;
	93	}
	94
	95	return 0;
	96	}
	97
	98	int ixp4xx_pci_read_errata(u32 addr, u32 cmd, u32* data)
	99	{
	100	unsigned long flags;
	101	int retval = 0;
	102	int i;
	103
bd31b859	104	raw_spin_lock_irqsave(&ixp4xx_pci_lock, flags);
1da177e4 LT	105
	106	*PCI_NP_AD = addr;
	107
	108	/*
	109	* PCI workaround - only works if NP PCI space reads have
	110	* no side effects!!! Read 8 times. last one will be good.
	111	*/
	112	for (i = 0; i < 8; i++) {
	113	*PCI_NP_CBE = cmd;
	114	data = PCI_NP_RDATA;
	115	data = PCI_NP_RDATA;
	116	}
	117
	118	if(check_master_abort())
	119	retval = 1;
	120
bd31b859	121	raw_spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
1da177e4 LT	122	return retval;
	123	}
	124
	125	int ixp4xx_pci_read_no_errata(u32 addr, u32 cmd, u32* data)
	126	{
	127	unsigned long flags;
	128	int retval = 0;
	129
bd31b859	130	raw_spin_lock_irqsave(&ixp4xx_pci_lock, flags);
1da177e4 LT	131
	132	*PCI_NP_AD = addr;
	133
	134	/* set up and execute the read */
	135	*PCI_NP_CBE = cmd;
	136
	137	/* the result of the read is now in NP_RDATA */
	138	data = PCI_NP_RDATA;
	139
	140	if(check_master_abort())
	141	retval = 1;
	142
bd31b859	143	raw_spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
1da177e4 LT	144	return retval;
	145	}
	146
	147	int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data)
	148	{
	149	unsigned long flags;
	150	int retval = 0;
	151
bd31b859	152	raw_spin_lock_irqsave(&ixp4xx_pci_lock, flags);
1da177e4 LT	153
	154	*PCI_NP_AD = addr;
	155
	156	/* set up the write */
	157	*PCI_NP_CBE = cmd;
	158
	159	/* execute the write by writing to NP_WDATA */
	160	*PCI_NP_WDATA = data;
	161
	162	if(check_master_abort())
	163	retval = 1;
	164
bd31b859	165	raw_spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
1da177e4 LT	166	return retval;
	167	}
	168
	169	static u32 ixp4xx_config_addr(u8 bus_num, u16 devfn, int where)
	170	{
	171	u32 addr;
	172	if (!bus_num) {
	173	/* type 0 */
	174	addr = BIT(32-PCI_SLOT(devfn)) \| ((PCI_FUNC(devfn)) << 8) \|
	175	(where & ~3);
	176	} else {
	177	/* type 1 */
	178	addr = (bus_num << 16) \| ((PCI_SLOT(devfn)) << 11) \|
	179	((PCI_FUNC(devfn)) << 8) \| (where & ~3) \| 1;
	180	}
	181	return addr;
	182	}
	183
	184	/*
	185	* Mask table, bits to mask for quantity of size 1, 2 or 4 bytes.
	186	* 0 and 3 are not valid indexes...
	187	*/
	188	static u32 bytemask[] = {
	189	/0/ 0,
	190	/1/ 0xff,
	191	/2/ 0xffff,
	192	/3/ 0,
	193	/4/ 0xffffffff,
	194	};
	195
	196	static u32 local_byte_lane_enable_bits(u32 n, int size)
	197	{
	198	if (size == 1)
	199	return (0xf & ~BIT(n)) << CRP_AD_CBE_BESL;
	200	if (size == 2)
	201	return (0xf & ~(BIT(n) \| BIT(n+1))) << CRP_AD_CBE_BESL;
	202	if (size == 4)
	203	return 0;
	204	return 0xffffffff;
	205	}
	206
	207	static int local_read_config(int where, int size, u32 *value)
	208	{
	209	u32 n, data;
	210	pr_debug("local_read_config from %d size %d\n", where, size);
	211	n = where % 4;
	212	crp_read(where & ~3, &data);
	213	value = (data >> (8n)) & bytemask[size];
	214	pr_debug("local_read_config read %#x\n", *value);
	215	return PCIBIOS_SUCCESSFUL;
	216	}
	217
	218	static int local_write_config(int where, int size, u32 value)
	219	{
	220	u32 n, byte_enables, data;
	221	pr_debug("local_write_config %#x to %d size %d\n", value, where, size);
	222	n = where % 4;
	223	byte_enables = local_byte_lane_enable_bits(n, size);
	224	if (byte_enables == 0xffffffff)
	225	return PCIBIOS_BAD_REGISTER_NUMBER;
	226	data = value << (8*n);
	227	crp_write((where & ~3) \| byte_enables, data);
	228	return PCIBIOS_SUCCESSFUL;
	229	}
230
231	static u32 byte_lane_enable_bits(u32 n, int size)
232	{
233	if (size == 1)
234	return (0xf & ~BIT(n)) << 4;
235	if (size == 2)
236	return (0xf & ~(BIT(n) \| BIT(n+1))) << 4;
237	if (size == 4)
238	return 0;
239	return 0xffffffff;
240	}
241
242	static int ixp4xx_pci_read_config(struct pci_bus bus, unsigned int devfn, int where, int size, u32 value)
243	{
244	u32 n, byte_enables, addr, data;
245	u8 bus_num = bus->number;
246
247	pr_debug("read_config from %d size %d dev %d:%d:%d\n", where, size,
248	bus_num, PCI_SLOT(devfn), PCI_FUNC(devfn));
249
250	*value = 0xffffffff;
251	n = where % 4;
252	byte_enables = byte_lane_enable_bits(n, size);
253	if (byte_enables == 0xffffffff)
254	return PCIBIOS_BAD_REGISTER_NUMBER;
255
256	addr = ixp4xx_config_addr(bus_num, devfn, where);
257	if (ixp4xx_pci_read(addr, byte_enables \| NP_CMD_CONFIGREAD, &data))
258	return PCIBIOS_DEVICE_NOT_FOUND;
259
260	value = (data >> (8n)) & bytemask[size];
261	pr_debug("read_config_byte read %#x\n", *value);
262	return PCIBIOS_SUCCESSFUL;
263	}
264
265	static int ixp4xx_pci_write_config(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value)
266	{
267	u32 n, byte_enables, addr, data;
268	u8 bus_num = bus->number;
269
270	pr_debug("write_config_byte %#x to %d size %d dev %d:%d:%d\n", value, where,
271	size, bus_num, PCI_SLOT(devfn), PCI_FUNC(devfn));
272
273	n = where % 4;
274	byte_enables = byte_lane_enable_bits(n, size);
275	if (byte_enables == 0xffffffff)
276	return PCIBIOS_BAD_REGISTER_NUMBER;
277
278	addr = ixp4xx_config_addr(bus_num, devfn, where);
279	data = value << (8*n);
280	if (ixp4xx_pci_write(addr, byte_enables \| NP_CMD_CONFIGWRITE, data))
281	return PCIBIOS_DEVICE_NOT_FOUND;
282
283	return PCIBIOS_SUCCESSFUL;
284	}
285
286	struct pci_ops ixp4xx_ops = {
287	.read = ixp4xx_pci_read_config,
288	.write = ixp4xx_pci_write_config,
289	};
290
291	/*
292	* PCI abort handler
293	*/
294	static int abort_handler(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
295	{
296	u32 isr, status;
297
298	isr = *PCI_ISR;
299	local_read_config(PCI_STATUS, 2, &status);
300	pr_debug("PCI: abort_handler addr = %#lx, isr = %#x, "
301	"status = %#x\n", addr, isr, status);
302
303	/* make sure the Master Abort bit is reset */
304	*PCI_ISR = PCI_ISR_PFE;
305	status \|= PCI_STATUS_REC_MASTER_ABORT;
306	local_write_config(PCI_STATUS, 2, status);
307
308	/*
309	* If it was an imprecise abort, then we need to correct the
310	* return address to be _after_ the instruction.
311	*/
312	if (fsr & (1 << 10))
313	regs->ARM_pc += 4;
314
315	return 0;
316	}
317
1da177e4	318	void __init ixp4xx_pci_preinit(void)
0a07232f	319	{
0ba8b9b2	320	unsigned long cpuid = read_cpuid_id();
1da177e4	321
c9d95fbe RH	322	#ifdef CONFIG_IXP4XX_INDIRECT_PCI
	323	pcibios_min_mem = 0x10000000; /* 1 GB of indirect PCI MMIO space */
	324	#else
	325	pcibios_min_mem = 0x48000000; /* 64 MB of PCI MMIO space */
	326	#endif
1da177e4 LT	327	/*
	328	* Determine which PCI read method to use.
	329	* Rev 0 IXP425 requires workaround.
	330	*/
0ba8b9b2	331	if (!(cpuid & 0xf) && cpu_is_ixp42x()) {
1da177e4 LT	332	printk("PCI: IXP42x A0 silicon detected - "
	333	"PCI Non-Prefetch Workaround Enabled\n");
	334	ixp4xx_pci_read = ixp4xx_pci_read_errata;
	335	} else
	336	ixp4xx_pci_read = ixp4xx_pci_read_no_errata;
	337
	338
	339	/* hook in our fault handler for PCI errors */
6338a6aa KS	340	hook_fault_code(16+6, abort_handler, SIGBUS, 0,
6338a6aa KS	341	"imprecise external abort");
1da177e4 LT	342
	343	pr_debug("setup PCI-AHB(inbound) and AHB-PCI(outbound) address mappings\n");
	344
0a07232f	345	/*
1da177e4 LT	346	* We use identity AHB->PCI address translation
	347	* in the 0x48000000 to 0x4bffffff address space
	348	*/
	349	*PCI_PCIMEMBASE = 0x48494A4B;
	350
0a07232f	351	/*
1da177e4 LT	352	* We also use identity PCI->AHB address translation
	353	* in 4 16MB BARs that begin at the physical memory start
	354	*/
0a07232f	355	*PCI_AHBMEMBASE = (PHYS_OFFSET & 0xFF000000) +
1da177e4 LT	356	((PHYS_OFFSET & 0xFF000000) >> 8) +
	357	((PHYS_OFFSET & 0xFF000000) >> 16) +
	358	((PHYS_OFFSET & 0xFF000000) >> 24) +
	359	0x00010203;
	360
	361	if (*PCI_CSR & PCI_CSR_HOST) {
	362	printk("PCI: IXP4xx is host\n");
	363
	364	pr_debug("setup BARs in controller\n");
	365
	366	/*
0a07232f	367	* We configure the PCI inbound memory windows to be
1da177e4 LT	368	* 1:1 mapped to SDRAM
1da177e4 LT	369	*/
0a07232f KH	370	local_write_config(PCI_BASE_ADDRESS_0, 4, PHYS_OFFSET);
	371	local_write_config(PCI_BASE_ADDRESS_1, 4, PHYS_OFFSET + SZ_16M);
	372	local_write_config(PCI_BASE_ADDRESS_2, 4, PHYS_OFFSET + SZ_32M);
3f8e2880 SB	373	local_write_config(PCI_BASE_ADDRESS_3, 4,
3f8e2880 SB	374	PHYS_OFFSET + SZ_32M + SZ_16M);
1da177e4 LT	375
1da177e4 LT	376	/*
0a07232f KH	377	* Enable CSR window at 64 MiB to allow PCI masters
0a07232f KH	378	* to continue prefetching past 64 MiB boundary.
1da177e4	379	*/
0a07232f	380	local_write_config(PCI_BASE_ADDRESS_4, 4, PHYS_OFFSET + SZ_64M);
1da177e4 LT	381
	382	/*
	383	* Enable the IO window to be way up high, at 0xfffffc00
	384	*/
	385	local_write_config(PCI_BASE_ADDRESS_5, 4, 0xfffffc01);
f203bc64	386	local_write_config(0x40, 4, 0x000080FF); /* No TRDY time limit */
1da177e4 LT	387	} else {
	388	printk("PCI: IXP4xx is target - No bus scan performed\n");
	389	}
	390
	391	printk("PCI: IXP4xx Using %s access for memory space\n",
	392	#ifndef CONFIG_IXP4XX_INDIRECT_PCI
	393	"direct"
	394	#else
	395	"indirect"
	396	#endif
	397	);
	398
	399	pr_debug("clear error bits in ISR\n");
	400	*PCI_ISR = PCI_ISR_PSE \| PCI_ISR_PFE \| PCI_ISR_PPE \| PCI_ISR_AHBE;
	401
	402	/*
	403	* Set Initialize Complete in PCI Control Register: allow IXP4XX to
	404	* respond to PCI configuration cycles. Specify that the AHB bus is
	405	* operating in big endian mode. Set up byte lane swapping between
	406	* little-endian PCI and the big-endian AHB bus
	407	*/
	408	#ifdef __ARMEB__
	409	*PCI_CSR = PCI_CSR_IC \| PCI_CSR_ABE \| PCI_CSR_PDS \| PCI_CSR_ADS;
	410	#else
84613387	411	*PCI_CSR = PCI_CSR_IC \| PCI_CSR_ABE;
1da177e4 LT	412	#endif
	413
	414	pr_debug("DONE\n");
	415	}
	416
	417	int ixp4xx_setup(int nr, struct pci_sys_data *sys)
	418	{
	419	struct resource *res;
	420
	421	if (nr >= 1)
	422	return 0;
	423
6396bb22	424	res = kcalloc(2, sizeof(*res), GFP_KERNEL);
1da177e4 LT	425	if (res == NULL) {
	426	/*
	427	* If we're out of memory this early, something is wrong,
	428	* so we might as well catch it here.
	429	*/
	430	panic("PCI: unable to allocate resources?\n");
	431	}
1da177e4 LT	432
	433	local_write_config(PCI_COMMAND, 2, PCI_COMMAND_MASTER \| PCI_COMMAND_MEMORY);
	434
	435	res[0].name = "PCI I/O Space";
450008b5 DS	436	res[0].start = 0x00000000;
450008b5 DS	437	res[0].end = 0x0000ffff;
1da177e4 LT	438	res[0].flags = IORESOURCE_IO;
	439
	440	res[1].name = "PCI Memory Space";
45fba084	441	res[1].start = PCIBIOS_MIN_MEM;
ed5b9fa0	442	res[1].end = PCIBIOS_MAX_MEM;
1da177e4 LT	443	res[1].flags = IORESOURCE_MEM;
	444
	445	request_resource(&ioport_resource, &res[0]);
	446	request_resource(&iomem_resource, &res[1]);
	447
9f786d03 BH	448	pci_add_resource_offset(&sys->resources, &res[0], sys->io_offset);
9f786d03 BH	449	pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset);
1da177e4	450
1da177e4 LT	451	return 1;
	452	}
	453
1da177e4 LT	454	EXPORT_SYMBOL(ixp4xx_pci_read);
1da177e4 LT	455	EXPORT_SYMBOL(ixp4xx_pci_write);