[mirror_ubuntu-jammy-kernel.git] / arch / arm / mach-ixp4xx / goramo_mlr.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Goramo MultiLink router platform code
 * Copyright (C) 2006-2009 Krzysztof Halasa <khc@pm.waw.pl>
 */

#include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/hdlc.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/platform_data/wan_ixp4xx_hss.h>
#include <linux/serial_8250.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/flash.h>
#include <asm/mach/pci.h>
#include <asm/system_info.h>

#include "irqs.h"

#define SLOT_ETHA		0x0B	/* IDSEL = AD21 */
#define SLOT_ETHB		0x0C	/* IDSEL = AD20 */
#define SLOT_MPCI		0x0D	/* IDSEL = AD19 */
#define SLOT_NEC		0x0E	/* IDSEL = AD18 */

/* GPIO lines */
#define GPIO_SCL		0
#define GPIO_SDA		1
#define GPIO_STR		2
#define GPIO_IRQ_NEC		3
#define GPIO_IRQ_ETHA		4
#define GPIO_IRQ_ETHB		5
#define GPIO_HSS0_DCD_N		6
#define GPIO_HSS1_DCD_N		7
#define GPIO_UART0_DCD		8
#define GPIO_UART1_DCD		9
#define GPIO_HSS0_CTS_N		10
#define GPIO_HSS1_CTS_N		11
#define GPIO_IRQ_MPCI		12
#define GPIO_HSS1_RTS_N		13
#define GPIO_HSS0_RTS_N		14
/* GPIO15 is not connected */

/* Control outputs from 74HC4094 */
#define CONTROL_HSS0_CLK_INT	0
#define CONTROL_HSS1_CLK_INT	1
#define CONTROL_HSS0_DTR_N	2
#define CONTROL_HSS1_DTR_N	3
#define CONTROL_EXT		4
#define CONTROL_AUTO_RESET	5
#define CONTROL_PCI_RESET_N	6
#define CONTROL_EEPROM_WC_N	7

/* offsets from start of flash ROM = 0x50000000 */
#define CFG_ETH0_ADDRESS	0x40 /* 6 bytes */
#define CFG_ETH1_ADDRESS	0x46 /* 6 bytes */
#define CFG_REV			0x4C /* u32 */
#define CFG_SDRAM_SIZE		0x50 /* u32 */
#define CFG_SDRAM_CONF		0x54 /* u32 */
#define CFG_SDRAM_MODE		0x58 /* u32 */
#define CFG_SDRAM_REFRESH	0x5C /* u32 */

#define CFG_HW_BITS		0x60 /* u32 */
#define  CFG_HW_USB_PORTS	0x00000007 /* 0 = no NEC chip, 1-5 = ports # */
#define  CFG_HW_HAS_PCI_SLOT	0x00000008
#define  CFG_HW_HAS_ETH0	0x00000010
#define  CFG_HW_HAS_ETH1	0x00000020
#define  CFG_HW_HAS_HSS0	0x00000040
#define  CFG_HW_HAS_HSS1	0x00000080
#define  CFG_HW_HAS_UART0	0x00000100
#define  CFG_HW_HAS_UART1	0x00000200
#define  CFG_HW_HAS_EEPROM	0x00000400

#define FLASH_CMD_READ_ARRAY	0xFF
#define FLASH_CMD_READ_ID	0x90
#define FLASH_SER_OFF		0x102 /* 0x81 in 16-bit mode */

static u32 hw_bits = 0xFFFFFFFD;    /* assume all hardware present */;
static u8 control_value;

/*
 * FIXME: this is reimplementing I2C bit-bangining. Move this
 * over to using driver/i2c/busses/i2c-gpio.c like all other boards
 * and register proper I2C device(s) on the bus for this. (See
 * other IXP4xx boards for examples.)
 */
static void set_scl(u8 value)
{
	gpio_set_value(GPIO_SCL, !!value);
	udelay(3);
}

static void set_sda(u8 value)
{
	gpio_set_value(GPIO_SDA, !!value);
	udelay(3);
}

static void set_str(u8 value)
{
	gpio_set_value(GPIO_STR, !!value);
	udelay(3);
}

static inline void set_control(int line, int value)
{
	if (value)
		control_value |=  (1 << line);
	else
		control_value &= ~(1 << line);
}


static void output_control(void)
{
	int i;

	gpio_direction_output(GPIO_SCL, 1);
	gpio_direction_output(GPIO_SDA, 1);

	for (i = 0; i < 8; i++) {
		set_scl(0);
		set_sda(control_value & (0x80 >> i)); /* MSB first */
		set_scl(1);	/* active edge */
	}

	set_str(1);
	set_str(0);

	set_scl(0);
	set_sda(1);		/* Be ready for START */
	set_scl(1);
}


static void (*set_carrier_cb_tab[2])(void *pdev, int carrier);

static int hss_set_clock(int port, unsigned int clock_type)
{
	int ctrl_int = port ? CONTROL_HSS1_CLK_INT : CONTROL_HSS0_CLK_INT;

	switch (clock_type) {
	case CLOCK_DEFAULT:
	case CLOCK_EXT:
		set_control(ctrl_int, 0);
		output_control();
		return CLOCK_EXT;

	case CLOCK_INT:
		set_control(ctrl_int, 1);
		output_control();
		return CLOCK_INT;

	default:
		return -EINVAL;
	}
}

static irqreturn_t hss_dcd_irq(int irq, void *pdev)
{
	int port = (irq == IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N));
	int i = gpio_get_value(port ? GPIO_HSS1_DCD_N : GPIO_HSS0_DCD_N);
	set_carrier_cb_tab[port](pdev, !i);
	return IRQ_HANDLED;
}


static int hss_open(int port, void *pdev,
		    void (*set_carrier_cb)(void *pdev, int carrier))
{
	int i, irq;

	if (!port)
		irq = IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N);
	else
		irq = IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N);

	i = gpio_get_value(port ? GPIO_HSS1_DCD_N : GPIO_HSS0_DCD_N);
	set_carrier_cb(pdev, !i);

	set_carrier_cb_tab[!!port] = set_carrier_cb;

	if ((i = request_irq(irq, hss_dcd_irq, 0, "IXP4xx HSS", pdev)) != 0) {
		printk(KERN_ERR "ixp4xx_hss: failed to request IRQ%i (%i)\n",
		       irq, i);
		return i;
	}

	set_control(port ? CONTROL_HSS1_DTR_N : CONTROL_HSS0_DTR_N, 0);
	output_control();
	gpio_set_value(port ? GPIO_HSS1_RTS_N : GPIO_HSS0_RTS_N, 0);
	return 0;
}

static void hss_close(int port, void *pdev)
{
	free_irq(port ? IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N) :
		 IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N), pdev);
	set_carrier_cb_tab[!!port] = NULL; /* catch bugs */

	set_control(port ? CONTROL_HSS1_DTR_N : CONTROL_HSS0_DTR_N, 1);
	output_control();
	gpio_set_value(port ? GPIO_HSS1_RTS_N : GPIO_HSS0_RTS_N, 1);
}


/* Flash memory */
static struct flash_platform_data flash_data = {
	.map_name	= "cfi_probe",
	.width		= 2,
};

static struct resource flash_resource = {
	.flags		= IORESOURCE_MEM,
};

static struct platform_device device_flash = {
	.name		= "IXP4XX-Flash",
	.id		= 0,
	.dev		= { .platform_data = &flash_data },
	.num_resources	= 1,
	.resource	= &flash_resource,
};

/* IXP425 2 UART ports */
static struct resource uart_resources[] = {
	{
		.start		= IXP4XX_UART1_BASE_PHYS,
		.end		= IXP4XX_UART1_BASE_PHYS + 0x0fff,
		.flags		= IORESOURCE_MEM,
	},
	{
		.start		= IXP4XX_UART2_BASE_PHYS,
		.end		= IXP4XX_UART2_BASE_PHYS + 0x0fff,
		.flags		= IORESOURCE_MEM,
	}
};

static struct plat_serial8250_port uart_data[] = {
	{
		.mapbase	= IXP4XX_UART1_BASE_PHYS,
		.membase	= (char __iomem *)IXP4XX_UART1_BASE_VIRT +
			REG_OFFSET,
		.irq		= IRQ_IXP4XX_UART1,
		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
		.iotype		= UPIO_MEM,
		.regshift	= 2,
		.uartclk	= IXP4XX_UART_XTAL,
	},
	{
		.mapbase	= IXP4XX_UART2_BASE_PHYS,
		.membase	= (char __iomem *)IXP4XX_UART2_BASE_VIRT +
			REG_OFFSET,
		.irq		= IRQ_IXP4XX_UART2,
		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
		.iotype		= UPIO_MEM,
		.regshift	= 2,
		.uartclk	= IXP4XX_UART_XTAL,
	},
	{ },
};

static struct platform_device device_uarts = {
	.name			= "serial8250",
	.id			= PLAT8250_DEV_PLATFORM,
	.dev.platform_data	= uart_data,
	.num_resources		= 2,
	.resource		= uart_resources,
};


/* Built-in 10/100 Ethernet MAC interfaces */
static struct resource eth_npeb_resources[] = {
	{
		.start		= IXP4XX_EthB_BASE_PHYS,
		.end		= IXP4XX_EthB_BASE_PHYS + 0x0fff,
		.flags		= IORESOURCE_MEM,
	},
};

static struct resource eth_npec_resources[] = {
	{
		.start		= IXP4XX_EthC_BASE_PHYS,
		.end		= IXP4XX_EthC_BASE_PHYS + 0x0fff,
		.flags		= IORESOURCE_MEM,
	},
};

static struct eth_plat_info eth_plat[] = {
	{
		.phy		= 0,
		.rxq		= 3,
		.txreadyq	= 32,
	}, {
		.phy		= 1,
		.rxq		= 4,
		.txreadyq	= 33,
	}
};

static struct platform_device device_eth_tab[] = {
	{
		.name			= "ixp4xx_eth",
		.id			= IXP4XX_ETH_NPEB,
		.dev.platform_data	= eth_plat,
		.num_resources		= ARRAY_SIZE(eth_npeb_resources),
		.resource		= eth_npeb_resources,
	}, {
		.name			= "ixp4xx_eth",
		.id			= IXP4XX_ETH_NPEC,
		.dev.platform_data	= eth_plat + 1,
		.num_resources		= ARRAY_SIZE(eth_npec_resources),
		.resource		= eth_npec_resources,
	}
};


/* IXP425 2 synchronous serial ports */
static struct hss_plat_info hss_plat[] = {
	{
		.set_clock	= hss_set_clock,
		.open		= hss_open,
		.close		= hss_close,
		.txreadyq	= 34,
	}, {
		.set_clock	= hss_set_clock,
		.open		= hss_open,
		.close		= hss_close,
		.txreadyq	= 35,
	}
};

static struct platform_device device_hss_tab[] = {
	{
		.name			= "ixp4xx_hss",
		.id			= 0,
		.dev.platform_data	= hss_plat,
	}, {
		.name			= "ixp4xx_hss",
		.id			= 1,
		.dev.platform_data	= hss_plat + 1,
	}
};


static struct platform_device *device_tab[7] __initdata = {
	&device_flash,		/* index 0 */
};

static inline u8 __init flash_readb(u8 __iomem *flash, u32 addr)
{
#ifdef __ARMEB__
	return __raw_readb(flash + addr);
#else
	return __raw_readb(flash + (addr ^ 3));
#endif
}

static inline u16 __init flash_readw(u8 __iomem *flash, u32 addr)
{
#ifdef __ARMEB__
	return __raw_readw(flash + addr);
#else
	return __raw_readw(flash + (addr ^ 2));
#endif
}

static void __init gmlr_init(void)
{
	u8 __iomem *flash;
	int i, devices = 1; /* flash */

	ixp4xx_sys_init();

	if ((flash = ioremap(IXP4XX_EXP_BUS_BASE_PHYS, 0x80)) == NULL)
		printk(KERN_ERR "goramo-mlr: unable to access system"
		       " configuration data\n");
	else {
		system_rev = __raw_readl(flash + CFG_REV);
		hw_bits = __raw_readl(flash + CFG_HW_BITS);

		for (i = 0; i < ETH_ALEN; i++) {
			eth_plat[0].hwaddr[i] =
				flash_readb(flash, CFG_ETH0_ADDRESS + i);
			eth_plat[1].hwaddr[i] =
				flash_readb(flash, CFG_ETH1_ADDRESS + i);
		}

		__raw_writew(FLASH_CMD_READ_ID, flash);
		system_serial_high = flash_readw(flash, FLASH_SER_OFF);
		system_serial_high <<= 16;
		system_serial_high |= flash_readw(flash, FLASH_SER_OFF + 2);
		system_serial_low = flash_readw(flash, FLASH_SER_OFF + 4);
		system_serial_low <<= 16;
		system_serial_low |= flash_readw(flash, FLASH_SER_OFF + 6);
		__raw_writew(FLASH_CMD_READ_ARRAY, flash);

		iounmap(flash);
	}

	switch (hw_bits & (CFG_HW_HAS_UART0 | CFG_HW_HAS_UART1)) {
	case CFG_HW_HAS_UART0:
		memset(&uart_data[1], 0, sizeof(uart_data[1]));
		device_uarts.num_resources = 1;
		break;

	case CFG_HW_HAS_UART1:
		device_uarts.dev.platform_data = &uart_data[1];
		device_uarts.resource = &uart_resources[1];
		device_uarts.num_resources = 1;
		break;
	}
	if (hw_bits & (CFG_HW_HAS_UART0 | CFG_HW_HAS_UART1))
		device_tab[devices++] = &device_uarts; /* max index 1 */

	if (hw_bits & CFG_HW_HAS_ETH0)
		device_tab[devices++] = &device_eth_tab[0]; /* max index 2 */
	if (hw_bits & CFG_HW_HAS_ETH1)
		device_tab[devices++] = &device_eth_tab[1]; /* max index 3 */

	if (hw_bits & CFG_HW_HAS_HSS0)
		device_tab[devices++] = &device_hss_tab[0]; /* max index 4 */
	if (hw_bits & CFG_HW_HAS_HSS1)
		device_tab[devices++] = &device_hss_tab[1]; /* max index 5 */

	hss_plat[0].timer_freq = ixp4xx_timer_freq;
	hss_plat[1].timer_freq = ixp4xx_timer_freq;

	gpio_request(GPIO_SCL, "SCL/clock");
	gpio_request(GPIO_SDA, "SDA/data");
	gpio_request(GPIO_STR, "strobe");
	gpio_request(GPIO_HSS0_RTS_N, "HSS0 RTS");
	gpio_request(GPIO_HSS1_RTS_N, "HSS1 RTS");
	gpio_request(GPIO_HSS0_DCD_N, "HSS0 DCD");
	gpio_request(GPIO_HSS1_DCD_N, "HSS1 DCD");

	gpio_direction_output(GPIO_SCL, 1);
	gpio_direction_output(GPIO_SDA, 1);
	gpio_direction_output(GPIO_STR, 0);
	gpio_direction_output(GPIO_HSS0_RTS_N, 1);
	gpio_direction_output(GPIO_HSS1_RTS_N, 1);
	gpio_direction_input(GPIO_HSS0_DCD_N);
	gpio_direction_input(GPIO_HSS1_DCD_N);
	irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N), IRQ_TYPE_EDGE_BOTH);
	irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N), IRQ_TYPE_EDGE_BOTH);

	set_control(CONTROL_HSS0_DTR_N, 1);
	set_control(CONTROL_HSS1_DTR_N, 1);
	set_control(CONTROL_EEPROM_WC_N, 1);
	set_control(CONTROL_PCI_RESET_N, 1);
	output_control();

	msleep(1);	      /* Wait for PCI devices to initialize */

	flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
	flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1;

	platform_add_devices(device_tab, devices);
}


#ifdef CONFIG_PCI
static void __init gmlr_pci_preinit(void)
{
	irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHA), IRQ_TYPE_LEVEL_LOW);
	irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHB), IRQ_TYPE_LEVEL_LOW);
	irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_NEC), IRQ_TYPE_LEVEL_LOW);
	irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_MPCI), IRQ_TYPE_LEVEL_LOW);
	ixp4xx_pci_preinit();
}

static void __init gmlr_pci_postinit(void)
{
	if ((hw_bits & CFG_HW_USB_PORTS) >= 2 &&
	    (hw_bits & CFG_HW_USB_PORTS) < 5) {
		/* need to adjust number of USB ports on NEC chip */
		u32 value, addr = BIT(32 - SLOT_NEC) | 0xE0;
		if (!ixp4xx_pci_read(addr, NP_CMD_CONFIGREAD, &value)) {
			value &= ~7;
			value |= (hw_bits & CFG_HW_USB_PORTS);
			ixp4xx_pci_write(addr, NP_CMD_CONFIGWRITE, value);
		}
	}
}

static int __init gmlr_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
	switch(slot) {
	case SLOT_ETHA:	return IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHA);
	case SLOT_ETHB:	return IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHB);
	case SLOT_NEC:	return IXP4XX_GPIO_IRQ(GPIO_IRQ_NEC);
	default:	return IXP4XX_GPIO_IRQ(GPIO_IRQ_MPCI);
	}
}

static struct hw_pci gmlr_hw_pci __initdata = {
	.nr_controllers = 1,
	.ops		= &ixp4xx_ops,
	.preinit	= gmlr_pci_preinit,
	.postinit	= gmlr_pci_postinit,
	.setup		= ixp4xx_setup,
	.map_irq	= gmlr_map_irq,
};

static int __init gmlr_pci_init(void)
{
	if (machine_is_goramo_mlr() &&
	    (hw_bits & (CFG_HW_USB_PORTS | CFG_HW_HAS_PCI_SLOT)))
		pci_common_init(&gmlr_hw_pci);
	return 0;
}

subsys_initcall(gmlr_pci_init);
#endif /* CONFIG_PCI */


MACHINE_START(GORAMO_MLR, "MultiLink")
	/* Maintainer: Krzysztof Halasa */
	.map_io		= ixp4xx_map_io,
	.init_early	= ixp4xx_init_early,
	.init_irq	= ixp4xx_init_irq,
	.init_time	= ixp4xx_timer_init,
	.atag_offset	= 0x100,
	.init_machine	= gmlr_init,
#if defined(CONFIG_PCI)
	.dma_zone_size	= SZ_64M,
#endif
	.restart	= ixp4xx_restart,
MACHINE_END
Commit	Line	Data
b2441318	1	// SPDX-License-Identifier: GPL-2.0
11c79740 KH	2	/*
	3	* Goramo MultiLink router platform code
	4	* Copyright (C) 2006-2009 Krzysztof Halasa <khc@pm.waw.pl>
	5	*/
	6
	7	#include <linux/delay.h>
e1a4018f	8	#include <linux/gpio.h>
11c79740	9	#include <linux/hdlc.h>
11c79740 KH	10	#include <linux/io.h>
	11	#include <linux/irq.h>
	12	#include <linux/kernel.h>
	13	#include <linux/pci.h>
c74f16b6	14	#include <linux/platform_data/wan_ixp4xx_hss.h>
11c79740 KH	15	#include <linux/serial_8250.h>
11c79740 KH	16	#include <asm/mach-types.h>
11c79740 KH	17	#include <asm/mach/arch.h>
	18	#include <asm/mach/flash.h>
	19	#include <asm/mach/pci.h>
3043c5c8	20	#include <asm/system_info.h>
11c79740	21
140d9009 AB	22	#include "irqs.h"
140d9009 AB	23
11c79740 KH	24	#define SLOT_ETHA 0x0B /* IDSEL = AD21 */
	25	#define SLOT_ETHB 0x0C /* IDSEL = AD20 */
	26	#define SLOT_MPCI 0x0D /* IDSEL = AD19 */
	27	#define SLOT_NEC 0x0E /* IDSEL = AD18 */
	28
11c79740 KH	29	/* GPIO lines */
	30	#define GPIO_SCL 0
	31	#define GPIO_SDA 1
	32	#define GPIO_STR 2
8d3fdf31 KH	33	#define GPIO_IRQ_NEC 3
	34	#define GPIO_IRQ_ETHA 4
	35	#define GPIO_IRQ_ETHB 5
11c79740 KH	36	#define GPIO_HSS0_DCD_N 6
11c79740 KH	37	#define GPIO_HSS1_DCD_N 7
8d3fdf31 KH	38	#define GPIO_UART0_DCD 8
8d3fdf31 KH	39	#define GPIO_UART1_DCD 9
11c79740 KH	40	#define GPIO_HSS0_CTS_N 10
11c79740 KH	41	#define GPIO_HSS1_CTS_N 11
8d3fdf31	42	#define GPIO_IRQ_MPCI 12
11c79740 KH	43	#define GPIO_HSS1_RTS_N 13
11c79740 KH	44	#define GPIO_HSS0_RTS_N 14
8d3fdf31	45	/* GPIO15 is not connected */
11c79740 KH	46
	47	/* Control outputs from 74HC4094 */
	48	#define CONTROL_HSS0_CLK_INT 0
	49	#define CONTROL_HSS1_CLK_INT 1
	50	#define CONTROL_HSS0_DTR_N 2
	51	#define CONTROL_HSS1_DTR_N 3
	52	#define CONTROL_EXT 4
	53	#define CONTROL_AUTO_RESET 5
	54	#define CONTROL_PCI_RESET_N 6
	55	#define CONTROL_EEPROM_WC_N 7
	56
	57	/* offsets from start of flash ROM = 0x50000000 */
	58	#define CFG_ETH0_ADDRESS 0x40 /* 6 bytes */
	59	#define CFG_ETH1_ADDRESS 0x46 /* 6 bytes */
	60	#define CFG_REV 0x4C /* u32 */
	61	#define CFG_SDRAM_SIZE 0x50 /* u32 */
	62	#define CFG_SDRAM_CONF 0x54 /* u32 */
	63	#define CFG_SDRAM_MODE 0x58 /* u32 */
	64	#define CFG_SDRAM_REFRESH 0x5C /* u32 */
	65
	66	#define CFG_HW_BITS 0x60 /* u32 */
	67	#define CFG_HW_USB_PORTS 0x00000007 /* 0 = no NEC chip, 1-5 = ports # */
	68	#define CFG_HW_HAS_PCI_SLOT 0x00000008
	69	#define CFG_HW_HAS_ETH0 0x00000010
	70	#define CFG_HW_HAS_ETH1 0x00000020
	71	#define CFG_HW_HAS_HSS0 0x00000040
	72	#define CFG_HW_HAS_HSS1 0x00000080
	73	#define CFG_HW_HAS_UART0 0x00000100
	74	#define CFG_HW_HAS_UART1 0x00000200
	75	#define CFG_HW_HAS_EEPROM 0x00000400
	76
	77	#define FLASH_CMD_READ_ARRAY 0xFF
	78	#define FLASH_CMD_READ_ID 0x90
	79	#define FLASH_SER_OFF 0x102 /* 0x81 in 16-bit mode */
	80
	81	static u32 hw_bits = 0xFFFFFFFD; /* assume all hardware present */;
	82	static u8 control_value;
	83
b2e63555 LW	84	/*
	85	* FIXME: this is reimplementing I2C bit-bangining. Move this
	86	* over to using driver/i2c/busses/i2c-gpio.c like all other boards
	87	* and register proper I2C device(s) on the bus for this. (See
	88	* other IXP4xx boards for examples.)
	89	*/
11c79740 KH	90	static void set_scl(u8 value)
11c79740 KH	91	{
e1a4018f	92	gpio_set_value(GPIO_SCL, !!value);
11c79740 KH	93	udelay(3);
	94	}
	95
	96	static void set_sda(u8 value)
	97	{
e1a4018f	98	gpio_set_value(GPIO_SDA, !!value);
11c79740 KH	99	udelay(3);
	100	}
	101
	102	static void set_str(u8 value)
	103	{
e1a4018f	104	gpio_set_value(GPIO_STR, !!value);
11c79740 KH	105	udelay(3);
	106	}
	107
	108	static inline void set_control(int line, int value)
	109	{
	110	if (value)
	111	control_value \|= (1 << line);
	112	else
	113	control_value &= ~(1 << line);
	114	}
	115
	116
	117	static void output_control(void)
	118	{
	119	int i;
	120
e1a4018f KH	121	gpio_direction_output(GPIO_SCL, 1);
e1a4018f KH	122	gpio_direction_output(GPIO_SDA, 1);
11c79740 KH	123
	124	for (i = 0; i < 8; i++) {
	125	set_scl(0);
	126	set_sda(control_value & (0x80 >> i)); /* MSB first */
	127	set_scl(1); /* active edge */
	128	}
	129
	130	set_str(1);
	131	set_str(0);
	132
	133	set_scl(0);
	134	set_sda(1); /* Be ready for START */
	135	set_scl(1);
	136	}
	137
	138
	139	static void (set_carrier_cb_tab[2])(void pdev, int carrier);
	140
	141	static int hss_set_clock(int port, unsigned int clock_type)
	142	{
	143	int ctrl_int = port ? CONTROL_HSS1_CLK_INT : CONTROL_HSS0_CLK_INT;
	144
	145	switch (clock_type) {
	146	case CLOCK_DEFAULT:
	147	case CLOCK_EXT:
	148	set_control(ctrl_int, 0);
	149	output_control();
	150	return CLOCK_EXT;
	151
	152	case CLOCK_INT:
	153	set_control(ctrl_int, 1);
	154	output_control();
	155	return CLOCK_INT;
	156
	157	default:
	158	return -EINVAL;
	159	}
	160	}
	161
	162	static irqreturn_t hss_dcd_irq(int irq, void *pdev)
	163	{
e1a4018f KH	164	int port = (irq == IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N));
e1a4018f KH	165	int i = gpio_get_value(port ? GPIO_HSS1_DCD_N : GPIO_HSS0_DCD_N);
11c79740 KH	166	set_carrier_cb_tab[port](pdev, !i);
	167	return IRQ_HANDLED;
	168	}
	169
	170
	171	static int hss_open(int port, void *pdev,
	172	void (set_carrier_cb)(void pdev, int carrier))
	173	{
	174	int i, irq;
	175
	176	if (!port)
8d3fdf31	177	irq = IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N);
11c79740	178	else
8d3fdf31	179	irq = IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N);
11c79740	180
e1a4018f	181	i = gpio_get_value(port ? GPIO_HSS1_DCD_N : GPIO_HSS0_DCD_N);
11c79740 KH	182	set_carrier_cb(pdev, !i);
	183
	184	set_carrier_cb_tab[!!port] = set_carrier_cb;
	185
	186	if ((i = request_irq(irq, hss_dcd_irq, 0, "IXP4xx HSS", pdev)) != 0) {
	187	printk(KERN_ERR "ixp4xx_hss: failed to request IRQ%i (%i)\n",
	188	irq, i);
	189	return i;
	190	}
	191
	192	set_control(port ? CONTROL_HSS1_DTR_N : CONTROL_HSS0_DTR_N, 0);
	193	output_control();
e1a4018f	194	gpio_set_value(port ? GPIO_HSS1_RTS_N : GPIO_HSS0_RTS_N, 0);
11c79740 KH	195	return 0;
	196	}
	197
	198	static void hss_close(int port, void *pdev)
	199	{
8d3fdf31 KH	200	free_irq(port ? IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N) :
8d3fdf31 KH	201	IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N), pdev);
11c79740 KH	202	set_carrier_cb_tab[!!port] = NULL; /* catch bugs */
	203
	204	set_control(port ? CONTROL_HSS1_DTR_N : CONTROL_HSS0_DTR_N, 1);
	205	output_control();
e1a4018f	206	gpio_set_value(port ? GPIO_HSS1_RTS_N : GPIO_HSS0_RTS_N, 1);
11c79740 KH	207	}
	208
	209
	210	/* Flash memory */
	211	static struct flash_platform_data flash_data = {
	212	.map_name = "cfi_probe",
	213	.width = 2,
	214	};
	215
	216	static struct resource flash_resource = {
	217	.flags = IORESOURCE_MEM,
	218	};
	219
	220	static struct platform_device device_flash = {
	221	.name = "IXP4XX-Flash",
	222	.id = 0,
	223	.dev = { .platform_data = &flash_data },
	224	.num_resources = 1,
	225	.resource = &flash_resource,
	226	};
	227
11c79740 KH	228	/* IXP425 2 UART ports */
	229	static struct resource uart_resources[] = {
	230	{
	231	.start = IXP4XX_UART1_BASE_PHYS,
	232	.end = IXP4XX_UART1_BASE_PHYS + 0x0fff,
	233	.flags = IORESOURCE_MEM,
	234	},
	235	{
	236	.start = IXP4XX_UART2_BASE_PHYS,
	237	.end = IXP4XX_UART2_BASE_PHYS + 0x0fff,
	238	.flags = IORESOURCE_MEM,
	239	}
	240	};
	241
	242	static struct plat_serial8250_port uart_data[] = {
	243	{
	244	.mapbase = IXP4XX_UART1_BASE_PHYS,
	245	.membase = (char __iomem *)IXP4XX_UART1_BASE_VIRT +
	246	REG_OFFSET,
	247	.irq = IRQ_IXP4XX_UART1,
	248	.flags = UPF_BOOT_AUTOCONF \| UPF_SKIP_TEST,
	249	.iotype = UPIO_MEM,
	250	.regshift = 2,
	251	.uartclk = IXP4XX_UART_XTAL,
	252	},
	253	{
	254	.mapbase = IXP4XX_UART2_BASE_PHYS,
	255	.membase = (char __iomem *)IXP4XX_UART2_BASE_VIRT +
	256	REG_OFFSET,
	257	.irq = IRQ_IXP4XX_UART2,
	258	.flags = UPF_BOOT_AUTOCONF \| UPF_SKIP_TEST,
	259	.iotype = UPIO_MEM,
	260	.regshift = 2,
	261	.uartclk = IXP4XX_UART_XTAL,
	262	},
	263	{ },
	264	};
	265
	266	static struct platform_device device_uarts = {
	267	.name = "serial8250",
	268	.id = PLAT8250_DEV_PLATFORM,
	269	.dev.platform_data = uart_data,
	270	.num_resources = 2,
	271	.resource = uart_resources,
	272	};
	273
	274
	275	/* Built-in 10/100 Ethernet MAC interfaces */
f458ac47 LW	276	static struct resource eth_npeb_resources[] = {
	277	{
	278	.start = IXP4XX_EthB_BASE_PHYS,
	279	.end = IXP4XX_EthB_BASE_PHYS + 0x0fff,
	280	.flags = IORESOURCE_MEM,
	281	},
	282	};
	283
	284	static struct resource eth_npec_resources[] = {
	285	{
	286	.start = IXP4XX_EthC_BASE_PHYS,
	287	.end = IXP4XX_EthC_BASE_PHYS + 0x0fff,
	288	.flags = IORESOURCE_MEM,
	289	},
	290	};
	291
11c79740 KH	292	static struct eth_plat_info eth_plat[] = {
	293	{
	294	.phy = 0,
	295	.rxq = 3,
	296	.txreadyq = 32,
	297	}, {
	298	.phy = 1,
	299	.rxq = 4,
	300	.txreadyq = 33,
	301	}
	302	};
	303
	304	static struct platform_device device_eth_tab[] = {
	305	{
	306	.name = "ixp4xx_eth",
	307	.id = IXP4XX_ETH_NPEB,
	308	.dev.platform_data = eth_plat,
f458ac47 LW	309	.num_resources = ARRAY_SIZE(eth_npeb_resources),
f458ac47 LW	310	.resource = eth_npeb_resources,
11c79740 KH	311	}, {
	312	.name = "ixp4xx_eth",
	313	.id = IXP4XX_ETH_NPEC,
	314	.dev.platform_data = eth_plat + 1,
f458ac47 LW	315	.num_resources = ARRAY_SIZE(eth_npec_resources),
f458ac47 LW	316	.resource = eth_npec_resources,
11c79740 KH	317	}
	318	};
	319
	320
	321	/* IXP425 2 synchronous serial ports */
	322	static struct hss_plat_info hss_plat[] = {
	323	{
	324	.set_clock = hss_set_clock,
	325	.open = hss_open,
	326	.close = hss_close,
	327	.txreadyq = 34,
	328	}, {
	329	.set_clock = hss_set_clock,
	330	.open = hss_open,
	331	.close = hss_close,
	332	.txreadyq = 35,
	333	}
	334	};
	335
	336	static struct platform_device device_hss_tab[] = {
	337	{
	338	.name = "ixp4xx_hss",
	339	.id = 0,
	340	.dev.platform_data = hss_plat,
	341	}, {
	342	.name = "ixp4xx_hss",
	343	.id = 1,
	344	.dev.platform_data = hss_plat + 1,
	345	}
	346	};
	347
	348
87ba5c6a	349	static struct platform_device *device_tab[7] __initdata = {
11c79740 KH	350	&device_flash, /* index 0 */
	351	};
	352
	353	static inline u8 __init flash_readb(u8 __iomem *flash, u32 addr)
	354	{
	355	#ifdef __ARMEB__
	356	return __raw_readb(flash + addr);
	357	#else
	358	return __raw_readb(flash + (addr ^ 3));
	359	#endif
	360	}
	361
	362	static inline u16 __init flash_readw(u8 __iomem *flash, u32 addr)
	363	{
	364	#ifdef __ARMEB__
	365	return __raw_readw(flash + addr);
	366	#else
	367	return __raw_readw(flash + (addr ^ 2));
	368	#endif
	369	}
	370
	371	static void __init gmlr_init(void)
	372	{
	373	u8 __iomem *flash;
	374	int i, devices = 1; /* flash */
	375
	376	ixp4xx_sys_init();
	377
	378	if ((flash = ioremap(IXP4XX_EXP_BUS_BASE_PHYS, 0x80)) == NULL)
	379	printk(KERN_ERR "goramo-mlr: unable to access system"
	380	" configuration data\n");
	381	else {
	382	system_rev = __raw_readl(flash + CFG_REV);
	383	hw_bits = __raw_readl(flash + CFG_HW_BITS);
	384
	385	for (i = 0; i < ETH_ALEN; i++) {
	386	eth_plat[0].hwaddr[i] =
	387	flash_readb(flash, CFG_ETH0_ADDRESS + i);
	388	eth_plat[1].hwaddr[i] =
	389	flash_readb(flash, CFG_ETH1_ADDRESS + i);
	390	}
	391
	392	__raw_writew(FLASH_CMD_READ_ID, flash);
	393	system_serial_high = flash_readw(flash, FLASH_SER_OFF);
	394	system_serial_high <<= 16;
	395	system_serial_high \|= flash_readw(flash, FLASH_SER_OFF + 2);
	396	system_serial_low = flash_readw(flash, FLASH_SER_OFF + 4);
	397	system_serial_low <<= 16;
	398	system_serial_low \|= flash_readw(flash, FLASH_SER_OFF + 6);
	399	__raw_writew(FLASH_CMD_READ_ARRAY, flash);
	400
	401	iounmap(flash);
	402	}
	403
	404	switch (hw_bits & (CFG_HW_HAS_UART0 \| CFG_HW_HAS_UART1)) {
	405	case CFG_HW_HAS_UART0:
	406	memset(&uart_data[1], 0, sizeof(uart_data[1]));
	407	device_uarts.num_resources = 1;
	408	break;
	409
	410	case CFG_HW_HAS_UART1:
	411	device_uarts.dev.platform_data = &uart_data[1];
	412	device_uarts.resource = &uart_resources[1];
	413	device_uarts.num_resources = 1;
414	break;
415	}
416	if (hw_bits & (CFG_HW_HAS_UART0 \| CFG_HW_HAS_UART1))
417	device_tab[devices++] = &device_uarts; /* max index 1 */
418
419	if (hw_bits & CFG_HW_HAS_ETH0)
420	device_tab[devices++] = &device_eth_tab[0]; /* max index 2 */
421	if (hw_bits & CFG_HW_HAS_ETH1)
422	device_tab[devices++] = &device_eth_tab[1]; /* max index 3 */
423
424	if (hw_bits & CFG_HW_HAS_HSS0)
425	device_tab[devices++] = &device_hss_tab[0]; /* max index 4 */
426	if (hw_bits & CFG_HW_HAS_HSS1)
427	device_tab[devices++] = &device_hss_tab[1]; /* max index 5 */
428
c74f16b6 AB	429	hss_plat[0].timer_freq = ixp4xx_timer_freq;
	430	hss_plat[1].timer_freq = ixp4xx_timer_freq;
	431
e1a4018f KH	432	gpio_request(GPIO_SCL, "SCL/clock");
	433	gpio_request(GPIO_SDA, "SDA/data");
	434	gpio_request(GPIO_STR, "strobe");
	435	gpio_request(GPIO_HSS0_RTS_N, "HSS0 RTS");
	436	gpio_request(GPIO_HSS1_RTS_N, "HSS1 RTS");
	437	gpio_request(GPIO_HSS0_DCD_N, "HSS0 DCD");
	438	gpio_request(GPIO_HSS1_DCD_N, "HSS1 DCD");
	439
	440	gpio_direction_output(GPIO_SCL, 1);
	441	gpio_direction_output(GPIO_SDA, 1);
	442	gpio_direction_output(GPIO_STR, 0);
	443	gpio_direction_output(GPIO_HSS0_RTS_N, 1);
	444	gpio_direction_output(GPIO_HSS1_RTS_N, 1);
	445	gpio_direction_input(GPIO_HSS0_DCD_N);
	446	gpio_direction_input(GPIO_HSS1_DCD_N);
6845664a TG	447	irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N), IRQ_TYPE_EDGE_BOTH);
6845664a TG	448	irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N), IRQ_TYPE_EDGE_BOTH);
11c79740 KH	449
	450	set_control(CONTROL_HSS0_DTR_N, 1);
	451	set_control(CONTROL_HSS1_DTR_N, 1);
	452	set_control(CONTROL_EEPROM_WC_N, 1);
	453	set_control(CONTROL_PCI_RESET_N, 1);
	454	output_control();
	455
	456	msleep(1); /* Wait for PCI devices to initialize */
	457
	458	flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
	459	flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1;
	460
	461	platform_add_devices(device_tab, devices);
	462	}
	463
	464
	465	#ifdef CONFIG_PCI
	466	static void __init gmlr_pci_preinit(void)
	467	{
6845664a TG	468	irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHA), IRQ_TYPE_LEVEL_LOW);
	469	irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHB), IRQ_TYPE_LEVEL_LOW);
	470	irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_NEC), IRQ_TYPE_LEVEL_LOW);
	471	irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_MPCI), IRQ_TYPE_LEVEL_LOW);
11c79740 KH	472	ixp4xx_pci_preinit();
	473	}
	474
	475	static void __init gmlr_pci_postinit(void)
	476	{
	477	if ((hw_bits & CFG_HW_USB_PORTS) >= 2 &&
	478	(hw_bits & CFG_HW_USB_PORTS) < 5) {
	479	/* need to adjust number of USB ports on NEC chip */
	480	u32 value, addr = BIT(32 - SLOT_NEC) \| 0xE0;
	481	if (!ixp4xx_pci_read(addr, NP_CMD_CONFIGREAD, &value)) {
	482	value &= ~7;
	483	value \|= (hw_bits & CFG_HW_USB_PORTS);
	484	ixp4xx_pci_write(addr, NP_CMD_CONFIGWRITE, value);
	485	}
	486	}
	487	}
	488
d5341942	489	static int __init gmlr_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
11c79740 KH	490	{
11c79740 KH	491	switch(slot) {
8d3fdf31 KH	492	case SLOT_ETHA: return IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHA);
	493	case SLOT_ETHB: return IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHB);
	494	case SLOT_NEC: return IXP4XX_GPIO_IRQ(GPIO_IRQ_NEC);
	495	default: return IXP4XX_GPIO_IRQ(GPIO_IRQ_MPCI);
11c79740 KH	496	}
	497	}
	498
	499	static struct hw_pci gmlr_hw_pci __initdata = {
	500	.nr_controllers = 1,
c23bfc38	501	.ops = &ixp4xx_ops,
11c79740 KH	502	.preinit = gmlr_pci_preinit,
11c79740 KH	503	.postinit = gmlr_pci_postinit,
11c79740	504	.setup = ixp4xx_setup,
11c79740 KH	505	.map_irq = gmlr_map_irq,
	506	};
	507
	508	static int __init gmlr_pci_init(void)
	509	{
	510	if (machine_is_goramo_mlr() &&
	511	(hw_bits & (CFG_HW_USB_PORTS \| CFG_HW_HAS_PCI_SLOT)))
	512	pci_common_init(&gmlr_hw_pci);
	513	return 0;
	514	}
	515
	516	subsys_initcall(gmlr_pci_init);
	517	#endif /* CONFIG_PCI */
	518
	519
	520	MACHINE_START(GORAMO_MLR, "MultiLink")
	521	/* Maintainer: Krzysztof Halasa */
11c79740	522	.map_io = ixp4xx_map_io,
f449588c	523	.init_early = ixp4xx_init_early,
11c79740	524	.init_irq = ixp4xx_init_irq,
6bb27d73	525	.init_time = ixp4xx_timer_init,
e022c729	526	.atag_offset = 0x100,
11c79740	527	.init_machine = gmlr_init,
7553ee77 NP	528	#if defined(CONFIG_PCI)
	529	.dma_zone_size = SZ_64M,
	530	#endif
d1b860fb	531	.restart = ixp4xx_restart,
11c79740	532	MACHINE_END