]>
Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
a09e64fb | 2 | * arch/arm/mach-ixp4xx/include/mach/io.h |
1da177e4 LT |
3 | * |
4 | * Author: Deepak Saxena <dsaxena@plexity.net> | |
5 | * | |
450008b5 | 6 | * Copyright (C) 2002-2005 MontaVista Software, Inc. |
1da177e4 LT |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #ifndef __ASM_ARM_ARCH_IO_H | |
14 | #define __ASM_ARM_ARCH_IO_H | |
15 | ||
8e93675e RW |
16 | #include <linux/bitops.h> |
17 | ||
a09e64fb | 18 | #include <mach/hardware.h> |
1da177e4 | 19 | |
dee2b904 | 20 | #define IO_SPACE_LIMIT 0x0000ffff |
1da177e4 | 21 | |
1da177e4 LT |
22 | extern int (*ixp4xx_pci_read)(u32 addr, u32 cmd, u32* data); |
23 | extern int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data); | |
24 | ||
25 | ||
26 | /* | |
27 | * IXP4xx provides two methods of accessing PCI memory space: | |
28 | * | |
29 | * 1) A direct mapped window from 0x48000000 to 0x4bffffff (64MB). | |
30 | * To access PCI via this space, we simply ioremap() the BAR | |
31 | * into the kernel and we can use the standard read[bwl]/write[bwl] | |
32 | * macros. This is the preffered method due to speed but it | |
33 | * limits the system to just 64MB of PCI memory. This can be | |
34 | * problamatic if using video cards and other memory-heavy | |
35 | * targets. | |
36 | * | |
37 | * 2) If > 64MB of memory space is required, the IXP4xx can be configured | |
38 | * to use indirect registers to access PCI (as we do below for I/O | |
39 | * transactions). This allows for up to 128MB (0x48000000 to 0x4fffffff) | |
fd245f00 | 40 | * of memory on the bus. The disadvantage of this is that every |
1da177e4 LT |
41 | * PCI access requires three local register accesses plus a spinlock, |
42 | * but in some cases the performance hit is acceptable. In addition, | |
43 | * you cannot mmap() PCI devices in this case. | |
44 | * | |
45 | */ | |
46 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | |
47 | ||
48 | #define __mem_pci(a) (a) | |
49 | ||
50 | #else | |
51 | ||
1da177e4 LT |
52 | /* |
53 | * In the case of using indirect PCI, we simply return the actual PCI | |
54 | * address and our read/write implementation use that to drive the | |
55 | * access registers. If something outside of PCI is ioremap'd, we | |
56 | * fallback to the default. | |
57 | */ | |
28f85cd3 KH |
58 | static inline void __iomem * __indirect_ioremap(unsigned long addr, size_t size, |
59 | unsigned int mtype) | |
1da177e4 | 60 | { |
45fba084 | 61 | if((addr < PCIBIOS_MIN_MEM) || (addr > 0x4fffffff)) |
3603ab2b | 62 | return __arm_ioremap(addr, size, mtype); |
1da177e4 | 63 | |
d2936b19 | 64 | return (void __iomem *)addr; |
1da177e4 LT |
65 | } |
66 | ||
28f85cd3 | 67 | static inline void __indirect_iounmap(void __iomem *addr) |
1da177e4 | 68 | { |
d2936b19 | 69 | if ((__force u32)addr >= VMALLOC_START) |
1da177e4 LT |
70 | __iounmap(addr); |
71 | } | |
72 | ||
28f85cd3 KH |
73 | #define __arch_ioremap(a, s, f) __indirect_ioremap(a, s, f) |
74 | #define __arch_iounmap(a) __indirect_iounmap(a) | |
1da177e4 | 75 | |
28f85cd3 KH |
76 | #define writeb(v, p) __indirect_writeb(v, p) |
77 | #define writew(v, p) __indirect_writew(v, p) | |
78 | #define writel(v, p) __indirect_writel(v, p) | |
1da177e4 | 79 | |
28f85cd3 KH |
80 | #define writesb(p, v, l) __indirect_writesb(p, v, l) |
81 | #define writesw(p, v, l) __indirect_writesw(p, v, l) | |
82 | #define writesl(p, v, l) __indirect_writesl(p, v, l) | |
1da177e4 | 83 | |
28f85cd3 KH |
84 | #define readb(p) __indirect_readb(p) |
85 | #define readw(p) __indirect_readw(p) | |
86 | #define readl(p) __indirect_readl(p) | |
87 | ||
88 | #define readsb(p, v, l) __indirect_readsb(p, v, l) | |
89 | #define readsw(p, v, l) __indirect_readsw(p, v, l) | |
90 | #define readsl(p, v, l) __indirect_readsl(p, v, l) | |
91 | ||
92 | static inline void __indirect_writeb(u8 value, volatile void __iomem *p) | |
1da177e4 | 93 | { |
bfca9459 | 94 | u32 addr = (u32)p; |
1da177e4 LT |
95 | u32 n, byte_enables, data; |
96 | ||
97 | if (addr >= VMALLOC_START) { | |
98 | __raw_writeb(value, addr); | |
99 | return; | |
100 | } | |
101 | ||
102 | n = addr % 4; | |
103 | byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL; | |
104 | data = value << (8*n); | |
105 | ixp4xx_pci_write(addr, byte_enables | NP_CMD_MEMWRITE, data); | |
106 | } | |
107 | ||
28f85cd3 KH |
108 | static inline void __indirect_writesb(volatile void __iomem *bus_addr, |
109 | const u8 *vaddr, int count) | |
1da177e4 LT |
110 | { |
111 | while (count--) | |
112 | writeb(*vaddr++, bus_addr); | |
113 | } | |
114 | ||
28f85cd3 | 115 | static inline void __indirect_writew(u16 value, volatile void __iomem *p) |
1da177e4 | 116 | { |
bfca9459 | 117 | u32 addr = (u32)p; |
1da177e4 LT |
118 | u32 n, byte_enables, data; |
119 | ||
120 | if (addr >= VMALLOC_START) { | |
121 | __raw_writew(value, addr); | |
122 | return; | |
123 | } | |
124 | ||
125 | n = addr % 4; | |
126 | byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL; | |
127 | data = value << (8*n); | |
128 | ixp4xx_pci_write(addr, byte_enables | NP_CMD_MEMWRITE, data); | |
129 | } | |
130 | ||
28f85cd3 KH |
131 | static inline void __indirect_writesw(volatile void __iomem *bus_addr, |
132 | const u16 *vaddr, int count) | |
1da177e4 LT |
133 | { |
134 | while (count--) | |
135 | writew(*vaddr++, bus_addr); | |
136 | } | |
137 | ||
28f85cd3 | 138 | static inline void __indirect_writel(u32 value, volatile void __iomem *p) |
1da177e4 | 139 | { |
d2936b19 | 140 | u32 addr = (__force u32)p; |
1da177e4 | 141 | if (addr >= VMALLOC_START) { |
d2936b19 | 142 | __raw_writel(value, p); |
1da177e4 LT |
143 | return; |
144 | } | |
145 | ||
146 | ixp4xx_pci_write(addr, NP_CMD_MEMWRITE, value); | |
147 | } | |
148 | ||
28f85cd3 KH |
149 | static inline void __indirect_writesl(volatile void __iomem *bus_addr, |
150 | const u32 *vaddr, int count) | |
1da177e4 LT |
151 | { |
152 | while (count--) | |
153 | writel(*vaddr++, bus_addr); | |
154 | } | |
155 | ||
28f85cd3 | 156 | static inline unsigned char __indirect_readb(const volatile void __iomem *p) |
1da177e4 | 157 | { |
bfca9459 | 158 | u32 addr = (u32)p; |
1da177e4 LT |
159 | u32 n, byte_enables, data; |
160 | ||
161 | if (addr >= VMALLOC_START) | |
162 | return __raw_readb(addr); | |
163 | ||
164 | n = addr % 4; | |
165 | byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL; | |
166 | if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_MEMREAD, &data)) | |
167 | return 0xff; | |
168 | ||
169 | return data >> (8*n); | |
170 | } | |
171 | ||
28f85cd3 KH |
172 | static inline void __indirect_readsb(const volatile void __iomem *bus_addr, |
173 | u8 *vaddr, u32 count) | |
1da177e4 LT |
174 | { |
175 | while (count--) | |
176 | *vaddr++ = readb(bus_addr); | |
177 | } | |
178 | ||
28f85cd3 | 179 | static inline unsigned short __indirect_readw(const volatile void __iomem *p) |
1da177e4 | 180 | { |
bfca9459 | 181 | u32 addr = (u32)p; |
1da177e4 LT |
182 | u32 n, byte_enables, data; |
183 | ||
184 | if (addr >= VMALLOC_START) | |
185 | return __raw_readw(addr); | |
186 | ||
187 | n = addr % 4; | |
188 | byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL; | |
189 | if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_MEMREAD, &data)) | |
190 | return 0xffff; | |
191 | ||
192 | return data>>(8*n); | |
193 | } | |
194 | ||
28f85cd3 KH |
195 | static inline void __indirect_readsw(const volatile void __iomem *bus_addr, |
196 | u16 *vaddr, u32 count) | |
1da177e4 LT |
197 | { |
198 | while (count--) | |
199 | *vaddr++ = readw(bus_addr); | |
200 | } | |
201 | ||
28f85cd3 | 202 | static inline unsigned long __indirect_readl(const volatile void __iomem *p) |
1da177e4 | 203 | { |
d2936b19 | 204 | u32 addr = (__force u32)p; |
1da177e4 LT |
205 | u32 data; |
206 | ||
207 | if (addr >= VMALLOC_START) | |
d2936b19 | 208 | return __raw_readl(p); |
1da177e4 LT |
209 | |
210 | if (ixp4xx_pci_read(addr, NP_CMD_MEMREAD, &data)) | |
211 | return 0xffffffff; | |
212 | ||
213 | return data; | |
214 | } | |
215 | ||
28f85cd3 KH |
216 | static inline void __indirect_readsl(const volatile void __iomem *bus_addr, |
217 | u32 *vaddr, u32 count) | |
1da177e4 LT |
218 | { |
219 | while (count--) | |
220 | *vaddr++ = readl(bus_addr); | |
221 | } | |
222 | ||
223 | ||
224 | /* | |
225 | * We can use the built-in functions b/c they end up calling writeb/readb | |
226 | */ | |
227 | #define memset_io(c,v,l) _memset_io((c),(v),(l)) | |
228 | #define memcpy_fromio(a,c,l) _memcpy_fromio((a),(c),(l)) | |
229 | #define memcpy_toio(c,a,l) _memcpy_toio((c),(a),(l)) | |
230 | ||
28f85cd3 | 231 | #endif /* CONFIG_IXP4XX_INDIRECT_PCI */ |
1da177e4 | 232 | |
76bbb002 DS |
233 | #ifndef CONFIG_PCI |
234 | ||
0560cf5a | 235 | #define __io(v) __typesafe_io(v) |
76bbb002 DS |
236 | |
237 | #else | |
238 | ||
1da177e4 LT |
239 | /* |
240 | * IXP4xx does not have a transparent cpu -> PCI I/O translation | |
241 | * window. Instead, it has a set of registers that must be tweaked | |
242 | * with the proper byte lanes, command types, and address for the | |
243 | * transaction. This means that we need to override the default | |
244 | * I/O functions. | |
245 | */ | |
246 | #define outb(p, v) __ixp4xx_outb(p, v) | |
247 | #define outw(p, v) __ixp4xx_outw(p, v) | |
248 | #define outl(p, v) __ixp4xx_outl(p, v) | |
249 | ||
250 | #define outsb(p, v, l) __ixp4xx_outsb(p, v, l) | |
251 | #define outsw(p, v, l) __ixp4xx_outsw(p, v, l) | |
252 | #define outsl(p, v, l) __ixp4xx_outsl(p, v, l) | |
253 | ||
254 | #define inb(p) __ixp4xx_inb(p) | |
255 | #define inw(p) __ixp4xx_inw(p) | |
256 | #define inl(p) __ixp4xx_inl(p) | |
257 | ||
258 | #define insb(p, v, l) __ixp4xx_insb(p, v, l) | |
259 | #define insw(p, v, l) __ixp4xx_insw(p, v, l) | |
260 | #define insl(p, v, l) __ixp4xx_insl(p, v, l) | |
261 | ||
262 | ||
263 | static inline void | |
264 | __ixp4xx_outb(u8 value, u32 addr) | |
265 | { | |
266 | u32 n, byte_enables, data; | |
267 | n = addr % 4; | |
268 | byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL; | |
269 | data = value << (8*n); | |
270 | ixp4xx_pci_write(addr, byte_enables | NP_CMD_IOWRITE, data); | |
271 | } | |
272 | ||
273 | static inline void | |
274 | __ixp4xx_outsb(u32 io_addr, const u8 *vaddr, u32 count) | |
275 | { | |
276 | while (count--) | |
277 | outb(*vaddr++, io_addr); | |
278 | } | |
279 | ||
280 | static inline void | |
281 | __ixp4xx_outw(u16 value, u32 addr) | |
282 | { | |
283 | u32 n, byte_enables, data; | |
284 | n = addr % 4; | |
285 | byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL; | |
286 | data = value << (8*n); | |
287 | ixp4xx_pci_write(addr, byte_enables | NP_CMD_IOWRITE, data); | |
288 | } | |
289 | ||
290 | static inline void | |
291 | __ixp4xx_outsw(u32 io_addr, const u16 *vaddr, u32 count) | |
292 | { | |
293 | while (count--) | |
294 | outw(cpu_to_le16(*vaddr++), io_addr); | |
295 | } | |
296 | ||
297 | static inline void | |
298 | __ixp4xx_outl(u32 value, u32 addr) | |
299 | { | |
300 | ixp4xx_pci_write(addr, NP_CMD_IOWRITE, value); | |
301 | } | |
302 | ||
303 | static inline void | |
304 | __ixp4xx_outsl(u32 io_addr, const u32 *vaddr, u32 count) | |
305 | { | |
306 | while (count--) | |
9f2c9492 | 307 | outl(cpu_to_le32(*vaddr++), io_addr); |
1da177e4 LT |
308 | } |
309 | ||
310 | static inline u8 | |
311 | __ixp4xx_inb(u32 addr) | |
312 | { | |
313 | u32 n, byte_enables, data; | |
314 | n = addr % 4; | |
315 | byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL; | |
316 | if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_IOREAD, &data)) | |
317 | return 0xff; | |
318 | ||
319 | return data >> (8*n); | |
320 | } | |
321 | ||
322 | static inline void | |
323 | __ixp4xx_insb(u32 io_addr, u8 *vaddr, u32 count) | |
324 | { | |
325 | while (count--) | |
326 | *vaddr++ = inb(io_addr); | |
327 | } | |
328 | ||
329 | static inline u16 | |
330 | __ixp4xx_inw(u32 addr) | |
331 | { | |
332 | u32 n, byte_enables, data; | |
333 | n = addr % 4; | |
334 | byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL; | |
335 | if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_IOREAD, &data)) | |
336 | return 0xffff; | |
337 | ||
338 | return data>>(8*n); | |
339 | } | |
340 | ||
341 | static inline void | |
342 | __ixp4xx_insw(u32 io_addr, u16 *vaddr, u32 count) | |
343 | { | |
344 | while (count--) | |
345 | *vaddr++ = le16_to_cpu(inw(io_addr)); | |
346 | } | |
347 | ||
348 | static inline u32 | |
349 | __ixp4xx_inl(u32 addr) | |
350 | { | |
351 | u32 data; | |
352 | if (ixp4xx_pci_read(addr, NP_CMD_IOREAD, &data)) | |
353 | return 0xffffffff; | |
354 | ||
355 | return data; | |
356 | } | |
357 | ||
358 | static inline void | |
359 | __ixp4xx_insl(u32 io_addr, u32 *vaddr, u32 count) | |
360 | { | |
361 | while (count--) | |
9f2c9492 | 362 | *vaddr++ = le32_to_cpu(inl(io_addr)); |
1da177e4 LT |
363 | } |
364 | ||
147056fb DV |
365 | #define PIO_OFFSET 0x10000UL |
366 | #define PIO_MASK 0x0ffffUL | |
367 | ||
368 | #define __is_io_address(p) (((unsigned long)p >= PIO_OFFSET) && \ | |
369 | ((unsigned long)p <= (PIO_MASK + PIO_OFFSET))) | |
9f2c9492 | 370 | |
450008b5 | 371 | static inline unsigned int |
bfca9459 | 372 | __ixp4xx_ioread8(const void __iomem *addr) |
450008b5 | 373 | { |
147056fb | 374 | unsigned long port = (unsigned long __force)addr; |
450008b5 | 375 | if (__is_io_address(port)) |
9f2c9492 | 376 | return (unsigned int)__ixp4xx_inb(port & PIO_MASK); |
450008b5 DS |
377 | else |
378 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | |
147056fb | 379 | return (unsigned int)__raw_readb(port); |
450008b5 | 380 | #else |
28f85cd3 | 381 | return (unsigned int)__indirect_readb(addr); |
450008b5 DS |
382 | #endif |
383 | } | |
384 | ||
385 | static inline void | |
bfca9459 | 386 | __ixp4xx_ioread8_rep(const void __iomem *addr, void *vaddr, u32 count) |
450008b5 | 387 | { |
147056fb | 388 | unsigned long port = (unsigned long __force)addr; |
450008b5 | 389 | if (__is_io_address(port)) |
147056fb | 390 | __ixp4xx_insb(port & PIO_MASK, vaddr, count); |
450008b5 DS |
391 | else |
392 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | |
147056fb | 393 | __raw_readsb(addr, vaddr, count); |
450008b5 | 394 | #else |
28f85cd3 | 395 | __indirect_readsb(addr, vaddr, count); |
450008b5 DS |
396 | #endif |
397 | } | |
398 | ||
399 | static inline unsigned int | |
bfca9459 | 400 | __ixp4xx_ioread16(const void __iomem *addr) |
450008b5 | 401 | { |
147056fb | 402 | unsigned long port = (unsigned long __force)addr; |
450008b5 | 403 | if (__is_io_address(port)) |
147056fb | 404 | return (unsigned int)__ixp4xx_inw(port & PIO_MASK); |
450008b5 DS |
405 | else |
406 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | |
407 | return le16_to_cpu(__raw_readw((u32)port)); | |
408 | #else | |
28f85cd3 | 409 | return (unsigned int)__indirect_readw(addr); |
450008b5 DS |
410 | #endif |
411 | } | |
412 | ||
413 | static inline void | |
bfca9459 | 414 | __ixp4xx_ioread16_rep(const void __iomem *addr, void *vaddr, u32 count) |
450008b5 | 415 | { |
147056fb | 416 | unsigned long port = (unsigned long __force)addr; |
450008b5 | 417 | if (__is_io_address(port)) |
147056fb | 418 | __ixp4xx_insw(port & PIO_MASK, vaddr, count); |
450008b5 DS |
419 | else |
420 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | |
147056fb | 421 | __raw_readsw(addr, vaddr, count); |
450008b5 | 422 | #else |
28f85cd3 | 423 | __indirect_readsw(addr, vaddr, count); |
450008b5 DS |
424 | #endif |
425 | } | |
426 | ||
427 | static inline unsigned int | |
bfca9459 | 428 | __ixp4xx_ioread32(const void __iomem *addr) |
450008b5 | 429 | { |
147056fb | 430 | unsigned long port = (unsigned long __force)addr; |
450008b5 | 431 | if (__is_io_address(port)) |
147056fb | 432 | return (unsigned int)__ixp4xx_inl(port & PIO_MASK); |
450008b5 DS |
433 | else { |
434 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | |
d2936b19 | 435 | return le32_to_cpu((__force __le32)__raw_readl(addr)); |
450008b5 | 436 | #else |
28f85cd3 | 437 | return (unsigned int)__indirect_readl(addr); |
450008b5 DS |
438 | #endif |
439 | } | |
440 | } | |
441 | ||
442 | static inline void | |
bfca9459 | 443 | __ixp4xx_ioread32_rep(const void __iomem *addr, void *vaddr, u32 count) |
450008b5 | 444 | { |
147056fb | 445 | unsigned long port = (unsigned long __force)addr; |
450008b5 | 446 | if (__is_io_address(port)) |
147056fb | 447 | __ixp4xx_insl(port & PIO_MASK, vaddr, count); |
450008b5 DS |
448 | else |
449 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | |
147056fb | 450 | __raw_readsl(addr, vaddr, count); |
450008b5 | 451 | #else |
28f85cd3 | 452 | __indirect_readsl(addr, vaddr, count); |
450008b5 DS |
453 | #endif |
454 | } | |
455 | ||
456 | static inline void | |
147056fb | 457 | __ixp4xx_iowrite8(u8 value, void __iomem *addr) |
450008b5 | 458 | { |
147056fb | 459 | unsigned long port = (unsigned long __force)addr; |
450008b5 | 460 | if (__is_io_address(port)) |
147056fb | 461 | __ixp4xx_outb(value, port & PIO_MASK); |
450008b5 DS |
462 | else |
463 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | |
147056fb | 464 | __raw_writeb(value, port); |
450008b5 | 465 | #else |
28f85cd3 | 466 | __indirect_writeb(value, addr); |
450008b5 DS |
467 | #endif |
468 | } | |
469 | ||
470 | static inline void | |
147056fb | 471 | __ixp4xx_iowrite8_rep(void __iomem *addr, const void *vaddr, u32 count) |
450008b5 | 472 | { |
147056fb | 473 | unsigned long port = (unsigned long __force)addr; |
450008b5 | 474 | if (__is_io_address(port)) |
147056fb DV |
475 | __ixp4xx_outsb(port & PIO_MASK, vaddr, count); |
476 | else | |
450008b5 | 477 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI |
147056fb | 478 | __raw_writesb(addr, vaddr, count); |
450008b5 | 479 | #else |
28f85cd3 | 480 | __indirect_writesb(addr, vaddr, count); |
450008b5 DS |
481 | #endif |
482 | } | |
483 | ||
484 | static inline void | |
147056fb | 485 | __ixp4xx_iowrite16(u16 value, void __iomem *addr) |
450008b5 | 486 | { |
147056fb | 487 | unsigned long port = (unsigned long __force)addr; |
450008b5 | 488 | if (__is_io_address(port)) |
147056fb | 489 | __ixp4xx_outw(value, port & PIO_MASK); |
450008b5 DS |
490 | else |
491 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | |
147056fb | 492 | __raw_writew(cpu_to_le16(value), addr); |
450008b5 | 493 | #else |
28f85cd3 | 494 | __indirect_writew(value, addr); |
450008b5 DS |
495 | #endif |
496 | } | |
497 | ||
498 | static inline void | |
147056fb | 499 | __ixp4xx_iowrite16_rep(void __iomem *addr, const void *vaddr, u32 count) |
450008b5 | 500 | { |
147056fb | 501 | unsigned long port = (unsigned long __force)addr; |
450008b5 | 502 | if (__is_io_address(port)) |
147056fb DV |
503 | __ixp4xx_outsw(port & PIO_MASK, vaddr, count); |
504 | else | |
450008b5 | 505 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI |
147056fb | 506 | __raw_writesw(addr, vaddr, count); |
450008b5 | 507 | #else |
28f85cd3 | 508 | __indirect_writesw(addr, vaddr, count); |
450008b5 DS |
509 | #endif |
510 | } | |
511 | ||
512 | static inline void | |
147056fb | 513 | __ixp4xx_iowrite32(u32 value, void __iomem *addr) |
450008b5 | 514 | { |
147056fb | 515 | unsigned long port = (unsigned long __force)addr; |
450008b5 | 516 | if (__is_io_address(port)) |
147056fb | 517 | __ixp4xx_outl(value, port & PIO_MASK); |
450008b5 DS |
518 | else |
519 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | |
d2936b19 | 520 | __raw_writel((u32 __force)cpu_to_le32(value), addr); |
450008b5 | 521 | #else |
28f85cd3 | 522 | __indirect_writel(value, addr); |
450008b5 DS |
523 | #endif |
524 | } | |
525 | ||
526 | static inline void | |
147056fb | 527 | __ixp4xx_iowrite32_rep(void __iomem *addr, const void *vaddr, u32 count) |
450008b5 | 528 | { |
147056fb | 529 | unsigned long port = (unsigned long __force)addr; |
450008b5 | 530 | if (__is_io_address(port)) |
147056fb DV |
531 | __ixp4xx_outsl(port & PIO_MASK, vaddr, count); |
532 | else | |
450008b5 | 533 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI |
147056fb | 534 | __raw_writesl(addr, vaddr, count); |
450008b5 | 535 | #else |
28f85cd3 | 536 | __indirect_writesl(addr, vaddr, count); |
450008b5 DS |
537 | #endif |
538 | } | |
539 | ||
540 | #define ioread8(p) __ixp4xx_ioread8(p) | |
541 | #define ioread16(p) __ixp4xx_ioread16(p) | |
542 | #define ioread32(p) __ixp4xx_ioread32(p) | |
543 | ||
544 | #define ioread8_rep(p, v, c) __ixp4xx_ioread8_rep(p, v, c) | |
545 | #define ioread16_rep(p, v, c) __ixp4xx_ioread16_rep(p, v, c) | |
546 | #define ioread32_rep(p, v, c) __ixp4xx_ioread32_rep(p, v, c) | |
547 | ||
548 | #define iowrite8(v,p) __ixp4xx_iowrite8(v,p) | |
549 | #define iowrite16(v,p) __ixp4xx_iowrite16(v,p) | |
550 | #define iowrite32(v,p) __ixp4xx_iowrite32(v,p) | |
551 | ||
552 | #define iowrite8_rep(p, v, c) __ixp4xx_iowrite8_rep(p, v, c) | |
553 | #define iowrite16_rep(p, v, c) __ixp4xx_iowrite16_rep(p, v, c) | |
554 | #define iowrite32_rep(p, v, c) __ixp4xx_iowrite32_rep(p, v, c) | |
555 | ||
147056fb | 556 | #define ioport_map(port, nr) ((void __iomem*)(port + PIO_OFFSET)) |
450008b5 | 557 | #define ioport_unmap(addr) |
76bbb002 | 558 | #endif // !CONFIG_PCI |
1da177e4 LT |
559 | |
560 | #endif // __ASM_ARM_ARCH_IO_H | |
561 |