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Commit | Line | Data |
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1da177e4 | 1 | /* |
a09e64fb | 2 | * arch/arm/mach-ixp4xx/include/mach/io.h |
1da177e4 LT |
3 | * |
4 | * Author: Deepak Saxena <dsaxena@plexity.net> | |
5 | * | |
450008b5 | 6 | * Copyright (C) 2002-2005 MontaVista Software, Inc. |
1da177e4 LT |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #ifndef __ASM_ARM_ARCH_IO_H | |
14 | #define __ASM_ARM_ARCH_IO_H | |
15 | ||
8e93675e RW |
16 | #include <linux/bitops.h> |
17 | ||
a09e64fb | 18 | #include <mach/hardware.h> |
1da177e4 | 19 | |
1da177e4 LT |
20 | extern int (*ixp4xx_pci_read)(u32 addr, u32 cmd, u32* data); |
21 | extern int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data); | |
22 | ||
23 | ||
24 | /* | |
25 | * IXP4xx provides two methods of accessing PCI memory space: | |
26 | * | |
ed5b9fa0 | 27 | * 1) A direct mapped window from 0x48000000 to 0x4BFFFFFF (64MB). |
1da177e4 LT |
28 | * To access PCI via this space, we simply ioremap() the BAR |
29 | * into the kernel and we can use the standard read[bwl]/write[bwl] | |
30 | * macros. This is the preffered method due to speed but it | |
ed5b9fa0 KH |
31 | * limits the system to just 64MB of PCI memory. This can be |
32 | * problematic if using video cards and other memory-heavy targets. | |
1da177e4 | 33 | * |
ed5b9fa0 KH |
34 | * 2) If > 64MB of memory space is required, the IXP4xx can use indirect |
35 | * registers to access the whole 4 GB of PCI memory space (as we do below | |
36 | * for I/O transactions). This allows currently for up to 1 GB (0x10000000 | |
37 | * to 0x4FFFFFFF) of memory on the bus. The disadvantage of this is that | |
38 | * every PCI access requires three local register accesses plus a spinlock, | |
39 | * but in some cases the performance hit is acceptable. In addition, you | |
40 | * cannot mmap() PCI devices in this case. | |
1da177e4 LT |
41 | */ |
42 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | |
43 | ||
44 | #define __mem_pci(a) (a) | |
45 | ||
46 | #else | |
47 | ||
1da177e4 LT |
48 | /* |
49 | * In the case of using indirect PCI, we simply return the actual PCI | |
50 | * address and our read/write implementation use that to drive the | |
51 | * access registers. If something outside of PCI is ioremap'd, we | |
52 | * fallback to the default. | |
53 | */ | |
cba36222 KH |
54 | |
55 | static inline int is_pci_memory(u32 addr) | |
56 | { | |
57 | return (addr >= PCIBIOS_MIN_MEM) && (addr <= 0x4FFFFFFF); | |
58 | } | |
59 | ||
28f85cd3 KH |
60 | #define writeb(v, p) __indirect_writeb(v, p) |
61 | #define writew(v, p) __indirect_writew(v, p) | |
62 | #define writel(v, p) __indirect_writel(v, p) | |
1da177e4 | 63 | |
28f85cd3 KH |
64 | #define writesb(p, v, l) __indirect_writesb(p, v, l) |
65 | #define writesw(p, v, l) __indirect_writesw(p, v, l) | |
66 | #define writesl(p, v, l) __indirect_writesl(p, v, l) | |
1da177e4 | 67 | |
28f85cd3 KH |
68 | #define readb(p) __indirect_readb(p) |
69 | #define readw(p) __indirect_readw(p) | |
70 | #define readl(p) __indirect_readl(p) | |
71 | ||
72 | #define readsb(p, v, l) __indirect_readsb(p, v, l) | |
73 | #define readsw(p, v, l) __indirect_readsw(p, v, l) | |
74 | #define readsl(p, v, l) __indirect_readsl(p, v, l) | |
75 | ||
76 | static inline void __indirect_writeb(u8 value, volatile void __iomem *p) | |
1da177e4 | 77 | { |
bfca9459 | 78 | u32 addr = (u32)p; |
1da177e4 LT |
79 | u32 n, byte_enables, data; |
80 | ||
cba36222 | 81 | if (!is_pci_memory(addr)) { |
1da177e4 LT |
82 | __raw_writeb(value, addr); |
83 | return; | |
84 | } | |
85 | ||
86 | n = addr % 4; | |
87 | byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL; | |
88 | data = value << (8*n); | |
89 | ixp4xx_pci_write(addr, byte_enables | NP_CMD_MEMWRITE, data); | |
90 | } | |
91 | ||
28f85cd3 KH |
92 | static inline void __indirect_writesb(volatile void __iomem *bus_addr, |
93 | const u8 *vaddr, int count) | |
1da177e4 LT |
94 | { |
95 | while (count--) | |
96 | writeb(*vaddr++, bus_addr); | |
97 | } | |
98 | ||
28f85cd3 | 99 | static inline void __indirect_writew(u16 value, volatile void __iomem *p) |
1da177e4 | 100 | { |
bfca9459 | 101 | u32 addr = (u32)p; |
1da177e4 LT |
102 | u32 n, byte_enables, data; |
103 | ||
cba36222 | 104 | if (!is_pci_memory(addr)) { |
1da177e4 LT |
105 | __raw_writew(value, addr); |
106 | return; | |
107 | } | |
108 | ||
109 | n = addr % 4; | |
110 | byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL; | |
111 | data = value << (8*n); | |
112 | ixp4xx_pci_write(addr, byte_enables | NP_CMD_MEMWRITE, data); | |
113 | } | |
114 | ||
28f85cd3 KH |
115 | static inline void __indirect_writesw(volatile void __iomem *bus_addr, |
116 | const u16 *vaddr, int count) | |
1da177e4 LT |
117 | { |
118 | while (count--) | |
119 | writew(*vaddr++, bus_addr); | |
120 | } | |
121 | ||
28f85cd3 | 122 | static inline void __indirect_writel(u32 value, volatile void __iomem *p) |
1da177e4 | 123 | { |
d2936b19 | 124 | u32 addr = (__force u32)p; |
cba36222 KH |
125 | |
126 | if (!is_pci_memory(addr)) { | |
d2936b19 | 127 | __raw_writel(value, p); |
1da177e4 LT |
128 | return; |
129 | } | |
130 | ||
131 | ixp4xx_pci_write(addr, NP_CMD_MEMWRITE, value); | |
132 | } | |
133 | ||
28f85cd3 KH |
134 | static inline void __indirect_writesl(volatile void __iomem *bus_addr, |
135 | const u32 *vaddr, int count) | |
1da177e4 LT |
136 | { |
137 | while (count--) | |
138 | writel(*vaddr++, bus_addr); | |
139 | } | |
140 | ||
28f85cd3 | 141 | static inline unsigned char __indirect_readb(const volatile void __iomem *p) |
1da177e4 | 142 | { |
bfca9459 | 143 | u32 addr = (u32)p; |
1da177e4 LT |
144 | u32 n, byte_enables, data; |
145 | ||
cba36222 | 146 | if (!is_pci_memory(addr)) |
1da177e4 LT |
147 | return __raw_readb(addr); |
148 | ||
149 | n = addr % 4; | |
150 | byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL; | |
151 | if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_MEMREAD, &data)) | |
152 | return 0xff; | |
153 | ||
154 | return data >> (8*n); | |
155 | } | |
156 | ||
28f85cd3 KH |
157 | static inline void __indirect_readsb(const volatile void __iomem *bus_addr, |
158 | u8 *vaddr, u32 count) | |
1da177e4 LT |
159 | { |
160 | while (count--) | |
161 | *vaddr++ = readb(bus_addr); | |
162 | } | |
163 | ||
28f85cd3 | 164 | static inline unsigned short __indirect_readw(const volatile void __iomem *p) |
1da177e4 | 165 | { |
bfca9459 | 166 | u32 addr = (u32)p; |
1da177e4 LT |
167 | u32 n, byte_enables, data; |
168 | ||
cba36222 | 169 | if (!is_pci_memory(addr)) |
1da177e4 LT |
170 | return __raw_readw(addr); |
171 | ||
172 | n = addr % 4; | |
173 | byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL; | |
174 | if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_MEMREAD, &data)) | |
175 | return 0xffff; | |
176 | ||
177 | return data>>(8*n); | |
178 | } | |
179 | ||
28f85cd3 KH |
180 | static inline void __indirect_readsw(const volatile void __iomem *bus_addr, |
181 | u16 *vaddr, u32 count) | |
1da177e4 LT |
182 | { |
183 | while (count--) | |
184 | *vaddr++ = readw(bus_addr); | |
185 | } | |
186 | ||
28f85cd3 | 187 | static inline unsigned long __indirect_readl(const volatile void __iomem *p) |
1da177e4 | 188 | { |
d2936b19 | 189 | u32 addr = (__force u32)p; |
1da177e4 LT |
190 | u32 data; |
191 | ||
cba36222 | 192 | if (!is_pci_memory(addr)) |
d2936b19 | 193 | return __raw_readl(p); |
1da177e4 LT |
194 | |
195 | if (ixp4xx_pci_read(addr, NP_CMD_MEMREAD, &data)) | |
196 | return 0xffffffff; | |
197 | ||
198 | return data; | |
199 | } | |
200 | ||
28f85cd3 KH |
201 | static inline void __indirect_readsl(const volatile void __iomem *bus_addr, |
202 | u32 *vaddr, u32 count) | |
1da177e4 LT |
203 | { |
204 | while (count--) | |
205 | *vaddr++ = readl(bus_addr); | |
206 | } | |
207 | ||
208 | ||
209 | /* | |
210 | * We can use the built-in functions b/c they end up calling writeb/readb | |
211 | */ | |
212 | #define memset_io(c,v,l) _memset_io((c),(v),(l)) | |
213 | #define memcpy_fromio(a,c,l) _memcpy_fromio((a),(c),(l)) | |
214 | #define memcpy_toio(c,a,l) _memcpy_toio((c),(a),(l)) | |
215 | ||
28f85cd3 | 216 | #endif /* CONFIG_IXP4XX_INDIRECT_PCI */ |
1da177e4 | 217 | |
76bbb002 DS |
218 | #ifndef CONFIG_PCI |
219 | ||
0560cf5a | 220 | #define __io(v) __typesafe_io(v) |
76bbb002 DS |
221 | |
222 | #else | |
223 | ||
1da177e4 LT |
224 | /* |
225 | * IXP4xx does not have a transparent cpu -> PCI I/O translation | |
226 | * window. Instead, it has a set of registers that must be tweaked | |
227 | * with the proper byte lanes, command types, and address for the | |
228 | * transaction. This means that we need to override the default | |
229 | * I/O functions. | |
230 | */ | |
1da177e4 | 231 | |
58e570d1 | 232 | static inline void outb(u8 value, u32 addr) |
1da177e4 LT |
233 | { |
234 | u32 n, byte_enables, data; | |
235 | n = addr % 4; | |
236 | byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL; | |
237 | data = value << (8*n); | |
238 | ixp4xx_pci_write(addr, byte_enables | NP_CMD_IOWRITE, data); | |
239 | } | |
240 | ||
58e570d1 | 241 | static inline void outsb(u32 io_addr, const u8 *vaddr, u32 count) |
1da177e4 LT |
242 | { |
243 | while (count--) | |
244 | outb(*vaddr++, io_addr); | |
245 | } | |
246 | ||
58e570d1 | 247 | static inline void outw(u16 value, u32 addr) |
1da177e4 LT |
248 | { |
249 | u32 n, byte_enables, data; | |
250 | n = addr % 4; | |
251 | byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL; | |
252 | data = value << (8*n); | |
253 | ixp4xx_pci_write(addr, byte_enables | NP_CMD_IOWRITE, data); | |
254 | } | |
255 | ||
58e570d1 | 256 | static inline void outsw(u32 io_addr, const u16 *vaddr, u32 count) |
1da177e4 LT |
257 | { |
258 | while (count--) | |
259 | outw(cpu_to_le16(*vaddr++), io_addr); | |
260 | } | |
261 | ||
58e570d1 | 262 | static inline void outl(u32 value, u32 addr) |
1da177e4 LT |
263 | { |
264 | ixp4xx_pci_write(addr, NP_CMD_IOWRITE, value); | |
265 | } | |
266 | ||
58e570d1 | 267 | static inline void outsl(u32 io_addr, const u32 *vaddr, u32 count) |
1da177e4 LT |
268 | { |
269 | while (count--) | |
9f2c9492 | 270 | outl(cpu_to_le32(*vaddr++), io_addr); |
1da177e4 LT |
271 | } |
272 | ||
58e570d1 | 273 | static inline u8 inb(u32 addr) |
1da177e4 LT |
274 | { |
275 | u32 n, byte_enables, data; | |
276 | n = addr % 4; | |
277 | byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL; | |
278 | if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_IOREAD, &data)) | |
279 | return 0xff; | |
280 | ||
281 | return data >> (8*n); | |
282 | } | |
283 | ||
58e570d1 | 284 | static inline void insb(u32 io_addr, u8 *vaddr, u32 count) |
1da177e4 LT |
285 | { |
286 | while (count--) | |
287 | *vaddr++ = inb(io_addr); | |
288 | } | |
289 | ||
58e570d1 | 290 | static inline u16 inw(u32 addr) |
1da177e4 LT |
291 | { |
292 | u32 n, byte_enables, data; | |
293 | n = addr % 4; | |
294 | byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL; | |
295 | if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_IOREAD, &data)) | |
296 | return 0xffff; | |
297 | ||
298 | return data>>(8*n); | |
299 | } | |
300 | ||
58e570d1 | 301 | static inline void insw(u32 io_addr, u16 *vaddr, u32 count) |
1da177e4 LT |
302 | { |
303 | while (count--) | |
304 | *vaddr++ = le16_to_cpu(inw(io_addr)); | |
305 | } | |
306 | ||
58e570d1 | 307 | static inline u32 inl(u32 addr) |
1da177e4 LT |
308 | { |
309 | u32 data; | |
310 | if (ixp4xx_pci_read(addr, NP_CMD_IOREAD, &data)) | |
311 | return 0xffffffff; | |
312 | ||
313 | return data; | |
314 | } | |
315 | ||
58e570d1 | 316 | static inline void insl(u32 io_addr, u32 *vaddr, u32 count) |
1da177e4 LT |
317 | { |
318 | while (count--) | |
9f2c9492 | 319 | *vaddr++ = le32_to_cpu(inl(io_addr)); |
1da177e4 LT |
320 | } |
321 | ||
147056fb DV |
322 | #define PIO_OFFSET 0x10000UL |
323 | #define PIO_MASK 0x0ffffUL | |
324 | ||
325 | #define __is_io_address(p) (((unsigned long)p >= PIO_OFFSET) && \ | |
326 | ((unsigned long)p <= (PIO_MASK + PIO_OFFSET))) | |
9f2c9492 | 327 | |
58e570d1 KH |
328 | #define ioread8(p) ioread8(p) |
329 | static inline unsigned int ioread8(const void __iomem *addr) | |
450008b5 | 330 | { |
147056fb | 331 | unsigned long port = (unsigned long __force)addr; |
450008b5 | 332 | if (__is_io_address(port)) |
58e570d1 | 333 | return (unsigned int)inb(port & PIO_MASK); |
450008b5 DS |
334 | else |
335 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | |
59c29017 | 336 | return (unsigned int)__raw_readb(addr); |
450008b5 | 337 | #else |
28f85cd3 | 338 | return (unsigned int)__indirect_readb(addr); |
450008b5 DS |
339 | #endif |
340 | } | |
341 | ||
58e570d1 KH |
342 | #define ioread8_rep(p, v, c) ioread8_rep(p, v, c) |
343 | static inline void ioread8_rep(const void __iomem *addr, void *vaddr, u32 count) | |
450008b5 | 344 | { |
147056fb | 345 | unsigned long port = (unsigned long __force)addr; |
450008b5 | 346 | if (__is_io_address(port)) |
58e570d1 | 347 | insb(port & PIO_MASK, vaddr, count); |
450008b5 DS |
348 | else |
349 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | |
147056fb | 350 | __raw_readsb(addr, vaddr, count); |
450008b5 | 351 | #else |
28f85cd3 | 352 | __indirect_readsb(addr, vaddr, count); |
450008b5 DS |
353 | #endif |
354 | } | |
355 | ||
58e570d1 KH |
356 | #define ioread16(p) ioread16(p) |
357 | static inline unsigned int ioread16(const void __iomem *addr) | |
450008b5 | 358 | { |
147056fb | 359 | unsigned long port = (unsigned long __force)addr; |
450008b5 | 360 | if (__is_io_address(port)) |
58e570d1 | 361 | return (unsigned int)inw(port & PIO_MASK); |
450008b5 DS |
362 | else |
363 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | |
59c29017 | 364 | return le16_to_cpu((__force __le16)__raw_readw(addr)); |
450008b5 | 365 | #else |
28f85cd3 | 366 | return (unsigned int)__indirect_readw(addr); |
450008b5 DS |
367 | #endif |
368 | } | |
369 | ||
58e570d1 KH |
370 | #define ioread16_rep(p, v, c) ioread16_rep(p, v, c) |
371 | static inline void ioread16_rep(const void __iomem *addr, void *vaddr, | |
372 | u32 count) | |
450008b5 | 373 | { |
147056fb | 374 | unsigned long port = (unsigned long __force)addr; |
450008b5 | 375 | if (__is_io_address(port)) |
58e570d1 | 376 | insw(port & PIO_MASK, vaddr, count); |
450008b5 DS |
377 | else |
378 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | |
147056fb | 379 | __raw_readsw(addr, vaddr, count); |
450008b5 | 380 | #else |
28f85cd3 | 381 | __indirect_readsw(addr, vaddr, count); |
450008b5 DS |
382 | #endif |
383 | } | |
384 | ||
58e570d1 KH |
385 | #define ioread32(p) ioread32(p) |
386 | static inline unsigned int ioread32(const void __iomem *addr) | |
450008b5 | 387 | { |
147056fb | 388 | unsigned long port = (unsigned long __force)addr; |
450008b5 | 389 | if (__is_io_address(port)) |
58e570d1 | 390 | return (unsigned int)inl(port & PIO_MASK); |
450008b5 DS |
391 | else { |
392 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | |
d2936b19 | 393 | return le32_to_cpu((__force __le32)__raw_readl(addr)); |
450008b5 | 394 | #else |
28f85cd3 | 395 | return (unsigned int)__indirect_readl(addr); |
450008b5 DS |
396 | #endif |
397 | } | |
398 | } | |
399 | ||
58e570d1 KH |
400 | #define ioread32_rep(p, v, c) ioread32_rep(p, v, c) |
401 | static inline void ioread32_rep(const void __iomem *addr, void *vaddr, | |
402 | u32 count) | |
450008b5 | 403 | { |
147056fb | 404 | unsigned long port = (unsigned long __force)addr; |
450008b5 | 405 | if (__is_io_address(port)) |
58e570d1 | 406 | insl(port & PIO_MASK, vaddr, count); |
450008b5 DS |
407 | else |
408 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | |
147056fb | 409 | __raw_readsl(addr, vaddr, count); |
450008b5 | 410 | #else |
28f85cd3 | 411 | __indirect_readsl(addr, vaddr, count); |
450008b5 DS |
412 | #endif |
413 | } | |
414 | ||
58e570d1 KH |
415 | #define iowrite8(v, p) iowrite8(v, p) |
416 | static inline void iowrite8(u8 value, void __iomem *addr) | |
450008b5 | 417 | { |
147056fb | 418 | unsigned long port = (unsigned long __force)addr; |
450008b5 | 419 | if (__is_io_address(port)) |
58e570d1 | 420 | outb(value, port & PIO_MASK); |
450008b5 DS |
421 | else |
422 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | |
59c29017 | 423 | __raw_writeb(value, addr); |
450008b5 | 424 | #else |
28f85cd3 | 425 | __indirect_writeb(value, addr); |
450008b5 DS |
426 | #endif |
427 | } | |
428 | ||
58e570d1 KH |
429 | #define iowrite8_rep(p, v, c) iowrite8_rep(p, v, c) |
430 | static inline void iowrite8_rep(void __iomem *addr, const void *vaddr, | |
431 | u32 count) | |
450008b5 | 432 | { |
147056fb | 433 | unsigned long port = (unsigned long __force)addr; |
450008b5 | 434 | if (__is_io_address(port)) |
58e570d1 | 435 | outsb(port & PIO_MASK, vaddr, count); |
147056fb | 436 | else |
450008b5 | 437 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI |
147056fb | 438 | __raw_writesb(addr, vaddr, count); |
450008b5 | 439 | #else |
28f85cd3 | 440 | __indirect_writesb(addr, vaddr, count); |
450008b5 DS |
441 | #endif |
442 | } | |
443 | ||
58e570d1 KH |
444 | #define iowrite16(v, p) iowrite16(v, p) |
445 | static inline void iowrite16(u16 value, void __iomem *addr) | |
450008b5 | 446 | { |
147056fb | 447 | unsigned long port = (unsigned long __force)addr; |
450008b5 | 448 | if (__is_io_address(port)) |
58e570d1 | 449 | outw(value, port & PIO_MASK); |
450008b5 DS |
450 | else |
451 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | |
147056fb | 452 | __raw_writew(cpu_to_le16(value), addr); |
450008b5 | 453 | #else |
28f85cd3 | 454 | __indirect_writew(value, addr); |
450008b5 DS |
455 | #endif |
456 | } | |
457 | ||
58e570d1 KH |
458 | #define iowrite16_rep(p, v, c) iowrite16_rep(p, v, c) |
459 | static inline void iowrite16_rep(void __iomem *addr, const void *vaddr, | |
460 | u32 count) | |
450008b5 | 461 | { |
147056fb | 462 | unsigned long port = (unsigned long __force)addr; |
450008b5 | 463 | if (__is_io_address(port)) |
58e570d1 | 464 | outsw(port & PIO_MASK, vaddr, count); |
147056fb | 465 | else |
450008b5 | 466 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI |
147056fb | 467 | __raw_writesw(addr, vaddr, count); |
450008b5 | 468 | #else |
28f85cd3 | 469 | __indirect_writesw(addr, vaddr, count); |
450008b5 DS |
470 | #endif |
471 | } | |
472 | ||
58e570d1 KH |
473 | #define iowrite32(v, p) iowrite32(v, p) |
474 | static inline void iowrite32(u32 value, void __iomem *addr) | |
450008b5 | 475 | { |
147056fb | 476 | unsigned long port = (unsigned long __force)addr; |
450008b5 | 477 | if (__is_io_address(port)) |
58e570d1 | 478 | outl(value, port & PIO_MASK); |
450008b5 DS |
479 | else |
480 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | |
d2936b19 | 481 | __raw_writel((u32 __force)cpu_to_le32(value), addr); |
450008b5 | 482 | #else |
28f85cd3 | 483 | __indirect_writel(value, addr); |
450008b5 DS |
484 | #endif |
485 | } | |
486 | ||
58e570d1 KH |
487 | #define iowrite32_rep(p, v, c) iowrite32_rep(p, v, c) |
488 | static inline void iowrite32_rep(void __iomem *addr, const void *vaddr, | |
489 | u32 count) | |
450008b5 | 490 | { |
147056fb | 491 | unsigned long port = (unsigned long __force)addr; |
450008b5 | 492 | if (__is_io_address(port)) |
58e570d1 | 493 | outsl(port & PIO_MASK, vaddr, count); |
147056fb | 494 | else |
450008b5 | 495 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI |
147056fb | 496 | __raw_writesl(addr, vaddr, count); |
450008b5 | 497 | #else |
28f85cd3 | 498 | __indirect_writesl(addr, vaddr, count); |
450008b5 DS |
499 | #endif |
500 | } | |
501 | ||
147056fb | 502 | #define ioport_map(port, nr) ((void __iomem*)(port + PIO_OFFSET)) |
450008b5 | 503 | #define ioport_unmap(addr) |
58e570d1 | 504 | #endif /* CONFIG_PCI */ |
1da177e4 | 505 | |
58e570d1 | 506 | #endif /* __ASM_ARM_ARCH_IO_H */ |