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Commit | Line | Data |
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1da177e4 | 1 | /* |
a09e64fb | 2 | * arch/arm/mach-ixp4xx/include/mach/io.h |
1da177e4 LT |
3 | * |
4 | * Author: Deepak Saxena <dsaxena@plexity.net> | |
5 | * | |
450008b5 | 6 | * Copyright (C) 2002-2005 MontaVista Software, Inc. |
1da177e4 LT |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #ifndef __ASM_ARM_ARCH_IO_H | |
14 | #define __ASM_ARM_ARCH_IO_H | |
15 | ||
8e93675e RW |
16 | #include <linux/bitops.h> |
17 | ||
a09e64fb | 18 | #include <mach/hardware.h> |
1da177e4 | 19 | |
1da177e4 LT |
20 | extern int (*ixp4xx_pci_read)(u32 addr, u32 cmd, u32* data); |
21 | extern int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data); | |
22 | ||
23 | ||
24 | /* | |
25 | * IXP4xx provides two methods of accessing PCI memory space: | |
26 | * | |
ed5b9fa0 | 27 | * 1) A direct mapped window from 0x48000000 to 0x4BFFFFFF (64MB). |
1da177e4 LT |
28 | * To access PCI via this space, we simply ioremap() the BAR |
29 | * into the kernel and we can use the standard read[bwl]/write[bwl] | |
30 | * macros. This is the preffered method due to speed but it | |
ed5b9fa0 KH |
31 | * limits the system to just 64MB of PCI memory. This can be |
32 | * problematic if using video cards and other memory-heavy targets. | |
1da177e4 | 33 | * |
ed5b9fa0 KH |
34 | * 2) If > 64MB of memory space is required, the IXP4xx can use indirect |
35 | * registers to access the whole 4 GB of PCI memory space (as we do below | |
36 | * for I/O transactions). This allows currently for up to 1 GB (0x10000000 | |
37 | * to 0x4FFFFFFF) of memory on the bus. The disadvantage of this is that | |
38 | * every PCI access requires three local register accesses plus a spinlock, | |
39 | * but in some cases the performance hit is acceptable. In addition, you | |
40 | * cannot mmap() PCI devices in this case. | |
1da177e4 | 41 | */ |
5621caac | 42 | #ifdef CONFIG_IXP4XX_INDIRECT_PCI |
1da177e4 | 43 | |
1da177e4 LT |
44 | /* |
45 | * In the case of using indirect PCI, we simply return the actual PCI | |
46 | * address and our read/write implementation use that to drive the | |
47 | * access registers. If something outside of PCI is ioremap'd, we | |
48 | * fallback to the default. | |
49 | */ | |
cba36222 | 50 | |
926aabde | 51 | extern unsigned long pcibios_min_mem; |
cba36222 KH |
52 | static inline int is_pci_memory(u32 addr) |
53 | { | |
926aabde | 54 | return (addr >= pcibios_min_mem) && (addr <= 0x4FFFFFFF); |
cba36222 KH |
55 | } |
56 | ||
28f85cd3 KH |
57 | #define writeb(v, p) __indirect_writeb(v, p) |
58 | #define writew(v, p) __indirect_writew(v, p) | |
59 | #define writel(v, p) __indirect_writel(v, p) | |
1da177e4 | 60 | |
e43b21cb AB |
61 | #define writeb_relaxed(v, p) __indirect_writeb(v, p) |
62 | #define writew_relaxed(v, p) __indirect_writew(v, p) | |
63 | #define writel_relaxed(v, p) __indirect_writel(v, p) | |
64 | ||
28f85cd3 KH |
65 | #define writesb(p, v, l) __indirect_writesb(p, v, l) |
66 | #define writesw(p, v, l) __indirect_writesw(p, v, l) | |
67 | #define writesl(p, v, l) __indirect_writesl(p, v, l) | |
1da177e4 | 68 | |
28f85cd3 KH |
69 | #define readb(p) __indirect_readb(p) |
70 | #define readw(p) __indirect_readw(p) | |
71 | #define readl(p) __indirect_readl(p) | |
72 | ||
e43b21cb AB |
73 | #define readb_relaxed(p) __indirect_readb(p) |
74 | #define readw_relaxed(p) __indirect_readw(p) | |
75 | #define readl_relaxed(p) __indirect_readl(p) | |
76 | ||
28f85cd3 KH |
77 | #define readsb(p, v, l) __indirect_readsb(p, v, l) |
78 | #define readsw(p, v, l) __indirect_readsw(p, v, l) | |
79 | #define readsl(p, v, l) __indirect_readsl(p, v, l) | |
80 | ||
81 | static inline void __indirect_writeb(u8 value, volatile void __iomem *p) | |
1da177e4 | 82 | { |
bfca9459 | 83 | u32 addr = (u32)p; |
1da177e4 LT |
84 | u32 n, byte_enables, data; |
85 | ||
cba36222 | 86 | if (!is_pci_memory(addr)) { |
e43b21cb | 87 | __raw_writeb(value, p); |
1da177e4 LT |
88 | return; |
89 | } | |
90 | ||
91 | n = addr % 4; | |
92 | byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL; | |
93 | data = value << (8*n); | |
94 | ixp4xx_pci_write(addr, byte_enables | NP_CMD_MEMWRITE, data); | |
95 | } | |
96 | ||
28f85cd3 | 97 | static inline void __indirect_writesb(volatile void __iomem *bus_addr, |
1f3b4d8f | 98 | const void *p, int count) |
1da177e4 | 99 | { |
1f3b4d8f AB |
100 | const u8 *vaddr = p; |
101 | ||
1da177e4 LT |
102 | while (count--) |
103 | writeb(*vaddr++, bus_addr); | |
104 | } | |
105 | ||
28f85cd3 | 106 | static inline void __indirect_writew(u16 value, volatile void __iomem *p) |
1da177e4 | 107 | { |
bfca9459 | 108 | u32 addr = (u32)p; |
1da177e4 LT |
109 | u32 n, byte_enables, data; |
110 | ||
cba36222 | 111 | if (!is_pci_memory(addr)) { |
e43b21cb | 112 | __raw_writew(value, p); |
1da177e4 LT |
113 | return; |
114 | } | |
115 | ||
116 | n = addr % 4; | |
117 | byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL; | |
118 | data = value << (8*n); | |
119 | ixp4xx_pci_write(addr, byte_enables | NP_CMD_MEMWRITE, data); | |
120 | } | |
121 | ||
28f85cd3 | 122 | static inline void __indirect_writesw(volatile void __iomem *bus_addr, |
1f3b4d8f | 123 | const void *p, int count) |
1da177e4 | 124 | { |
1f3b4d8f AB |
125 | const u16 *vaddr = p; |
126 | ||
1da177e4 LT |
127 | while (count--) |
128 | writew(*vaddr++, bus_addr); | |
129 | } | |
130 | ||
28f85cd3 | 131 | static inline void __indirect_writel(u32 value, volatile void __iomem *p) |
1da177e4 | 132 | { |
d2936b19 | 133 | u32 addr = (__force u32)p; |
cba36222 KH |
134 | |
135 | if (!is_pci_memory(addr)) { | |
d2936b19 | 136 | __raw_writel(value, p); |
1da177e4 LT |
137 | return; |
138 | } | |
139 | ||
140 | ixp4xx_pci_write(addr, NP_CMD_MEMWRITE, value); | |
141 | } | |
142 | ||
28f85cd3 | 143 | static inline void __indirect_writesl(volatile void __iomem *bus_addr, |
1f3b4d8f | 144 | const void *p, int count) |
1da177e4 | 145 | { |
1f3b4d8f | 146 | const u32 *vaddr = p; |
1da177e4 LT |
147 | while (count--) |
148 | writel(*vaddr++, bus_addr); | |
149 | } | |
150 | ||
d66e5139 | 151 | static inline u8 __indirect_readb(const volatile void __iomem *p) |
1da177e4 | 152 | { |
bfca9459 | 153 | u32 addr = (u32)p; |
1da177e4 LT |
154 | u32 n, byte_enables, data; |
155 | ||
cba36222 | 156 | if (!is_pci_memory(addr)) |
e43b21cb | 157 | return __raw_readb(p); |
1da177e4 LT |
158 | |
159 | n = addr % 4; | |
160 | byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL; | |
161 | if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_MEMREAD, &data)) | |
162 | return 0xff; | |
163 | ||
164 | return data >> (8*n); | |
165 | } | |
166 | ||
28f85cd3 | 167 | static inline void __indirect_readsb(const volatile void __iomem *bus_addr, |
1f3b4d8f | 168 | void *p, u32 count) |
1da177e4 | 169 | { |
1f3b4d8f AB |
170 | u8 *vaddr = p; |
171 | ||
1da177e4 LT |
172 | while (count--) |
173 | *vaddr++ = readb(bus_addr); | |
174 | } | |
175 | ||
d66e5139 | 176 | static inline u16 __indirect_readw(const volatile void __iomem *p) |
1da177e4 | 177 | { |
bfca9459 | 178 | u32 addr = (u32)p; |
1da177e4 LT |
179 | u32 n, byte_enables, data; |
180 | ||
cba36222 | 181 | if (!is_pci_memory(addr)) |
e43b21cb | 182 | return __raw_readw(p); |
1da177e4 LT |
183 | |
184 | n = addr % 4; | |
185 | byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL; | |
186 | if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_MEMREAD, &data)) | |
187 | return 0xffff; | |
188 | ||
189 | return data>>(8*n); | |
190 | } | |
191 | ||
28f85cd3 | 192 | static inline void __indirect_readsw(const volatile void __iomem *bus_addr, |
1f3b4d8f | 193 | void *p, u32 count) |
1da177e4 | 194 | { |
1f3b4d8f AB |
195 | u16 *vaddr = p; |
196 | ||
1da177e4 LT |
197 | while (count--) |
198 | *vaddr++ = readw(bus_addr); | |
199 | } | |
200 | ||
d66e5139 | 201 | static inline u32 __indirect_readl(const volatile void __iomem *p) |
1da177e4 | 202 | { |
d2936b19 | 203 | u32 addr = (__force u32)p; |
1da177e4 LT |
204 | u32 data; |
205 | ||
cba36222 | 206 | if (!is_pci_memory(addr)) |
d2936b19 | 207 | return __raw_readl(p); |
1da177e4 LT |
208 | |
209 | if (ixp4xx_pci_read(addr, NP_CMD_MEMREAD, &data)) | |
210 | return 0xffffffff; | |
211 | ||
212 | return data; | |
213 | } | |
214 | ||
28f85cd3 | 215 | static inline void __indirect_readsl(const volatile void __iomem *bus_addr, |
1f3b4d8f | 216 | void *p, u32 count) |
1da177e4 | 217 | { |
1f3b4d8f AB |
218 | u32 *vaddr = p; |
219 | ||
1da177e4 LT |
220 | while (count--) |
221 | *vaddr++ = readl(bus_addr); | |
222 | } | |
223 | ||
224 | ||
225 | /* | |
226 | * We can use the built-in functions b/c they end up calling writeb/readb | |
227 | */ | |
228 | #define memset_io(c,v,l) _memset_io((c),(v),(l)) | |
229 | #define memcpy_fromio(a,c,l) _memcpy_fromio((a),(c),(l)) | |
230 | #define memcpy_toio(c,a,l) _memcpy_toio((c),(a),(l)) | |
231 | ||
28f85cd3 | 232 | #endif /* CONFIG_IXP4XX_INDIRECT_PCI */ |
1da177e4 | 233 | |
76bbb002 DS |
234 | #ifndef CONFIG_PCI |
235 | ||
0560cf5a | 236 | #define __io(v) __typesafe_io(v) |
76bbb002 DS |
237 | |
238 | #else | |
239 | ||
1da177e4 LT |
240 | /* |
241 | * IXP4xx does not have a transparent cpu -> PCI I/O translation | |
242 | * window. Instead, it has a set of registers that must be tweaked | |
243 | * with the proper byte lanes, command types, and address for the | |
244 | * transaction. This means that we need to override the default | |
245 | * I/O functions. | |
246 | */ | |
1da177e4 | 247 | |
2e0fa0c9 | 248 | #define outb outb |
58e570d1 | 249 | static inline void outb(u8 value, u32 addr) |
1da177e4 LT |
250 | { |
251 | u32 n, byte_enables, data; | |
252 | n = addr % 4; | |
253 | byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL; | |
254 | data = value << (8*n); | |
255 | ixp4xx_pci_write(addr, byte_enables | NP_CMD_IOWRITE, data); | |
256 | } | |
257 | ||
2e0fa0c9 | 258 | #define outsb outsb |
1aeb3c5c | 259 | static inline void outsb(u32 io_addr, const void *p, u32 count) |
1da177e4 | 260 | { |
1aeb3c5c AB |
261 | const u8 *vaddr = p; |
262 | ||
1da177e4 LT |
263 | while (count--) |
264 | outb(*vaddr++, io_addr); | |
265 | } | |
266 | ||
2e0fa0c9 | 267 | #define outw outw |
58e570d1 | 268 | static inline void outw(u16 value, u32 addr) |
1da177e4 LT |
269 | { |
270 | u32 n, byte_enables, data; | |
271 | n = addr % 4; | |
272 | byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL; | |
273 | data = value << (8*n); | |
274 | ixp4xx_pci_write(addr, byte_enables | NP_CMD_IOWRITE, data); | |
275 | } | |
276 | ||
2e0fa0c9 | 277 | #define outsw outsw |
1aeb3c5c | 278 | static inline void outsw(u32 io_addr, const void *p, u32 count) |
1da177e4 | 279 | { |
1aeb3c5c | 280 | const u16 *vaddr = p; |
1da177e4 LT |
281 | while (count--) |
282 | outw(cpu_to_le16(*vaddr++), io_addr); | |
283 | } | |
284 | ||
2e0fa0c9 | 285 | #define outl outl |
58e570d1 | 286 | static inline void outl(u32 value, u32 addr) |
1da177e4 LT |
287 | { |
288 | ixp4xx_pci_write(addr, NP_CMD_IOWRITE, value); | |
289 | } | |
290 | ||
2e0fa0c9 | 291 | #define outsl outsl |
1aeb3c5c | 292 | static inline void outsl(u32 io_addr, const void *p, u32 count) |
1da177e4 | 293 | { |
1aeb3c5c | 294 | const u32 *vaddr = p; |
1da177e4 | 295 | while (count--) |
9f2c9492 | 296 | outl(cpu_to_le32(*vaddr++), io_addr); |
1da177e4 LT |
297 | } |
298 | ||
2e0fa0c9 | 299 | #define inb inb |
58e570d1 | 300 | static inline u8 inb(u32 addr) |
1da177e4 LT |
301 | { |
302 | u32 n, byte_enables, data; | |
303 | n = addr % 4; | |
304 | byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL; | |
305 | if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_IOREAD, &data)) | |
306 | return 0xff; | |
307 | ||
308 | return data >> (8*n); | |
309 | } | |
310 | ||
2e0fa0c9 | 311 | #define insb insb |
1aeb3c5c | 312 | static inline void insb(u32 io_addr, void *p, u32 count) |
1da177e4 | 313 | { |
1aeb3c5c | 314 | u8 *vaddr = p; |
1da177e4 LT |
315 | while (count--) |
316 | *vaddr++ = inb(io_addr); | |
317 | } | |
318 | ||
2e0fa0c9 | 319 | #define inw inw |
58e570d1 | 320 | static inline u16 inw(u32 addr) |
1da177e4 LT |
321 | { |
322 | u32 n, byte_enables, data; | |
323 | n = addr % 4; | |
324 | byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL; | |
325 | if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_IOREAD, &data)) | |
326 | return 0xffff; | |
327 | ||
328 | return data>>(8*n); | |
329 | } | |
330 | ||
2e0fa0c9 | 331 | #define insw insw |
1aeb3c5c | 332 | static inline void insw(u32 io_addr, void *p, u32 count) |
1da177e4 | 333 | { |
1aeb3c5c | 334 | u16 *vaddr = p; |
1da177e4 LT |
335 | while (count--) |
336 | *vaddr++ = le16_to_cpu(inw(io_addr)); | |
337 | } | |
338 | ||
2e0fa0c9 | 339 | #define inl inl |
58e570d1 | 340 | static inline u32 inl(u32 addr) |
1da177e4 LT |
341 | { |
342 | u32 data; | |
343 | if (ixp4xx_pci_read(addr, NP_CMD_IOREAD, &data)) | |
344 | return 0xffffffff; | |
345 | ||
346 | return data; | |
347 | } | |
348 | ||
2e0fa0c9 | 349 | #define insl insl |
1aeb3c5c | 350 | static inline void insl(u32 io_addr, void *p, u32 count) |
1da177e4 | 351 | { |
1aeb3c5c | 352 | u32 *vaddr = p; |
1da177e4 | 353 | while (count--) |
9f2c9492 | 354 | *vaddr++ = le32_to_cpu(inl(io_addr)); |
1da177e4 LT |
355 | } |
356 | ||
147056fb DV |
357 | #define PIO_OFFSET 0x10000UL |
358 | #define PIO_MASK 0x0ffffUL | |
359 | ||
360 | #define __is_io_address(p) (((unsigned long)p >= PIO_OFFSET) && \ | |
361 | ((unsigned long)p <= (PIO_MASK + PIO_OFFSET))) | |
9f2c9492 | 362 | |
58e570d1 | 363 | #define ioread8(p) ioread8(p) |
d66e5139 | 364 | static inline u8 ioread8(const void __iomem *addr) |
450008b5 | 365 | { |
147056fb | 366 | unsigned long port = (unsigned long __force)addr; |
450008b5 | 367 | if (__is_io_address(port)) |
58e570d1 | 368 | return (unsigned int)inb(port & PIO_MASK); |
450008b5 DS |
369 | else |
370 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | |
59c29017 | 371 | return (unsigned int)__raw_readb(addr); |
450008b5 | 372 | #else |
28f85cd3 | 373 | return (unsigned int)__indirect_readb(addr); |
450008b5 DS |
374 | #endif |
375 | } | |
376 | ||
58e570d1 KH |
377 | #define ioread8_rep(p, v, c) ioread8_rep(p, v, c) |
378 | static inline void ioread8_rep(const void __iomem *addr, void *vaddr, u32 count) | |
450008b5 | 379 | { |
147056fb | 380 | unsigned long port = (unsigned long __force)addr; |
450008b5 | 381 | if (__is_io_address(port)) |
58e570d1 | 382 | insb(port & PIO_MASK, vaddr, count); |
450008b5 DS |
383 | else |
384 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | |
147056fb | 385 | __raw_readsb(addr, vaddr, count); |
450008b5 | 386 | #else |
28f85cd3 | 387 | __indirect_readsb(addr, vaddr, count); |
450008b5 DS |
388 | #endif |
389 | } | |
390 | ||
58e570d1 | 391 | #define ioread16(p) ioread16(p) |
d66e5139 | 392 | static inline u16 ioread16(const void __iomem *addr) |
450008b5 | 393 | { |
147056fb | 394 | unsigned long port = (unsigned long __force)addr; |
450008b5 | 395 | if (__is_io_address(port)) |
58e570d1 | 396 | return (unsigned int)inw(port & PIO_MASK); |
450008b5 DS |
397 | else |
398 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | |
59c29017 | 399 | return le16_to_cpu((__force __le16)__raw_readw(addr)); |
450008b5 | 400 | #else |
28f85cd3 | 401 | return (unsigned int)__indirect_readw(addr); |
450008b5 DS |
402 | #endif |
403 | } | |
404 | ||
58e570d1 KH |
405 | #define ioread16_rep(p, v, c) ioread16_rep(p, v, c) |
406 | static inline void ioread16_rep(const void __iomem *addr, void *vaddr, | |
407 | u32 count) | |
450008b5 | 408 | { |
147056fb | 409 | unsigned long port = (unsigned long __force)addr; |
450008b5 | 410 | if (__is_io_address(port)) |
58e570d1 | 411 | insw(port & PIO_MASK, vaddr, count); |
450008b5 DS |
412 | else |
413 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | |
147056fb | 414 | __raw_readsw(addr, vaddr, count); |
450008b5 | 415 | #else |
28f85cd3 | 416 | __indirect_readsw(addr, vaddr, count); |
450008b5 DS |
417 | #endif |
418 | } | |
419 | ||
58e570d1 | 420 | #define ioread32(p) ioread32(p) |
d66e5139 | 421 | static inline u32 ioread32(const void __iomem *addr) |
450008b5 | 422 | { |
147056fb | 423 | unsigned long port = (unsigned long __force)addr; |
450008b5 | 424 | if (__is_io_address(port)) |
58e570d1 | 425 | return (unsigned int)inl(port & PIO_MASK); |
450008b5 DS |
426 | else { |
427 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | |
d2936b19 | 428 | return le32_to_cpu((__force __le32)__raw_readl(addr)); |
450008b5 | 429 | #else |
28f85cd3 | 430 | return (unsigned int)__indirect_readl(addr); |
450008b5 DS |
431 | #endif |
432 | } | |
433 | } | |
434 | ||
58e570d1 KH |
435 | #define ioread32_rep(p, v, c) ioread32_rep(p, v, c) |
436 | static inline void ioread32_rep(const void __iomem *addr, void *vaddr, | |
437 | u32 count) | |
450008b5 | 438 | { |
147056fb | 439 | unsigned long port = (unsigned long __force)addr; |
450008b5 | 440 | if (__is_io_address(port)) |
58e570d1 | 441 | insl(port & PIO_MASK, vaddr, count); |
450008b5 DS |
442 | else |
443 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | |
147056fb | 444 | __raw_readsl(addr, vaddr, count); |
450008b5 | 445 | #else |
28f85cd3 | 446 | __indirect_readsl(addr, vaddr, count); |
450008b5 DS |
447 | #endif |
448 | } | |
449 | ||
58e570d1 KH |
450 | #define iowrite8(v, p) iowrite8(v, p) |
451 | static inline void iowrite8(u8 value, void __iomem *addr) | |
450008b5 | 452 | { |
147056fb | 453 | unsigned long port = (unsigned long __force)addr; |
450008b5 | 454 | if (__is_io_address(port)) |
58e570d1 | 455 | outb(value, port & PIO_MASK); |
450008b5 DS |
456 | else |
457 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | |
59c29017 | 458 | __raw_writeb(value, addr); |
450008b5 | 459 | #else |
28f85cd3 | 460 | __indirect_writeb(value, addr); |
450008b5 DS |
461 | #endif |
462 | } | |
463 | ||
58e570d1 KH |
464 | #define iowrite8_rep(p, v, c) iowrite8_rep(p, v, c) |
465 | static inline void iowrite8_rep(void __iomem *addr, const void *vaddr, | |
466 | u32 count) | |
450008b5 | 467 | { |
147056fb | 468 | unsigned long port = (unsigned long __force)addr; |
450008b5 | 469 | if (__is_io_address(port)) |
58e570d1 | 470 | outsb(port & PIO_MASK, vaddr, count); |
147056fb | 471 | else |
450008b5 | 472 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI |
147056fb | 473 | __raw_writesb(addr, vaddr, count); |
450008b5 | 474 | #else |
28f85cd3 | 475 | __indirect_writesb(addr, vaddr, count); |
450008b5 DS |
476 | #endif |
477 | } | |
478 | ||
58e570d1 KH |
479 | #define iowrite16(v, p) iowrite16(v, p) |
480 | static inline void iowrite16(u16 value, void __iomem *addr) | |
450008b5 | 481 | { |
147056fb | 482 | unsigned long port = (unsigned long __force)addr; |
450008b5 | 483 | if (__is_io_address(port)) |
58e570d1 | 484 | outw(value, port & PIO_MASK); |
450008b5 DS |
485 | else |
486 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | |
147056fb | 487 | __raw_writew(cpu_to_le16(value), addr); |
450008b5 | 488 | #else |
28f85cd3 | 489 | __indirect_writew(value, addr); |
450008b5 DS |
490 | #endif |
491 | } | |
492 | ||
58e570d1 KH |
493 | #define iowrite16_rep(p, v, c) iowrite16_rep(p, v, c) |
494 | static inline void iowrite16_rep(void __iomem *addr, const void *vaddr, | |
495 | u32 count) | |
450008b5 | 496 | { |
147056fb | 497 | unsigned long port = (unsigned long __force)addr; |
450008b5 | 498 | if (__is_io_address(port)) |
58e570d1 | 499 | outsw(port & PIO_MASK, vaddr, count); |
147056fb | 500 | else |
450008b5 | 501 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI |
147056fb | 502 | __raw_writesw(addr, vaddr, count); |
450008b5 | 503 | #else |
28f85cd3 | 504 | __indirect_writesw(addr, vaddr, count); |
450008b5 DS |
505 | #endif |
506 | } | |
507 | ||
58e570d1 KH |
508 | #define iowrite32(v, p) iowrite32(v, p) |
509 | static inline void iowrite32(u32 value, void __iomem *addr) | |
450008b5 | 510 | { |
147056fb | 511 | unsigned long port = (unsigned long __force)addr; |
450008b5 | 512 | if (__is_io_address(port)) |
58e570d1 | 513 | outl(value, port & PIO_MASK); |
450008b5 DS |
514 | else |
515 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | |
d2936b19 | 516 | __raw_writel((u32 __force)cpu_to_le32(value), addr); |
450008b5 | 517 | #else |
28f85cd3 | 518 | __indirect_writel(value, addr); |
450008b5 DS |
519 | #endif |
520 | } | |
521 | ||
58e570d1 KH |
522 | #define iowrite32_rep(p, v, c) iowrite32_rep(p, v, c) |
523 | static inline void iowrite32_rep(void __iomem *addr, const void *vaddr, | |
524 | u32 count) | |
450008b5 | 525 | { |
147056fb | 526 | unsigned long port = (unsigned long __force)addr; |
450008b5 | 527 | if (__is_io_address(port)) |
58e570d1 | 528 | outsl(port & PIO_MASK, vaddr, count); |
147056fb | 529 | else |
450008b5 | 530 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI |
147056fb | 531 | __raw_writesl(addr, vaddr, count); |
450008b5 | 532 | #else |
28f85cd3 | 533 | __indirect_writesl(addr, vaddr, count); |
450008b5 DS |
534 | #endif |
535 | } | |
536 | ||
c4caa8db AB |
537 | #define ioport_map(port, nr) ioport_map(port, nr) |
538 | static inline void __iomem *ioport_map(unsigned long port, unsigned int nr) | |
539 | { | |
540 | return ((void __iomem*)((port) + PIO_OFFSET)); | |
541 | } | |
542 | #define ioport_unmap(addr) ioport_unmap(addr) | |
543 | static inline void ioport_unmap(void __iomem *addr) | |
544 | { | |
545 | } | |
58e570d1 | 546 | #endif /* CONFIG_PCI */ |
1da177e4 | 547 | |
58e570d1 | 548 | #endif /* __ASM_ARM_ARCH_IO_H */ |