[mirror_ubuntu-artful-kernel.git] / arch / arm / mach-ixp4xx / include / mach / qmgr.h

/*
 * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of version 2 of the GNU General Public License
 * as published by the Free Software Foundation.
 */

#ifndef IXP4XX_QMGR_H
#define IXP4XX_QMGR_H

#include <linux/io.h>
#include <linux/kernel.h>

#define DEBUG_QMGR	0

#define HALF_QUEUES	32
#define QUEUES		64
#define MAX_QUEUE_LENGTH 4	/* in dwords */

#define QUEUE_STAT1_EMPTY		1 /* queue status bits */
#define QUEUE_STAT1_NEARLY_EMPTY	2
#define QUEUE_STAT1_NEARLY_FULL		4
#define QUEUE_STAT1_FULL		8
#define QUEUE_STAT2_UNDERFLOW		1
#define QUEUE_STAT2_OVERFLOW		2

#define QUEUE_WATERMARK_0_ENTRIES	0
#define QUEUE_WATERMARK_1_ENTRY		1
#define QUEUE_WATERMARK_2_ENTRIES	2
#define QUEUE_WATERMARK_4_ENTRIES	3
#define QUEUE_WATERMARK_8_ENTRIES	4
#define QUEUE_WATERMARK_16_ENTRIES	5
#define QUEUE_WATERMARK_32_ENTRIES	6
#define QUEUE_WATERMARK_64_ENTRIES	7

/* queue interrupt request conditions */
#define QUEUE_IRQ_SRC_EMPTY		0
#define QUEUE_IRQ_SRC_NEARLY_EMPTY	1
#define QUEUE_IRQ_SRC_NEARLY_FULL	2
#define QUEUE_IRQ_SRC_FULL		3
#define QUEUE_IRQ_SRC_NOT_EMPTY		4
#define QUEUE_IRQ_SRC_NOT_NEARLY_EMPTY	5
#define QUEUE_IRQ_SRC_NOT_NEARLY_FULL	6
#define QUEUE_IRQ_SRC_NOT_FULL		7

struct qmgr_regs {
	u32 acc[QUEUES][MAX_QUEUE_LENGTH]; /* 0x000 - 0x3FF */
	u32 stat1[4];		/* 0x400 - 0x40F */
	u32 stat2[2];		/* 0x410 - 0x417 */
	u32 statne_h;		/* 0x418 - queue nearly empty */
	u32 statf_h;		/* 0x41C - queue full */
	u32 irqsrc[4];		/* 0x420 - 0x42F IRC source */
	u32 irqen[2];		/* 0x430 - 0x437 IRQ enabled */
	u32 irqstat[2];		/* 0x438 - 0x43F - IRQ access only */
	u32 reserved[1776];
	u32 sram[2048];		/* 0x2000 - 0x3FFF - config and buffer */
};

void qmgr_set_irq(unsigned int queue, int src,
		  void (*handler)(void *pdev), void *pdev);
void qmgr_enable_irq(unsigned int queue);
void qmgr_disable_irq(unsigned int queue);

/* request_ and release_queue() must be called from non-IRQ context */

#if DEBUG_QMGR
extern char qmgr_queue_descs[QUEUES][32];

int qmgr_request_queue(unsigned int queue, unsigned int len /* dwords */,
		       unsigned int nearly_empty_watermark,
		       unsigned int nearly_full_watermark,
		       const char *desc_format, const char* name);
#else
int __qmgr_request_queue(unsigned int queue, unsigned int len /* dwords */,
			 unsigned int nearly_empty_watermark,
			 unsigned int nearly_full_watermark);
#define qmgr_request_queue(queue, len, nearly_empty_watermark,		\
			   nearly_full_watermark, desc_format, name)	\
	__qmgr_request_queue(queue, len, nearly_empty_watermark,	\
			     nearly_full_watermark)
#endif

void qmgr_release_queue(unsigned int queue);


static inline void qmgr_put_entry(unsigned int queue, u32 val)
{
	struct qmgr_regs __iomem *qmgr_regs = IXP4XX_QMGR_BASE_VIRT;
#if DEBUG_QMGR
	BUG_ON(!qmgr_queue_descs[queue]); /* not yet requested */

	printk(KERN_DEBUG "Queue %s(%i) put %X\n",
	       qmgr_queue_descs[queue], queue, val);
#endif
	__raw_writel(val, &qmgr_regs->acc[queue][0]);
}

static inline u32 qmgr_get_entry(unsigned int queue)
{
	u32 val;
	const struct qmgr_regs __iomem *qmgr_regs = IXP4XX_QMGR_BASE_VIRT;
	val = __raw_readl(&qmgr_regs->acc[queue][0]);
#if DEBUG_QMGR
	BUG_ON(!qmgr_queue_descs[queue]); /* not yet requested */

	printk(KERN_DEBUG "Queue %s(%i) get %X\n",
	       qmgr_queue_descs[queue], queue, val);
#endif
	return val;
}

static inline int __qmgr_get_stat1(unsigned int queue)
{
	const struct qmgr_regs __iomem *qmgr_regs = IXP4XX_QMGR_BASE_VIRT;
	return (__raw_readl(&qmgr_regs->stat1[queue >> 3])
		>> ((queue & 7) << 2)) & 0xF;
}

static inline int __qmgr_get_stat2(unsigned int queue)
{
	const struct qmgr_regs __iomem *qmgr_regs = IXP4XX_QMGR_BASE_VIRT;
	BUG_ON(queue >= HALF_QUEUES);
	return (__raw_readl(&qmgr_regs->stat2[queue >> 4])
		>> ((queue & 0xF) << 1)) & 0x3;
}

/**
 * qmgr_stat_empty() - checks if a hardware queue is empty
 * @queue:	queue number
 *
 * Returns non-zero value if the queue is empty.
 */
static inline int qmgr_stat_empty(unsigned int queue)
{
	BUG_ON(queue >= HALF_QUEUES);
	return __qmgr_get_stat1(queue) & QUEUE_STAT1_EMPTY;
}

/**
 * qmgr_stat_below_low_watermark() - checks if a queue is below low watermark
 * @queue:	queue number
 *
 * Returns non-zero value if the queue is below low watermark.
 */
static inline int qmgr_stat_below_low_watermark(unsigned int queue)
{
	const struct qmgr_regs __iomem *qmgr_regs = IXP4XX_QMGR_BASE_VIRT;
	if (queue >= HALF_QUEUES)
		return (__raw_readl(&qmgr_regs->statne_h) >>
			(queue - HALF_QUEUES)) & 0x01;
	return __qmgr_get_stat1(queue) & QUEUE_STAT1_NEARLY_EMPTY;
}

/**
 * qmgr_stat_above_high_watermark() - checks if a queue is above high watermark
 * @queue:	queue number
 *
 * Returns non-zero value if the queue is above high watermark
 */
static inline int qmgr_stat_above_high_watermark(unsigned int queue)
{
	BUG_ON(queue >= HALF_QUEUES);
	return __qmgr_get_stat1(queue) & QUEUE_STAT1_NEARLY_FULL;
}

/**
 * qmgr_stat_full() - checks if a hardware queue is full
 * @queue:	queue number
 *
 * Returns non-zero value if the queue is full.
 */
static inline int qmgr_stat_full(unsigned int queue)
{
	const struct qmgr_regs __iomem *qmgr_regs = IXP4XX_QMGR_BASE_VIRT;
	if (queue >= HALF_QUEUES)
		return (__raw_readl(&qmgr_regs->statf_h) >>
			(queue - HALF_QUEUES)) & 0x01;
	return __qmgr_get_stat1(queue) & QUEUE_STAT1_FULL;
}

/**
 * qmgr_stat_underflow() - checks if a hardware queue experienced underflow
 * @queue:	queue number
 *
 * Returns non-zero value if the queue experienced underflow.
 */
static inline int qmgr_stat_underflow(unsigned int queue)
{
	return __qmgr_get_stat2(queue) & QUEUE_STAT2_UNDERFLOW;
}

/**
 * qmgr_stat_overflow() - checks if a hardware queue experienced overflow
 * @queue:	queue number
 *
 * Returns non-zero value if the queue experienced overflow.
 */
static inline int qmgr_stat_overflow(unsigned int queue)
{
	return __qmgr_get_stat2(queue) & QUEUE_STAT2_OVERFLOW;
}

#endif
Commit	Line	Data
82a96f57 KH	1	/*
	2	* Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl>
	3	*
	4	* This program is free software; you can redistribute it and/or modify it
	5	* under the terms of version 2 of the GNU General Public License
	6	* as published by the Free Software Foundation.
	7	*/
	8
	9	#ifndef IXP4XX_QMGR_H
	10	#define IXP4XX_QMGR_H
	11
	12	#include <linux/io.h>
	13	#include <linux/kernel.h>
	14
e6da96ac KH	15	#define DEBUG_QMGR 0
e6da96ac KH	16
82a96f57	17	#define HALF_QUEUES 32
a6a9fb85	18	#define QUEUES 64
82a96f57 KH	19	#define MAX_QUEUE_LENGTH 4 /* in dwords */
	20
	21	#define QUEUE_STAT1_EMPTY 1 /* queue status bits */
	22	#define QUEUE_STAT1_NEARLY_EMPTY 2
	23	#define QUEUE_STAT1_NEARLY_FULL 4
	24	#define QUEUE_STAT1_FULL 8
	25	#define QUEUE_STAT2_UNDERFLOW 1
	26	#define QUEUE_STAT2_OVERFLOW 2
	27
	28	#define QUEUE_WATERMARK_0_ENTRIES 0
	29	#define QUEUE_WATERMARK_1_ENTRY 1
	30	#define QUEUE_WATERMARK_2_ENTRIES 2
	31	#define QUEUE_WATERMARK_4_ENTRIES 3
	32	#define QUEUE_WATERMARK_8_ENTRIES 4
	33	#define QUEUE_WATERMARK_16_ENTRIES 5
	34	#define QUEUE_WATERMARK_32_ENTRIES 6
	35	#define QUEUE_WATERMARK_64_ENTRIES 7
	36
	37	/* queue interrupt request conditions */
	38	#define QUEUE_IRQ_SRC_EMPTY 0
	39	#define QUEUE_IRQ_SRC_NEARLY_EMPTY 1
	40	#define QUEUE_IRQ_SRC_NEARLY_FULL 2
	41	#define QUEUE_IRQ_SRC_FULL 3
	42	#define QUEUE_IRQ_SRC_NOT_EMPTY 4
	43	#define QUEUE_IRQ_SRC_NOT_NEARLY_EMPTY 5
	44	#define QUEUE_IRQ_SRC_NOT_NEARLY_FULL 6
	45	#define QUEUE_IRQ_SRC_NOT_FULL 7
	46
	47	struct qmgr_regs {
	48	u32 acc[QUEUES][MAX_QUEUE_LENGTH]; /* 0x000 - 0x3FF */
	49	u32 stat1[4]; /* 0x400 - 0x40F */
	50	u32 stat2[2]; /* 0x410 - 0x417 */
	51	u32 statne_h; /* 0x418 - queue nearly empty */
	52	u32 statf_h; /* 0x41C - queue full */
	53	u32 irqsrc[4]; /* 0x420 - 0x42F IRC source */
	54	u32 irqen[2]; /* 0x430 - 0x437 IRQ enabled */
	55	u32 irqstat[2]; /* 0x438 - 0x43F - IRQ access only */
	56	u32 reserved[1776];
	57	u32 sram[2048]; /* 0x2000 - 0x3FFF - config and buffer */
	58	};
	59
	60	void qmgr_set_irq(unsigned int queue, int src,
	61	void (handler)(void pdev), void *pdev);
	62	void qmgr_enable_irq(unsigned int queue);
	63	void qmgr_disable_irq(unsigned int queue);
	64
	65	/* request_ and release_queue() must be called from non-IRQ context */
e6da96ac KH	66
	67	#if DEBUG_QMGR
	68	extern char qmgr_queue_descs[QUEUES][32];
	69
82a96f57 KH	70	int qmgr_request_queue(unsigned int queue, unsigned int len /* dwords */,
82a96f57 KH	71	unsigned int nearly_empty_watermark,
e6da96ac KH	72	unsigned int nearly_full_watermark,
	73	const char desc_format, const char name);
	74	#else
	75	int __qmgr_request_queue(unsigned int queue, unsigned int len /* dwords */,
	76	unsigned int nearly_empty_watermark,
	77	unsigned int nearly_full_watermark);
	78	#define qmgr_request_queue(queue, len, nearly_empty_watermark, \
	79	nearly_full_watermark, desc_format, name) \
	80	__qmgr_request_queue(queue, len, nearly_empty_watermark, \
	81	nearly_full_watermark)
	82	#endif
	83
82a96f57 KH	84	void qmgr_release_queue(unsigned int queue);
	85
	86
	87	static inline void qmgr_put_entry(unsigned int queue, u32 val)
	88	{
0d2c9f05	89	struct qmgr_regs __iomem *qmgr_regs = IXP4XX_QMGR_BASE_VIRT;
e6da96ac KH	90	#if DEBUG_QMGR
	91	BUG_ON(!qmgr_queue_descs[queue]); /* not yet requested */
	92
	93	printk(KERN_DEBUG "Queue %s(%i) put %X\n",
	94	qmgr_queue_descs[queue], queue, val);
	95	#endif
82a96f57 KH	96	__raw_writel(val, &qmgr_regs->acc[queue][0]);
	97	}
	98
	99	static inline u32 qmgr_get_entry(unsigned int queue)
	100	{
e6da96ac	101	u32 val;
0d2c9f05	102	const struct qmgr_regs __iomem *qmgr_regs = IXP4XX_QMGR_BASE_VIRT;
e6da96ac KH	103	val = __raw_readl(&qmgr_regs->acc[queue][0]);
	104	#if DEBUG_QMGR
	105	BUG_ON(!qmgr_queue_descs[queue]); /* not yet requested */
	106
	107	printk(KERN_DEBUG "Queue %s(%i) get %X\n",
	108	qmgr_queue_descs[queue], queue, val);
	109	#endif
	110	return val;
82a96f57 KH	111	}
82a96f57 KH	112
a6a9fb85	113	static inline int __qmgr_get_stat1(unsigned int queue)
82a96f57	114	{
0d2c9f05	115	const struct qmgr_regs __iomem *qmgr_regs = IXP4XX_QMGR_BASE_VIRT;
82a96f57 KH	116	return (__raw_readl(&qmgr_regs->stat1[queue >> 3])
	117	>> ((queue & 7) << 2)) & 0xF;
	118	}
	119
a6a9fb85	120	static inline int __qmgr_get_stat2(unsigned int queue)
82a96f57	121	{
0d2c9f05	122	const struct qmgr_regs __iomem *qmgr_regs = IXP4XX_QMGR_BASE_VIRT;
a6a9fb85	123	BUG_ON(queue >= HALF_QUEUES);
82a96f57 KH	124	return (__raw_readl(&qmgr_regs->stat2[queue >> 4])
	125	>> ((queue & 0xF) << 1)) & 0x3;
	126	}
	127
a6a9fb85 KH	128	/**
	129	* qmgr_stat_empty() - checks if a hardware queue is empty
	130	* @queue: queue number
	131	*
	132	* Returns non-zero value if the queue is empty.
	133	*/
82a96f57 KH	134	static inline int qmgr_stat_empty(unsigned int queue)
82a96f57 KH	135	{
a6a9fb85 KH	136	BUG_ON(queue >= HALF_QUEUES);
a6a9fb85 KH	137	return __qmgr_get_stat1(queue) & QUEUE_STAT1_EMPTY;
82a96f57 KH	138	}
82a96f57 KH	139
a6a9fb85	140	/**
9733bb8e	141	* qmgr_stat_below_low_watermark() - checks if a queue is below low watermark
a6a9fb85 KH	142	* @queue: queue number
a6a9fb85 KH	143	*
9733bb8e	144	* Returns non-zero value if the queue is below low watermark.
a6a9fb85	145	*/
9733bb8e	146	static inline int qmgr_stat_below_low_watermark(unsigned int queue)
82a96f57	147	{
0d2c9f05	148	const struct qmgr_regs __iomem *qmgr_regs = IXP4XX_QMGR_BASE_VIRT;
a6a9fb85 KH	149	if (queue >= HALF_QUEUES)
	150	return (__raw_readl(&qmgr_regs->statne_h) >>
	151	(queue - HALF_QUEUES)) & 0x01;
	152	return __qmgr_get_stat1(queue) & QUEUE_STAT1_NEARLY_EMPTY;
82a96f57 KH	153	}
82a96f57 KH	154
a6a9fb85	155	/**
9733bb8e	156	* qmgr_stat_above_high_watermark() - checks if a queue is above high watermark
a6a9fb85 KH	157	* @queue: queue number
a6a9fb85 KH	158	*
9733bb8e	159	* Returns non-zero value if the queue is above high watermark
a6a9fb85	160	*/
9733bb8e	161	static inline int qmgr_stat_above_high_watermark(unsigned int queue)
82a96f57	162	{
a6a9fb85 KH	163	BUG_ON(queue >= HALF_QUEUES);
a6a9fb85 KH	164	return __qmgr_get_stat1(queue) & QUEUE_STAT1_NEARLY_FULL;
82a96f57 KH	165	}
82a96f57 KH	166
a6a9fb85	167	/**
9733bb8e	168	* qmgr_stat_full() - checks if a hardware queue is full
a6a9fb85 KH	169	* @queue: queue number
	170	*
	171	* Returns non-zero value if the queue is full.
	172	*/
82a96f57 KH	173	static inline int qmgr_stat_full(unsigned int queue)
82a96f57 KH	174	{
0d2c9f05	175	const struct qmgr_regs __iomem *qmgr_regs = IXP4XX_QMGR_BASE_VIRT;
a6a9fb85 KH	176	if (queue >= HALF_QUEUES)
	177	return (__raw_readl(&qmgr_regs->statf_h) >>
	178	(queue - HALF_QUEUES)) & 0x01;
	179	return __qmgr_get_stat1(queue) & QUEUE_STAT1_FULL;
82a96f57 KH	180	}
82a96f57 KH	181
a6a9fb85	182	/**
9733bb8e	183	* qmgr_stat_underflow() - checks if a hardware queue experienced underflow
a6a9fb85 KH	184	* @queue: queue number
a6a9fb85 KH	185	*
9733bb8e	186	* Returns non-zero value if the queue experienced underflow.
a6a9fb85	187	*/
82a96f57 KH	188	static inline int qmgr_stat_underflow(unsigned int queue)
82a96f57 KH	189	{
a6a9fb85	190	return __qmgr_get_stat2(queue) & QUEUE_STAT2_UNDERFLOW;
82a96f57 KH	191	}
82a96f57 KH	192
a6a9fb85	193	/**
9733bb8e	194	* qmgr_stat_overflow() - checks if a hardware queue experienced overflow
a6a9fb85 KH	195	* @queue: queue number
a6a9fb85 KH	196	*
9733bb8e	197	* Returns non-zero value if the queue experienced overflow.
a6a9fb85	198	*/
82a96f57 KH	199	static inline int qmgr_stat_overflow(unsigned int queue)
82a96f57 KH	200	{
a6a9fb85	201	return __qmgr_get_stat2(queue) & QUEUE_STAT2_OVERFLOW;
82a96f57 KH	202	}
	203
	204	#endif