]>
Commit | Line | Data |
---|---|---|
b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
1da177e4 LT |
2 | /* |
3 | * arch/arm/mach-ixp4xx/ixdp425-setup.c | |
4 | * | |
9bf4d676 | 5 | * IXDP425/IXCDP1100 board-setup |
1da177e4 LT |
6 | * |
7 | * Copyright (C) 2003-2005 MontaVista Software, Inc. | |
8 | * | |
9 | * Author: Deepak Saxena <dsaxena@plexity.net> | |
10 | */ | |
11 | ||
12 | #include <linux/kernel.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/device.h> | |
15 | #include <linux/serial.h> | |
16 | #include <linux/tty.h> | |
17 | #include <linux/serial_8250.h> | |
b2e63555 | 18 | #include <linux/gpio/machine.h> |
4ad48b4b VB |
19 | #include <linux/io.h> |
20 | #include <linux/mtd/mtd.h> | |
d4092d76 | 21 | #include <linux/mtd/rawnand.h> |
4ad48b4b | 22 | #include <linux/mtd/partitions.h> |
c7921bb3 | 23 | #include <linux/mtd/platnand.h> |
8029db12 | 24 | #include <linux/delay.h> |
8040dd09 | 25 | #include <linux/gpio.h> |
1da177e4 LT |
26 | #include <asm/types.h> |
27 | #include <asm/setup.h> | |
28 | #include <asm/memory.h> | |
a09e64fb | 29 | #include <mach/hardware.h> |
1da177e4 LT |
30 | #include <asm/mach-types.h> |
31 | #include <asm/irq.h> | |
32 | #include <asm/mach/arch.h> | |
33 | #include <asm/mach/flash.h> | |
34 | ||
dc8ef8cd LW |
35 | #include "irqs.h" |
36 | ||
9bf4d676 KH |
37 | #define IXDP425_SDA_PIN 7 |
38 | #define IXDP425_SCL_PIN 6 | |
39 | ||
40 | /* NAND Flash pins */ | |
41 | #define IXDP425_NAND_NCE_PIN 12 | |
42 | ||
43 | #define IXDP425_NAND_CMD_BYTE 0x01 | |
44 | #define IXDP425_NAND_ADDR_BYTE 0x02 | |
45 | ||
1da177e4 LT |
46 | static struct flash_platform_data ixdp425_flash_data = { |
47 | .map_name = "cfi_probe", | |
48 | .width = 2, | |
49 | }; | |
50 | ||
51 | static struct resource ixdp425_flash_resource = { | |
1da177e4 LT |
52 | .flags = IORESOURCE_MEM, |
53 | }; | |
54 | ||
55 | static struct platform_device ixdp425_flash = { | |
56 | .name = "IXP4XX-Flash", | |
57 | .id = 0, | |
58 | .dev = { | |
59 | .platform_data = &ixdp425_flash_data, | |
60 | }, | |
61 | .num_resources = 1, | |
62 | .resource = &ixdp425_flash_resource, | |
63 | }; | |
64 | ||
4ad48b4b VB |
65 | #if defined(CONFIG_MTD_NAND_PLATFORM) || \ |
66 | defined(CONFIG_MTD_NAND_PLATFORM_MODULE) | |
67 | ||
4ad48b4b VB |
68 | static struct mtd_partition ixdp425_partitions[] = { |
69 | { | |
70 | .name = "ixp400 NAND FS 0", | |
71 | .offset = 0, | |
72 | .size = SZ_8M | |
73 | }, { | |
74 | .name = "ixp400 NAND FS 1", | |
75 | .offset = MTDPART_OFS_APPEND, | |
76 | .size = MTDPART_SIZ_FULL | |
77 | }, | |
78 | }; | |
4ad48b4b VB |
79 | |
80 | static void | |
47bd59e5 | 81 | ixdp425_flash_nand_cmd_ctrl(struct nand_chip *this, int cmd, unsigned int ctrl) |
4ad48b4b | 82 | { |
d9dccc68 | 83 | int offset = (int)nand_get_controller_data(this); |
4ad48b4b VB |
84 | |
85 | if (ctrl & NAND_CTRL_CHANGE) { | |
86 | if (ctrl & NAND_NCE) { | |
8040dd09 | 87 | gpio_set_value(IXDP425_NAND_NCE_PIN, 0); |
4ad48b4b VB |
88 | udelay(5); |
89 | } else | |
8040dd09 | 90 | gpio_set_value(IXDP425_NAND_NCE_PIN, 1); |
4ad48b4b VB |
91 | |
92 | offset = (ctrl & NAND_CLE) ? IXDP425_NAND_CMD_BYTE : 0; | |
93 | offset |= (ctrl & NAND_ALE) ? IXDP425_NAND_ADDR_BYTE : 0; | |
d9dccc68 | 94 | nand_set_controller_data(this, (void *)offset); |
4ad48b4b VB |
95 | } |
96 | ||
97 | if (cmd != NAND_CMD_NONE) | |
82fc5099 | 98 | writeb(cmd, this->legacy.IO_ADDR_W + offset); |
4ad48b4b VB |
99 | } |
100 | ||
101 | static struct platform_nand_data ixdp425_flash_nand_data = { | |
102 | .chip = { | |
ef077179 | 103 | .nr_chips = 1, |
4ad48b4b | 104 | .chip_delay = 30, |
4ad48b4b VB |
105 | .partitions = ixdp425_partitions, |
106 | .nr_partitions = ARRAY_SIZE(ixdp425_partitions), | |
4ad48b4b VB |
107 | }, |
108 | .ctrl = { | |
109 | .cmd_ctrl = ixdp425_flash_nand_cmd_ctrl | |
110 | } | |
111 | }; | |
112 | ||
113 | static struct resource ixdp425_flash_nand_resource = { | |
114 | .flags = IORESOURCE_MEM, | |
115 | }; | |
116 | ||
117 | static struct platform_device ixdp425_flash_nand = { | |
118 | .name = "gen_nand", | |
119 | .id = -1, | |
120 | .dev = { | |
121 | .platform_data = &ixdp425_flash_nand_data, | |
122 | }, | |
123 | .num_resources = 1, | |
124 | .resource = &ixdp425_flash_nand_resource, | |
125 | }; | |
126 | #endif /* CONFIG_MTD_NAND_PLATFORM */ | |
127 | ||
b2e63555 | 128 | static struct gpiod_lookup_table ixdp425_i2c_gpiod_table = { |
f59c303b | 129 | .dev_id = "i2c-gpio.0", |
b2e63555 LW |
130 | .table = { |
131 | GPIO_LOOKUP_IDX("IXP4XX_GPIO_CHIP", IXDP425_SDA_PIN, | |
4d0ce62c | 132 | NULL, 0, GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN), |
b2e63555 | 133 | GPIO_LOOKUP_IDX("IXP4XX_GPIO_CHIP", IXDP425_SCL_PIN, |
4d0ce62c | 134 | NULL, 1, GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN), |
b2e63555 | 135 | }, |
1da177e4 LT |
136 | }; |
137 | ||
5a4a2387 MLJ |
138 | static struct platform_device ixdp425_i2c_gpio = { |
139 | .name = "i2c-gpio", | |
1da177e4 | 140 | .id = 0, |
5a4a2387 | 141 | .dev = { |
b2e63555 | 142 | .platform_data = NULL, |
1da177e4 | 143 | }, |
1da177e4 LT |
144 | }; |
145 | ||
146 | static struct resource ixdp425_uart_resources[] = { | |
147 | { | |
148 | .start = IXP4XX_UART1_BASE_PHYS, | |
149 | .end = IXP4XX_UART1_BASE_PHYS + 0x0fff, | |
150 | .flags = IORESOURCE_MEM | |
151 | }, | |
152 | { | |
153 | .start = IXP4XX_UART2_BASE_PHYS, | |
154 | .end = IXP4XX_UART2_BASE_PHYS + 0x0fff, | |
155 | .flags = IORESOURCE_MEM | |
156 | } | |
157 | }; | |
158 | ||
159 | static struct plat_serial8250_port ixdp425_uart_data[] = { | |
160 | { | |
161 | .mapbase = IXP4XX_UART1_BASE_PHYS, | |
162 | .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET, | |
163 | .irq = IRQ_IXP4XX_UART1, | |
8c741ed7 | 164 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, |
1da177e4 LT |
165 | .iotype = UPIO_MEM, |
166 | .regshift = 2, | |
167 | .uartclk = IXP4XX_UART_XTAL, | |
168 | }, | |
169 | { | |
170 | .mapbase = IXP4XX_UART2_BASE_PHYS, | |
171 | .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET, | |
a35d6c91 | 172 | .irq = IRQ_IXP4XX_UART2, |
8c741ed7 | 173 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, |
1da177e4 LT |
174 | .iotype = UPIO_MEM, |
175 | .regshift = 2, | |
176 | .uartclk = IXP4XX_UART_XTAL, | |
bcaafbe4 SS |
177 | }, |
178 | { }, | |
1da177e4 LT |
179 | }; |
180 | ||
181 | static struct platform_device ixdp425_uart = { | |
182 | .name = "serial8250", | |
6df29deb | 183 | .id = PLAT8250_DEV_PLATFORM, |
1da177e4 LT |
184 | .dev.platform_data = ixdp425_uart_data, |
185 | .num_resources = 2, | |
186 | .resource = ixdp425_uart_resources | |
187 | }; | |
188 | ||
78225913 RW |
189 | /* Built-in 10/100 Ethernet MAC interfaces */ |
190 | static struct eth_plat_info ixdp425_plat_eth[] = { | |
191 | { | |
192 | .phy = 0, | |
193 | .rxq = 3, | |
194 | .txreadyq = 20, | |
195 | }, { | |
196 | .phy = 1, | |
197 | .rxq = 4, | |
198 | .txreadyq = 21, | |
199 | } | |
200 | }; | |
201 | ||
202 | static struct platform_device ixdp425_eth[] = { | |
203 | { | |
204 | .name = "ixp4xx_eth", | |
205 | .id = IXP4XX_ETH_NPEB, | |
206 | .dev.platform_data = ixdp425_plat_eth, | |
207 | }, { | |
208 | .name = "ixp4xx_eth", | |
209 | .id = IXP4XX_ETH_NPEC, | |
210 | .dev.platform_data = ixdp425_plat_eth + 1, | |
211 | } | |
212 | }; | |
213 | ||
1da177e4 | 214 | static struct platform_device *ixdp425_devices[] __initdata = { |
5a4a2387 | 215 | &ixdp425_i2c_gpio, |
1da177e4 | 216 | &ixdp425_flash, |
4ad48b4b VB |
217 | #if defined(CONFIG_MTD_NAND_PLATFORM) || \ |
218 | defined(CONFIG_MTD_NAND_PLATFORM_MODULE) | |
219 | &ixdp425_flash_nand, | |
220 | #endif | |
78225913 RW |
221 | &ixdp425_uart, |
222 | &ixdp425_eth[0], | |
223 | &ixdp425_eth[1], | |
1da177e4 LT |
224 | }; |
225 | ||
1da177e4 LT |
226 | static void __init ixdp425_init(void) |
227 | { | |
228 | ixp4xx_sys_init(); | |
229 | ||
54e269ea DS |
230 | ixdp425_flash_resource.start = IXP4XX_EXP_BUS_BASE(0); |
231 | ixdp425_flash_resource.end = | |
232 | IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1; | |
1da177e4 | 233 | |
4ad48b4b VB |
234 | #if defined(CONFIG_MTD_NAND_PLATFORM) || \ |
235 | defined(CONFIG_MTD_NAND_PLATFORM_MODULE) | |
236 | ixdp425_flash_nand_resource.start = IXP4XX_EXP_BUS_BASE(3), | |
237 | ixdp425_flash_nand_resource.end = IXP4XX_EXP_BUS_BASE(3) + 0x10 - 1; | |
238 | ||
8040dd09 LW |
239 | gpio_request(IXDP425_NAND_NCE_PIN, "NAND NCE pin"); |
240 | gpio_direction_output(IXDP425_NAND_NCE_PIN, 0); | |
4ad48b4b VB |
241 | |
242 | /* Configure expansion bus for NAND Flash */ | |
243 | *IXP4XX_EXP_CS3 = IXP4XX_EXP_BUS_CS_EN | | |
244 | IXP4XX_EXP_BUS_STROBE_T(1) | /* extend by 1 clock */ | |
245 | IXP4XX_EXP_BUS_CYCLES(0) | /* Intel cycles */ | |
246 | IXP4XX_EXP_BUS_SIZE(0) | /* 512bytes addr space*/ | |
247 | IXP4XX_EXP_BUS_WR_EN | | |
248 | IXP4XX_EXP_BUS_BYTE_EN; /* 8 bit data bus */ | |
249 | #endif | |
250 | ||
45fba084 RS |
251 | if (cpu_is_ixp43x()) { |
252 | ixdp425_uart.num_resources = 1; | |
253 | ixdp425_uart_data[1].flags = 0; | |
254 | } | |
255 | ||
b2e63555 | 256 | gpiod_add_lookup_table(&ixdp425_i2c_gpiod_table); |
1da177e4 LT |
257 | platform_add_devices(ixdp425_devices, ARRAY_SIZE(ixdp425_devices)); |
258 | } | |
259 | ||
b38708fc | 260 | #ifdef CONFIG_ARCH_IXDP425 |
1da177e4 | 261 | MACHINE_START(IXDP425, "Intel IXDP425 Development Platform") |
e9dea0c6 | 262 | /* Maintainer: MontaVista Software, Inc. */ |
e605ecd7 | 263 | .map_io = ixp4xx_map_io, |
f449588c | 264 | .init_early = ixp4xx_init_early, |
e9dea0c6 | 265 | .init_irq = ixp4xx_init_irq, |
6bb27d73 | 266 | .init_time = ixp4xx_timer_init, |
e022c729 | 267 | .atag_offset = 0x100, |
e9dea0c6 | 268 | .init_machine = ixdp425_init, |
7553ee77 NP |
269 | #if defined(CONFIG_PCI) |
270 | .dma_zone_size = SZ_64M, | |
271 | #endif | |
d1b860fb | 272 | .restart = ixp4xx_restart, |
1da177e4 | 273 | MACHINE_END |
e0a20089 | 274 | #endif |
1da177e4 | 275 | |
e0a20089 | 276 | #ifdef CONFIG_MACH_IXDP465 |
1da177e4 | 277 | MACHINE_START(IXDP465, "Intel IXDP465 Development Platform") |
e9dea0c6 | 278 | /* Maintainer: MontaVista Software, Inc. */ |
e605ecd7 | 279 | .map_io = ixp4xx_map_io, |
f449588c | 280 | .init_early = ixp4xx_init_early, |
e9dea0c6 | 281 | .init_irq = ixp4xx_init_irq, |
6bb27d73 | 282 | .init_time = ixp4xx_timer_init, |
e022c729 | 283 | .atag_offset = 0x100, |
e9dea0c6 | 284 | .init_machine = ixdp425_init, |
7553ee77 NP |
285 | #if defined(CONFIG_PCI) |
286 | .dma_zone_size = SZ_64M, | |
287 | #endif | |
1da177e4 | 288 | MACHINE_END |
e0a20089 | 289 | #endif |
1da177e4 | 290 | |
e0a20089 | 291 | #ifdef CONFIG_ARCH_PRPMC1100 |
1da177e4 | 292 | MACHINE_START(IXCDP1100, "Intel IXCDP1100 Development Platform") |
e9dea0c6 | 293 | /* Maintainer: MontaVista Software, Inc. */ |
e605ecd7 | 294 | .map_io = ixp4xx_map_io, |
f449588c | 295 | .init_early = ixp4xx_init_early, |
e9dea0c6 | 296 | .init_irq = ixp4xx_init_irq, |
6bb27d73 | 297 | .init_time = ixp4xx_timer_init, |
e022c729 | 298 | .atag_offset = 0x100, |
e9dea0c6 | 299 | .init_machine = ixdp425_init, |
7553ee77 NP |
300 | #if defined(CONFIG_PCI) |
301 | .dma_zone_size = SZ_64M, | |
302 | #endif | |
1da177e4 | 303 | MACHINE_END |
e0a20089 | 304 | #endif |
45fba084 RS |
305 | |
306 | #ifdef CONFIG_MACH_KIXRP435 | |
307 | MACHINE_START(KIXRP435, "Intel KIXRP435 Reference Platform") | |
308 | /* Maintainer: MontaVista Software, Inc. */ | |
45fba084 | 309 | .map_io = ixp4xx_map_io, |
f449588c | 310 | .init_early = ixp4xx_init_early, |
45fba084 | 311 | .init_irq = ixp4xx_init_irq, |
6bb27d73 | 312 | .init_time = ixp4xx_timer_init, |
e022c729 | 313 | .atag_offset = 0x100, |
45fba084 | 314 | .init_machine = ixdp425_init, |
7553ee77 NP |
315 | #if defined(CONFIG_PCI) |
316 | .dma_zone_size = SZ_64M, | |
317 | #endif | |
45fba084 RS |
318 | MACHINE_END |
319 | #endif |