[mirror_ubuntu-focal-kernel.git] / arch / arm / mach-ixp4xx / ixdp425-setup.c

/*
 * arch/arm/mach-ixp4xx/ixdp425-setup.c
 *
 * IXDP425/IXCDP1100 board-setup 
 *
 * Copyright (C) 2003-2005 MontaVista Software, Inc.
 *
 * Author: Deepak Saxena <dsaxena@plexity.net>
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/device.h>
#include <linux/serial.h>
#include <linux/tty.h>
#include <linux/serial_8250.h>
#include <linux/slab.h>
#include <linux/i2c-gpio.h>
#include <linux/io.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/partitions.h>

#include <asm/types.h>
#include <asm/setup.h>
#include <asm/memory.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/flash.h>
#include <asm/delay.h>

static struct flash_platform_data ixdp425_flash_data = {
	.map_name	= "cfi_probe",
	.width		= 2,
};

static struct resource ixdp425_flash_resource = {
	.flags		= IORESOURCE_MEM,
};

static struct platform_device ixdp425_flash = {
	.name		= "IXP4XX-Flash",
	.id		= 0,
	.dev		= {
		.platform_data = &ixdp425_flash_data,
	},
	.num_resources	= 1,
	.resource	= &ixdp425_flash_resource,
};

#if defined(CONFIG_MTD_NAND_PLATFORM) || \
    defined(CONFIG_MTD_NAND_PLATFORM_MODULE)

#ifdef CONFIG_MTD_PARTITIONS
const char *part_probes[] = { "cmdlinepart", NULL };

static struct mtd_partition ixdp425_partitions[] = {
	{
		.name	= "ixp400 NAND FS 0",
		.offset	= 0,
		.size 	= SZ_8M
	}, {
		.name	= "ixp400 NAND FS 1",
		.offset	= MTDPART_OFS_APPEND,
		.size	= MTDPART_SIZ_FULL
	},
};
#endif

static void
ixdp425_flash_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
	struct nand_chip *this = mtd->priv;
	int offset = (int)this->priv;

	if (ctrl & NAND_CTRL_CHANGE) {
		if (ctrl & NAND_NCE) {
			gpio_line_set(IXDP425_NAND_NCE_PIN, IXP4XX_GPIO_LOW);
			udelay(5);
		} else
			gpio_line_set(IXDP425_NAND_NCE_PIN, IXP4XX_GPIO_HIGH);

		offset = (ctrl & NAND_CLE) ? IXDP425_NAND_CMD_BYTE : 0;
		offset |= (ctrl & NAND_ALE) ? IXDP425_NAND_ADDR_BYTE : 0;
		this->priv = (void *)offset;
	}

	if (cmd != NAND_CMD_NONE)
		writeb(cmd, this->IO_ADDR_W + offset);
}

static struct platform_nand_data ixdp425_flash_nand_data = {
	.chip = {
		.chip_delay		= 30,
		.options		= NAND_NO_AUTOINCR,
#ifdef CONFIG_MTD_PARTITIONS
		.part_probe_types 	= part_probes,
		.partitions	 	= ixdp425_partitions,
		.nr_partitions	 	= ARRAY_SIZE(ixdp425_partitions),
#endif
	},
	.ctrl = {
		.cmd_ctrl 		= ixdp425_flash_nand_cmd_ctrl
	}
};

static struct resource ixdp425_flash_nand_resource = {
	.flags		= IORESOURCE_MEM,
};

static struct platform_device ixdp425_flash_nand = {
	.name		= "gen_nand",
	.id		= -1,
	.dev		= {
		.platform_data = &ixdp425_flash_nand_data,
	},
	.num_resources	= 1,
	.resource	= &ixdp425_flash_nand_resource,
};
#endif	/* CONFIG_MTD_NAND_PLATFORM */

static struct i2c_gpio_platform_data ixdp425_i2c_gpio_data = {
	.sda_pin	= IXDP425_SDA_PIN,
	.scl_pin	= IXDP425_SCL_PIN,
};

static struct platform_device ixdp425_i2c_gpio = {
	.name		= "i2c-gpio",
	.id		= 0,
	.dev	 = {
		.platform_data	= &ixdp425_i2c_gpio_data,
	},
};

static struct resource ixdp425_uart_resources[] = {
	{
		.start		= IXP4XX_UART1_BASE_PHYS,
		.end		= IXP4XX_UART1_BASE_PHYS + 0x0fff,
		.flags		= IORESOURCE_MEM
	},
	{
		.start		= IXP4XX_UART2_BASE_PHYS,
		.end		= IXP4XX_UART2_BASE_PHYS + 0x0fff,
		.flags		= IORESOURCE_MEM
	}
};

static struct plat_serial8250_port ixdp425_uart_data[] = {
	{
		.mapbase	= IXP4XX_UART1_BASE_PHYS,
		.membase	= (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
		.irq		= IRQ_IXP4XX_UART1,
		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
		.iotype		= UPIO_MEM,
		.regshift	= 2,
		.uartclk	= IXP4XX_UART_XTAL,
	},
	{
		.mapbase	= IXP4XX_UART2_BASE_PHYS,
		.membase	= (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
		.irq		= IRQ_IXP4XX_UART2,
		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
		.iotype		= UPIO_MEM,
		.regshift	= 2,
		.uartclk	= IXP4XX_UART_XTAL,
	},
	{ },
};

static struct platform_device ixdp425_uart = {
	.name			= "serial8250",
	.id			= PLAT8250_DEV_PLATFORM,
	.dev.platform_data	= ixdp425_uart_data,
	.num_resources		= 2,
	.resource		= ixdp425_uart_resources
};

/* Built-in 10/100 Ethernet MAC interfaces */
static struct eth_plat_info ixdp425_plat_eth[] = {
	{
		.phy		= 0,
		.rxq		= 3,
		.txreadyq	= 20,
	}, {
		.phy		= 1,
		.rxq		= 4,
		.txreadyq	= 21,
	}
};

static struct platform_device ixdp425_eth[] = {
	{
		.name			= "ixp4xx_eth",
		.id			= IXP4XX_ETH_NPEB,
		.dev.platform_data	= ixdp425_plat_eth,
	}, {
		.name			= "ixp4xx_eth",
		.id			= IXP4XX_ETH_NPEC,
		.dev.platform_data	= ixdp425_plat_eth + 1,
	}
};

static struct platform_device *ixdp425_devices[] __initdata = {
	&ixdp425_i2c_gpio,
	&ixdp425_flash,
#if defined(CONFIG_MTD_NAND_PLATFORM) || \
    defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
	&ixdp425_flash_nand,
#endif
	&ixdp425_uart,
	&ixdp425_eth[0],
	&ixdp425_eth[1],
};

static void __init ixdp425_init(void)
{
	ixp4xx_sys_init();

	ixdp425_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
	ixdp425_flash_resource.end =
		IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1;

#if defined(CONFIG_MTD_NAND_PLATFORM) || \
    defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
	ixdp425_flash_nand_resource.start = IXP4XX_EXP_BUS_BASE(3),
	ixdp425_flash_nand_resource.end   = IXP4XX_EXP_BUS_BASE(3) + 0x10 - 1;

	gpio_line_config(IXDP425_NAND_NCE_PIN, IXP4XX_GPIO_OUT);

	/* Configure expansion bus for NAND Flash */
	*IXP4XX_EXP_CS3 = IXP4XX_EXP_BUS_CS_EN |
			  IXP4XX_EXP_BUS_STROBE_T(1) |	/* extend by 1 clock */
			  IXP4XX_EXP_BUS_CYCLES(0) |	/* Intel cycles */
			  IXP4XX_EXP_BUS_SIZE(0) |	/* 512bytes addr space*/
			  IXP4XX_EXP_BUS_WR_EN |
			  IXP4XX_EXP_BUS_BYTE_EN;	/* 8 bit data bus */
#endif

	if (cpu_is_ixp43x()) {
		ixdp425_uart.num_resources = 1;
		ixdp425_uart_data[1].flags = 0;
	}

	platform_add_devices(ixdp425_devices, ARRAY_SIZE(ixdp425_devices));
}

#ifdef CONFIG_ARCH_IXDP425
MACHINE_START(IXDP425, "Intel IXDP425 Development Platform")
	/* Maintainer: MontaVista Software, Inc. */
	.phys_io	= IXP4XX_PERIPHERAL_BASE_PHYS,
	.io_pg_offst	= ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
	.map_io		= ixp4xx_map_io,
	.init_irq	= ixp4xx_init_irq,
	.timer		= &ixp4xx_timer,
	.boot_params	= 0x0100,
	.init_machine	= ixdp425_init,
MACHINE_END
#endif

#ifdef CONFIG_MACH_IXDP465
MACHINE_START(IXDP465, "Intel IXDP465 Development Platform")
	/* Maintainer: MontaVista Software, Inc. */
	.phys_io	= IXP4XX_PERIPHERAL_BASE_PHYS,
	.io_pg_offst	= ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
	.map_io		= ixp4xx_map_io,
	.init_irq	= ixp4xx_init_irq,
	.timer		= &ixp4xx_timer,
	.boot_params	= 0x0100,
	.init_machine	= ixdp425_init,
MACHINE_END
#endif

#ifdef CONFIG_ARCH_PRPMC1100
MACHINE_START(IXCDP1100, "Intel IXCDP1100 Development Platform")
	/* Maintainer: MontaVista Software, Inc. */
	.phys_io	= IXP4XX_PERIPHERAL_BASE_PHYS,
	.io_pg_offst	= ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
	.map_io		= ixp4xx_map_io,
	.init_irq	= ixp4xx_init_irq,
	.timer		= &ixp4xx_timer,
	.boot_params	= 0x0100,
	.init_machine	= ixdp425_init,
MACHINE_END
#endif

#ifdef CONFIG_MACH_KIXRP435
MACHINE_START(KIXRP435, "Intel KIXRP435 Reference Platform")
	/* Maintainer: MontaVista Software, Inc. */
	.phys_io	= IXP4XX_PERIPHERAL_BASE_PHYS,
	.io_pg_offst	= ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
	.map_io		= ixp4xx_map_io,
	.init_irq	= ixp4xx_init_irq,
	.timer		= &ixp4xx_timer,
	.boot_params	= 0x0100,
	.init_machine	= ixdp425_init,
MACHINE_END
#endif
Commit	Line	Data
1da177e4 LT	1	/*
	2	* arch/arm/mach-ixp4xx/ixdp425-setup.c
	3	*
	4	* IXDP425/IXCDP1100 board-setup
	5	*
	6	* Copyright (C) 2003-2005 MontaVista Software, Inc.
	7	*
	8	* Author: Deepak Saxena <dsaxena@plexity.net>
	9	*/
	10
	11	#include <linux/kernel.h>
	12	#include <linux/init.h>
	13	#include <linux/device.h>
	14	#include <linux/serial.h>
	15	#include <linux/tty.h>
	16	#include <linux/serial_8250.h>
54e269ea	17	#include <linux/slab.h>
5a4a2387	18	#include <linux/i2c-gpio.h>
4ad48b4b VB	19	#include <linux/io.h>
	20	#include <linux/mtd/mtd.h>
	21	#include <linux/mtd/nand.h>
	22	#include <linux/mtd/partitions.h>
1da177e4 LT	23
	24	#include <asm/types.h>
	25	#include <asm/setup.h>
	26	#include <asm/memory.h>
a09e64fb	27	#include <mach/hardware.h>
1da177e4 LT	28	#include <asm/mach-types.h>
	29	#include <asm/irq.h>
	30	#include <asm/mach/arch.h>
	31	#include <asm/mach/flash.h>
4ad48b4b	32	#include <asm/delay.h>
1da177e4	33
1da177e4 LT	34	static struct flash_platform_data ixdp425_flash_data = {
	35	.map_name = "cfi_probe",
	36	.width = 2,
	37	};
	38
	39	static struct resource ixdp425_flash_resource = {
1da177e4 LT	40	.flags = IORESOURCE_MEM,
	41	};
	42
	43	static struct platform_device ixdp425_flash = {
	44	.name = "IXP4XX-Flash",
	45	.id = 0,
	46	.dev = {
	47	.platform_data = &ixdp425_flash_data,
	48	},
	49	.num_resources = 1,
	50	.resource = &ixdp425_flash_resource,
	51	};
	52
4ad48b4b VB	53	#if defined(CONFIG_MTD_NAND_PLATFORM) \|\| \
	54	defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
	55
	56	#ifdef CONFIG_MTD_PARTITIONS
	57	const char *part_probes[] = { "cmdlinepart", NULL };
	58
	59	static struct mtd_partition ixdp425_partitions[] = {
	60	{
	61	.name = "ixp400 NAND FS 0",
	62	.offset = 0,
	63	.size = SZ_8M
	64	}, {
	65	.name = "ixp400 NAND FS 1",
	66	.offset = MTDPART_OFS_APPEND,
	67	.size = MTDPART_SIZ_FULL
	68	},
	69	};
	70	#endif
	71
	72	static void
	73	ixdp425_flash_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
	74	{
	75	struct nand_chip *this = mtd->priv;
	76	int offset = (int)this->priv;
	77
	78	if (ctrl & NAND_CTRL_CHANGE) {
	79	if (ctrl & NAND_NCE) {
	80	gpio_line_set(IXDP425_NAND_NCE_PIN, IXP4XX_GPIO_LOW);
	81	udelay(5);
	82	} else
	83	gpio_line_set(IXDP425_NAND_NCE_PIN, IXP4XX_GPIO_HIGH);
	84
	85	offset = (ctrl & NAND_CLE) ? IXDP425_NAND_CMD_BYTE : 0;
	86	offset \|= (ctrl & NAND_ALE) ? IXDP425_NAND_ADDR_BYTE : 0;
	87	this->priv = (void *)offset;
	88	}
	89
	90	if (cmd != NAND_CMD_NONE)
	91	writeb(cmd, this->IO_ADDR_W + offset);
	92	}
	93
	94	static struct platform_nand_data ixdp425_flash_nand_data = {
	95	.chip = {
	96	.chip_delay = 30,
	97	.options = NAND_NO_AUTOINCR,
	98	#ifdef CONFIG_MTD_PARTITIONS
	99	.part_probe_types = part_probes,
	100	.partitions = ixdp425_partitions,
	101	.nr_partitions = ARRAY_SIZE(ixdp425_partitions),
	102	#endif
	103	},
	104	.ctrl = {
	105	.cmd_ctrl = ixdp425_flash_nand_cmd_ctrl
	106	}
	107	};
	108
	109	static struct resource ixdp425_flash_nand_resource = {
	110	.flags = IORESOURCE_MEM,
	111	};
	112
	113	static struct platform_device ixdp425_flash_nand = {
	114	.name = "gen_nand",
	115	.id = -1,
	116	.dev = {
117	.platform_data = &ixdp425_flash_nand_data,
118	},
119	.num_resources = 1,
120	.resource = &ixdp425_flash_nand_resource,
121	};
122	#endif /* CONFIG_MTD_NAND_PLATFORM */
123
5a4a2387	124	static struct i2c_gpio_platform_data ixdp425_i2c_gpio_data = {
1da177e4 LT	125	.sda_pin = IXDP425_SDA_PIN,
	126	.scl_pin = IXDP425_SCL_PIN,
	127	};
	128
5a4a2387 MLJ	129	static struct platform_device ixdp425_i2c_gpio = {
5a4a2387 MLJ	130	.name = "i2c-gpio",
1da177e4	131	.id = 0,
5a4a2387 MLJ	132	.dev = {
5a4a2387 MLJ	133	.platform_data = &ixdp425_i2c_gpio_data,
1da177e4	134	},
1da177e4 LT	135	};
	136
	137	static struct resource ixdp425_uart_resources[] = {
	138	{
	139	.start = IXP4XX_UART1_BASE_PHYS,
	140	.end = IXP4XX_UART1_BASE_PHYS + 0x0fff,
	141	.flags = IORESOURCE_MEM
	142	},
	143	{
	144	.start = IXP4XX_UART2_BASE_PHYS,
	145	.end = IXP4XX_UART2_BASE_PHYS + 0x0fff,
	146	.flags = IORESOURCE_MEM
	147	}
	148	};
	149
	150	static struct plat_serial8250_port ixdp425_uart_data[] = {
	151	{
	152	.mapbase = IXP4XX_UART1_BASE_PHYS,
	153	.membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
	154	.irq = IRQ_IXP4XX_UART1,
8c741ed7	155	.flags = UPF_BOOT_AUTOCONF \| UPF_SKIP_TEST,
1da177e4 LT	156	.iotype = UPIO_MEM,
	157	.regshift = 2,
	158	.uartclk = IXP4XX_UART_XTAL,
	159	},
	160	{
	161	.mapbase = IXP4XX_UART2_BASE_PHYS,
	162	.membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
a35d6c91	163	.irq = IRQ_IXP4XX_UART2,
8c741ed7	164	.flags = UPF_BOOT_AUTOCONF \| UPF_SKIP_TEST,
1da177e4 LT	165	.iotype = UPIO_MEM,
	166	.regshift = 2,
	167	.uartclk = IXP4XX_UART_XTAL,
bcaafbe4 SS	168	},
bcaafbe4 SS	169	{ },
1da177e4 LT	170	};
	171
	172	static struct platform_device ixdp425_uart = {
	173	.name = "serial8250",
6df29deb	174	.id = PLAT8250_DEV_PLATFORM,
1da177e4 LT	175	.dev.platform_data = ixdp425_uart_data,
	176	.num_resources = 2,
	177	.resource = ixdp425_uart_resources
	178	};
	179
78225913 RW	180	/* Built-in 10/100 Ethernet MAC interfaces */
	181	static struct eth_plat_info ixdp425_plat_eth[] = {
	182	{
	183	.phy = 0,
	184	.rxq = 3,
	185	.txreadyq = 20,
	186	}, {
	187	.phy = 1,
	188	.rxq = 4,
	189	.txreadyq = 21,
	190	}
	191	};
	192
	193	static struct platform_device ixdp425_eth[] = {
	194	{
	195	.name = "ixp4xx_eth",
	196	.id = IXP4XX_ETH_NPEB,
	197	.dev.platform_data = ixdp425_plat_eth,
	198	}, {
	199	.name = "ixp4xx_eth",
	200	.id = IXP4XX_ETH_NPEC,
	201	.dev.platform_data = ixdp425_plat_eth + 1,
	202	}
	203	};
	204
1da177e4	205	static struct platform_device *ixdp425_devices[] __initdata = {
5a4a2387	206	&ixdp425_i2c_gpio,
1da177e4	207	&ixdp425_flash,
4ad48b4b VB	208	#if defined(CONFIG_MTD_NAND_PLATFORM) \|\| \
	209	defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
	210	&ixdp425_flash_nand,
	211	#endif
78225913 RW	212	&ixdp425_uart,
	213	&ixdp425_eth[0],
	214	&ixdp425_eth[1],
1da177e4 LT	215	};
1da177e4 LT	216
1da177e4 LT	217	static void __init ixdp425_init(void)
	218	{
	219	ixp4xx_sys_init();
	220
54e269ea DS	221	ixdp425_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
	222	ixdp425_flash_resource.end =
	223	IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1;
1da177e4	224
4ad48b4b VB	225	#if defined(CONFIG_MTD_NAND_PLATFORM) \|\| \
	226	defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
	227	ixdp425_flash_nand_resource.start = IXP4XX_EXP_BUS_BASE(3),
	228	ixdp425_flash_nand_resource.end = IXP4XX_EXP_BUS_BASE(3) + 0x10 - 1;
	229
	230	gpio_line_config(IXDP425_NAND_NCE_PIN, IXP4XX_GPIO_OUT);
	231
	232	/* Configure expansion bus for NAND Flash */
	233	*IXP4XX_EXP_CS3 = IXP4XX_EXP_BUS_CS_EN \|
	234	IXP4XX_EXP_BUS_STROBE_T(1) \| /* extend by 1 clock */
	235	IXP4XX_EXP_BUS_CYCLES(0) \| /* Intel cycles */
	236	IXP4XX_EXP_BUS_SIZE(0) \| /* 512bytes addr space*/
	237	IXP4XX_EXP_BUS_WR_EN \|
	238	IXP4XX_EXP_BUS_BYTE_EN; /* 8 bit data bus */
	239	#endif
	240
45fba084 RS	241	if (cpu_is_ixp43x()) {
	242	ixdp425_uart.num_resources = 1;
	243	ixdp425_uart_data[1].flags = 0;
	244	}
	245
1da177e4 LT	246	platform_add_devices(ixdp425_devices, ARRAY_SIZE(ixdp425_devices));
	247	}
	248
b38708fc	249	#ifdef CONFIG_ARCH_IXDP425
1da177e4	250	MACHINE_START(IXDP425, "Intel IXDP425 Development Platform")
e9dea0c6	251	/* Maintainer: MontaVista Software, Inc. */
e9dea0c6 RK	252	.phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
e9dea0c6 RK	253	.io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
e605ecd7	254	.map_io = ixp4xx_map_io,
e9dea0c6	255	.init_irq = ixp4xx_init_irq,
1da177e4	256	.timer = &ixp4xx_timer,
e9dea0c6 RK	257	.boot_params = 0x0100,
e9dea0c6 RK	258	.init_machine = ixdp425_init,
1da177e4	259	MACHINE_END
e0a20089	260	#endif
1da177e4	261
e0a20089	262	#ifdef CONFIG_MACH_IXDP465
1da177e4	263	MACHINE_START(IXDP465, "Intel IXDP465 Development Platform")
e9dea0c6	264	/* Maintainer: MontaVista Software, Inc. */
e9dea0c6 RK	265	.phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
e9dea0c6 RK	266	.io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
e605ecd7	267	.map_io = ixp4xx_map_io,
e9dea0c6	268	.init_irq = ixp4xx_init_irq,
1da177e4	269	.timer = &ixp4xx_timer,
e9dea0c6 RK	270	.boot_params = 0x0100,
e9dea0c6 RK	271	.init_machine = ixdp425_init,
1da177e4	272	MACHINE_END
e0a20089	273	#endif
1da177e4	274
e0a20089	275	#ifdef CONFIG_ARCH_PRPMC1100
1da177e4	276	MACHINE_START(IXCDP1100, "Intel IXCDP1100 Development Platform")
e9dea0c6	277	/* Maintainer: MontaVista Software, Inc. */
e9dea0c6 RK	278	.phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
e9dea0c6 RK	279	.io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
e605ecd7	280	.map_io = ixp4xx_map_io,
e9dea0c6	281	.init_irq = ixp4xx_init_irq,
1da177e4	282	.timer = &ixp4xx_timer,
e9dea0c6 RK	283	.boot_params = 0x0100,
e9dea0c6 RK	284	.init_machine = ixdp425_init,
1da177e4	285	MACHINE_END
e0a20089	286	#endif
45fba084 RS	287
	288	#ifdef CONFIG_MACH_KIXRP435
	289	MACHINE_START(KIXRP435, "Intel KIXRP435 Reference Platform")
	290	/* Maintainer: MontaVista Software, Inc. */
	291	.phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
	292	.io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
	293	.map_io = ixp4xx_map_io,
	294	.init_irq = ixp4xx_init_irq,
	295	.timer = &ixp4xx_timer,
	296	.boot_params = 0x0100,
	297	.init_machine = ixdp425_init,
	298	MACHINE_END
	299	#endif