projects / mirror_ubuntu-jammy-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
| 3145d8a6 RW |
2 | /* |
| 3 | * arch/arm/mach-ixp4xx/nas100d-pci.c | |
| 4 | * | |
| 5 | * NAS 100d board-level PCI initialization | |
| 6 | * | |
| 7 | * based on ixdp425-pci.c: | |
| 8 | * Copyright (C) 2002 Intel Corporation. | |
| 9 | * Copyright (C) 2003-2004 MontaVista Software, Inc. | |
| 10 | * | |
| 11 | * Maintainer: http://www.nslu2-linux.org/ | |
| 3145d8a6 RW |
12 | */ |
| 13 | ||
| 3145d8a6 RW |
14 | #include <linux/pci.h> |
| 15 | #include <linux/init.h> | |
| 698dfe2b | 16 | #include <linux/irq.h> |
| 3145d8a6 RW |
17 | #include <asm/mach/pci.h> |
| 18 | #include <asm/mach-types.h> | |
| 19 | ||
| dc8ef8cd LW |
20 | #include "irqs.h" |
| 21 | ||
| 8d3fdf31 KH |
22 | #define MAX_DEV 3 |
| 23 | #define IRQ_LINES 3 | |
| 23fa6846 KH |
24 | |
| 25 | /* PCI controller GPIO to IRQ pin mappings */ | |
| 8d3fdf31 KH |
26 | #define INTA 11 |
| 27 | #define INTB 10 | |
| 28 | #define INTC 9 | |
| 29 | #define INTD 8 | |
| 30 | #define INTE 7 | |
| 23fa6846 | 31 | |
| 3145d8a6 RW |
32 | void __init nas100d_pci_preinit(void) |
| 33 | { | |
| 6845664a TG |
34 | irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); |
| 35 | irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); | |
| 36 | irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); | |
| 37 | irq_set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW); | |
| 38 | irq_set_irq_type(IXP4XX_GPIO_IRQ(INTE), IRQ_TYPE_LEVEL_LOW); | |
| 3145d8a6 RW |
39 | ixp4xx_pci_preinit(); |
| 40 | } | |
| 41 | ||
| d5341942 | 42 | static int __init nas100d_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) |
| 3145d8a6 | 43 | { |
| 8d3fdf31 KH |
44 | static int pci_irq_table[MAX_DEV][IRQ_LINES] = { |
| 45 | { IXP4XX_GPIO_IRQ(INTA), -1, -1 }, | |
| 46 | { IXP4XX_GPIO_IRQ(INTB), -1, -1 }, | |
| 47 | { IXP4XX_GPIO_IRQ(INTC), IXP4XX_GPIO_IRQ(INTD), | |
| 48 | IXP4XX_GPIO_IRQ(INTE) }, | |
| 3145d8a6 RW |
49 | }; |
| 50 | ||
| 8d3fdf31 KH |
51 | if (slot >= 1 && slot <= MAX_DEV && pin >= 1 && pin <= IRQ_LINES) |
| 52 | return pci_irq_table[slot - 1][pin - 1]; | |
| 3145d8a6 | 53 | |
| 8d3fdf31 | 54 | return -1; |
| 3145d8a6 RW |
55 | } |
| 56 | ||
| 57 | struct hw_pci __initdata nas100d_pci = { | |
| 58 | .nr_controllers = 1, | |
| c23bfc38 | 59 | .ops = &ixp4xx_ops, |
| 3145d8a6 | 60 | .preinit = nas100d_pci_preinit, |
| 3145d8a6 | 61 | .setup = ixp4xx_setup, |
| 3145d8a6 RW |
62 | .map_irq = nas100d_map_irq, |
| 63 | }; | |
| 64 | ||
| 65 | int __init nas100d_pci_init(void) | |
| 66 | { | |
| 67 | if (machine_is_nas100d()) | |
| 68 | pci_common_init(&nas100d_pci); | |
| 69 | ||
| 70 | return 0; | |
| 71 | } | |
| 72 | ||
| 73 | subsys_initcall(nas100d_pci_init); |