]>
Commit | Line | Data |
---|---|---|
651c74c7 SB |
1 | /* |
2 | * arch/arm/mach-kirkwood/common.c | |
3 | * | |
4 | * Core functions for Marvell Kirkwood SoCs | |
5 | * | |
6 | * This file is licensed under the terms of the GNU General Public | |
7 | * License version 2. This program is licensed "as is" without any | |
8 | * warranty of any kind, whether express or implied. | |
9 | */ | |
10 | ||
11 | #include <linux/kernel.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/platform_device.h> | |
14 | #include <linux/serial_8250.h> | |
651c74c7 | 15 | #include <linux/ata_platform.h> |
fb7b2d3f | 16 | #include <linux/mtd/nand.h> |
ee962723 | 17 | #include <linux/dma-mapping.h> |
2f129bf4 AL |
18 | #include <linux/clk-provider.h> |
19 | #include <linux/spinlock.h> | |
dcf1cece | 20 | #include <net/dsa.h> |
651c74c7 SB |
21 | #include <asm/page.h> |
22 | #include <asm/timex.h> | |
9c15364f | 23 | #include <asm/kexec.h> |
651c74c7 SB |
24 | #include <asm/mach/map.h> |
25 | #include <asm/mach/time.h> | |
a09e64fb | 26 | #include <mach/kirkwood.h> |
fdd8b079 | 27 | #include <mach/bridge-regs.h> |
49106c72 | 28 | #include <plat/audio.h> |
6f088f1d | 29 | #include <plat/cache-feroceon-l2.h> |
8235ee00 | 30 | #include <plat/mvsdio.h> |
6f088f1d | 31 | #include <plat/orion_nand.h> |
72053353 | 32 | #include <plat/ehci-orion.h> |
28a2b450 | 33 | #include <plat/common.h> |
6f088f1d | 34 | #include <plat/time.h> |
45173d5e | 35 | #include <plat/addr-map.h> |
2f129bf4 | 36 | #include <plat/mv_xor.h> |
651c74c7 SB |
37 | #include "common.h" |
38 | ||
39 | /***************************************************************************** | |
40 | * I/O Address Mapping | |
41 | ****************************************************************************/ | |
42 | static struct map_desc kirkwood_io_desc[] __initdata = { | |
43 | { | |
44 | .virtual = KIRKWOOD_PCIE_IO_VIRT_BASE, | |
45 | .pfn = __phys_to_pfn(KIRKWOOD_PCIE_IO_PHYS_BASE), | |
46 | .length = KIRKWOOD_PCIE_IO_SIZE, | |
47 | .type = MT_DEVICE, | |
ffd58bd2 SB |
48 | }, { |
49 | .virtual = KIRKWOOD_PCIE1_IO_VIRT_BASE, | |
50 | .pfn = __phys_to_pfn(KIRKWOOD_PCIE1_IO_PHYS_BASE), | |
51 | .length = KIRKWOOD_PCIE1_IO_SIZE, | |
52 | .type = MT_DEVICE, | |
651c74c7 SB |
53 | }, { |
54 | .virtual = KIRKWOOD_REGS_VIRT_BASE, | |
55 | .pfn = __phys_to_pfn(KIRKWOOD_REGS_PHYS_BASE), | |
56 | .length = KIRKWOOD_REGS_SIZE, | |
57 | .type = MT_DEVICE, | |
58 | }, | |
59 | }; | |
60 | ||
61 | void __init kirkwood_map_io(void) | |
62 | { | |
63 | iotable_init(kirkwood_io_desc, ARRAY_SIZE(kirkwood_io_desc)); | |
64 | } | |
65 | ||
2f129bf4 AL |
66 | /***************************************************************************** |
67 | * CLK tree | |
68 | ****************************************************************************/ | |
98d9986c | 69 | |
b5409430 SB |
70 | static void enable_sata0(void) |
71 | { | |
72 | /* Enable PLL and IVREF */ | |
73 | writel(readl(SATA0_PHY_MODE_2) | 0xf, SATA0_PHY_MODE_2); | |
74 | /* Enable PHY */ | |
75 | writel(readl(SATA0_IF_CTRL) & ~0x200, SATA0_IF_CTRL); | |
76 | } | |
77 | ||
98d9986c AL |
78 | static void disable_sata0(void) |
79 | { | |
80 | /* Disable PLL and IVREF */ | |
81 | writel(readl(SATA0_PHY_MODE_2) & ~0xf, SATA0_PHY_MODE_2); | |
82 | /* Disable PHY */ | |
83 | writel(readl(SATA0_IF_CTRL) | 0x200, SATA0_IF_CTRL); | |
84 | } | |
85 | ||
b5409430 SB |
86 | static void enable_sata1(void) |
87 | { | |
88 | /* Enable PLL and IVREF */ | |
89 | writel(readl(SATA1_PHY_MODE_2) | 0xf, SATA1_PHY_MODE_2); | |
90 | /* Enable PHY */ | |
91 | writel(readl(SATA1_IF_CTRL) & ~0x200, SATA1_IF_CTRL); | |
92 | } | |
93 | ||
98d9986c AL |
94 | static void disable_sata1(void) |
95 | { | |
96 | /* Disable PLL and IVREF */ | |
97 | writel(readl(SATA1_PHY_MODE_2) & ~0xf, SATA1_PHY_MODE_2); | |
98 | /* Disable PHY */ | |
99 | writel(readl(SATA1_IF_CTRL) | 0x200, SATA1_IF_CTRL); | |
100 | } | |
101 | ||
102 | static void disable_pcie0(void) | |
103 | { | |
104 | writel(readl(PCIE_LINK_CTRL) | 0x10, PCIE_LINK_CTRL); | |
105 | while (1) | |
106 | if (readl(PCIE_STATUS) & 0x1) | |
107 | break; | |
108 | writel(readl(PCIE_LINK_CTRL) & ~0x10, PCIE_LINK_CTRL); | |
109 | } | |
110 | ||
111 | static void disable_pcie1(void) | |
112 | { | |
113 | u32 dev, rev; | |
114 | ||
115 | kirkwood_pcie_id(&dev, &rev); | |
116 | ||
117 | if (dev == MV88F6282_DEV_ID) { | |
118 | writel(readl(PCIE1_LINK_CTRL) | 0x10, PCIE1_LINK_CTRL); | |
119 | while (1) | |
120 | if (readl(PCIE1_STATUS) & 0x1) | |
121 | break; | |
122 | writel(readl(PCIE1_LINK_CTRL) & ~0x10, PCIE1_LINK_CTRL); | |
123 | } | |
124 | } | |
125 | ||
b5409430 SB |
126 | /* An extended version of the gated clk. This calls fn_en()/fn_dis |
127 | * before enabling/disabling the clock. We use this to turn on/off | |
128 | * PHYs etc. */ | |
98d9986c AL |
129 | struct clk_gate_fn { |
130 | struct clk_gate gate; | |
b5409430 SB |
131 | void (*fn_en)(void); |
132 | void (*fn_dis)(void); | |
98d9986c AL |
133 | }; |
134 | ||
135 | #define to_clk_gate_fn(_gate) container_of(_gate, struct clk_gate_fn, gate) | |
136 | #define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw) | |
137 | ||
b5409430 SB |
138 | static int clk_gate_fn_enable(struct clk_hw *hw) |
139 | { | |
140 | struct clk_gate *gate = to_clk_gate(hw); | |
141 | struct clk_gate_fn *gate_fn = to_clk_gate_fn(gate); | |
142 | int ret; | |
143 | ||
144 | ret = clk_gate_ops.enable(hw); | |
145 | if (!ret && gate_fn->fn_en) | |
146 | gate_fn->fn_en(); | |
147 | ||
148 | return ret; | |
149 | } | |
150 | ||
98d9986c AL |
151 | static void clk_gate_fn_disable(struct clk_hw *hw) |
152 | { | |
153 | struct clk_gate *gate = to_clk_gate(hw); | |
154 | struct clk_gate_fn *gate_fn = to_clk_gate_fn(gate); | |
155 | ||
b5409430 SB |
156 | if (gate_fn->fn_dis) |
157 | gate_fn->fn_dis(); | |
98d9986c AL |
158 | |
159 | clk_gate_ops.disable(hw); | |
160 | } | |
161 | ||
162 | static struct clk_ops clk_gate_fn_ops; | |
163 | ||
164 | static struct clk __init *clk_register_gate_fn(struct device *dev, | |
165 | const char *name, | |
166 | const char *parent_name, unsigned long flags, | |
167 | void __iomem *reg, u8 bit_idx, | |
168 | u8 clk_gate_flags, spinlock_t *lock, | |
b5409430 | 169 | void (*fn_en)(void), void (*fn_dis)(void)) |
98d9986c AL |
170 | { |
171 | struct clk_gate_fn *gate_fn; | |
172 | struct clk *clk; | |
173 | struct clk_init_data init; | |
174 | ||
175 | gate_fn = kzalloc(sizeof(struct clk_gate_fn), GFP_KERNEL); | |
176 | if (!gate_fn) { | |
177 | pr_err("%s: could not allocate gated clk\n", __func__); | |
178 | return ERR_PTR(-ENOMEM); | |
179 | } | |
180 | ||
181 | init.name = name; | |
182 | init.ops = &clk_gate_fn_ops; | |
183 | init.flags = flags; | |
184 | init.parent_names = (parent_name ? &parent_name : NULL); | |
185 | init.num_parents = (parent_name ? 1 : 0); | |
186 | ||
187 | /* struct clk_gate assignments */ | |
188 | gate_fn->gate.reg = reg; | |
189 | gate_fn->gate.bit_idx = bit_idx; | |
190 | gate_fn->gate.flags = clk_gate_flags; | |
191 | gate_fn->gate.lock = lock; | |
192 | gate_fn->gate.hw.init = &init; | |
b5409430 SB |
193 | gate_fn->fn_en = fn_en; |
194 | gate_fn->fn_dis = fn_dis; | |
98d9986c | 195 | |
b5409430 SB |
196 | /* ops is the gate ops, but with our enable/disable functions */ |
197 | if (clk_gate_fn_ops.enable != clk_gate_fn_enable || | |
198 | clk_gate_fn_ops.disable != clk_gate_fn_disable) { | |
98d9986c | 199 | clk_gate_fn_ops = clk_gate_ops; |
b5409430 | 200 | clk_gate_fn_ops.enable = clk_gate_fn_enable; |
98d9986c AL |
201 | clk_gate_fn_ops.disable = clk_gate_fn_disable; |
202 | } | |
203 | ||
204 | clk = clk_register(dev, &gate_fn->gate.hw); | |
205 | ||
206 | if (IS_ERR(clk)) | |
207 | kfree(gate_fn); | |
208 | ||
209 | return clk; | |
210 | } | |
211 | ||
2f129bf4 AL |
212 | static DEFINE_SPINLOCK(gating_lock); |
213 | static struct clk *tclk; | |
214 | ||
215 | static struct clk __init *kirkwood_register_gate(const char *name, u8 bit_idx) | |
216 | { | |
98d9986c | 217 | return clk_register_gate(NULL, name, "tclk", 0, |
2f129bf4 AL |
218 | (void __iomem *)CLOCK_GATING_CTRL, |
219 | bit_idx, 0, &gating_lock); | |
220 | } | |
221 | ||
98d9986c AL |
222 | static struct clk __init *kirkwood_register_gate_fn(const char *name, |
223 | u8 bit_idx, | |
b5409430 SB |
224 | void (*fn_en)(void), |
225 | void (*fn_dis)(void)) | |
98d9986c AL |
226 | { |
227 | return clk_register_gate_fn(NULL, name, "tclk", 0, | |
228 | (void __iomem *)CLOCK_GATING_CTRL, | |
b5409430 | 229 | bit_idx, 0, &gating_lock, fn_en, fn_dis); |
98d9986c AL |
230 | } |
231 | ||
128789a8 AL |
232 | static struct clk *ge0, *ge1; |
233 | ||
2f129bf4 AL |
234 | void __init kirkwood_clk_init(void) |
235 | { | |
128789a8 | 236 | struct clk *runit, *sata0, *sata1, *usb0, *sdio; |
e919c716 | 237 | struct clk *crypto, *xor0, *xor1, *pex0, *pex1, *audio; |
4574b886 | 238 | |
2f129bf4 AL |
239 | tclk = clk_register_fixed_rate(NULL, "tclk", NULL, |
240 | CLK_IS_ROOT, kirkwood_tclk); | |
241 | ||
4574b886 | 242 | runit = kirkwood_register_gate("runit", CGC_BIT_RUNIT); |
452503eb AL |
243 | ge0 = kirkwood_register_gate("ge0", CGC_BIT_GE0); |
244 | ge1 = kirkwood_register_gate("ge1", CGC_BIT_GE1); | |
98d9986c | 245 | sata0 = kirkwood_register_gate_fn("sata0", CGC_BIT_SATA0, |
b5409430 | 246 | enable_sata0, disable_sata0); |
98d9986c | 247 | sata1 = kirkwood_register_gate_fn("sata1", CGC_BIT_SATA1, |
b5409430 | 248 | enable_sata1, disable_sata1); |
8c869eda | 249 | usb0 = kirkwood_register_gate("usb0", CGC_BIT_USB0); |
f4f7561e | 250 | sdio = kirkwood_register_gate("sdio", CGC_BIT_SDIO); |
1f80b126 | 251 | crypto = kirkwood_register_gate("crypto", CGC_BIT_CRYPTO); |
c510182b AL |
252 | xor0 = kirkwood_register_gate("xor0", CGC_BIT_XOR0); |
253 | xor1 = kirkwood_register_gate("xor1", CGC_BIT_XOR1); | |
98d9986c | 254 | pex0 = kirkwood_register_gate_fn("pex0", CGC_BIT_PEX0, |
b5409430 | 255 | NULL, disable_pcie0); |
98d9986c | 256 | pex1 = kirkwood_register_gate_fn("pex1", CGC_BIT_PEX1, |
b5409430 | 257 | NULL, disable_pcie1); |
e919c716 | 258 | audio = kirkwood_register_gate("audio", CGC_BIT_AUDIO); |
2f129bf4 AL |
259 | kirkwood_register_gate("tdm", CGC_BIT_TDM); |
260 | kirkwood_register_gate("tsu", CGC_BIT_TSU); | |
4574b886 AL |
261 | |
262 | /* clkdev entries, mapping clks to devices */ | |
263 | orion_clkdev_add(NULL, "orion_spi.0", runit); | |
264 | orion_clkdev_add(NULL, "orion_spi.1", runit); | |
452503eb AL |
265 | orion_clkdev_add(NULL, MV643XX_ETH_NAME ".0", ge0); |
266 | orion_clkdev_add(NULL, MV643XX_ETH_NAME ".1", ge1); | |
4f04be62 | 267 | orion_clkdev_add(NULL, "orion_wdt", tclk); |
eee98990 AL |
268 | orion_clkdev_add("0", "sata_mv.0", sata0); |
269 | orion_clkdev_add("1", "sata_mv.0", sata1); | |
8c869eda | 270 | orion_clkdev_add(NULL, "orion-ehci.0", usb0); |
9c2bd504 | 271 | orion_clkdev_add(NULL, "orion_nand", runit); |
f4f7561e | 272 | orion_clkdev_add(NULL, "mvsdio", sdio); |
1f80b126 | 273 | orion_clkdev_add(NULL, "mv_crypto", crypto); |
c510182b AL |
274 | orion_clkdev_add(NULL, MV_XOR_SHARED_NAME ".0", xor0); |
275 | orion_clkdev_add(NULL, MV_XOR_SHARED_NAME ".1", xor1); | |
27e53cfb AL |
276 | orion_clkdev_add("0", "pcie", pex0); |
277 | orion_clkdev_add("1", "pcie", pex1); | |
e919c716 | 278 | orion_clkdev_add(NULL, "kirkwood-i2s", audio); |
f479db44 AL |
279 | |
280 | /* Marvell says runit is used by SPI, UART, NAND, TWSI, ..., | |
281 | * so should never be gated. | |
282 | */ | |
283 | clk_prepare_enable(runit); | |
2f129bf4 AL |
284 | } |
285 | ||
651c74c7 SB |
286 | /***************************************************************************** |
287 | * EHCI0 | |
288 | ****************************************************************************/ | |
651c74c7 SB |
289 | void __init kirkwood_ehci_init(void) |
290 | { | |
72053353 | 291 | orion_ehci_init(USB_PHYS_BASE, IRQ_KIRKWOOD_USB, EHCI_PHY_NA); |
651c74c7 SB |
292 | } |
293 | ||
294 | ||
295 | /***************************************************************************** | |
296 | * GE00 | |
297 | ****************************************************************************/ | |
651c74c7 SB |
298 | void __init kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data) |
299 | { | |
db33f4de | 300 | orion_ge00_init(eth_data, |
7e3819d8 | 301 | GE00_PHYS_BASE, IRQ_KIRKWOOD_GE00_SUM, |
452503eb | 302 | IRQ_KIRKWOOD_GE00_ERR); |
128789a8 AL |
303 | /* The interface forgets the MAC address assigned by u-boot if |
304 | the clock is turned off, so claim the clk now. */ | |
305 | clk_prepare_enable(ge0); | |
651c74c7 SB |
306 | } |
307 | ||
308 | ||
d15fb9ef RS |
309 | /***************************************************************************** |
310 | * GE01 | |
311 | ****************************************************************************/ | |
d15fb9ef RS |
312 | void __init kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data) |
313 | { | |
db33f4de | 314 | orion_ge01_init(eth_data, |
7e3819d8 | 315 | GE01_PHYS_BASE, IRQ_KIRKWOOD_GE01_SUM, |
452503eb | 316 | IRQ_KIRKWOOD_GE01_ERR); |
128789a8 | 317 | clk_prepare_enable(ge1); |
d15fb9ef RS |
318 | } |
319 | ||
320 | ||
dcf1cece LB |
321 | /***************************************************************************** |
322 | * Ethernet switch | |
323 | ****************************************************************************/ | |
dcf1cece LB |
324 | void __init kirkwood_ge00_switch_init(struct dsa_platform_data *d, int irq) |
325 | { | |
7e3819d8 | 326 | orion_ge00_switch_init(d, irq); |
dcf1cece LB |
327 | } |
328 | ||
329 | ||
fb7b2d3f NP |
330 | /***************************************************************************** |
331 | * NAND flash | |
332 | ****************************************************************************/ | |
333 | static struct resource kirkwood_nand_resource = { | |
334 | .flags = IORESOURCE_MEM, | |
335 | .start = KIRKWOOD_NAND_MEM_PHYS_BASE, | |
336 | .end = KIRKWOOD_NAND_MEM_PHYS_BASE + | |
337 | KIRKWOOD_NAND_MEM_SIZE - 1, | |
338 | }; | |
339 | ||
340 | static struct orion_nand_data kirkwood_nand_data = { | |
341 | .cle = 0, | |
342 | .ale = 1, | |
343 | .width = 8, | |
344 | }; | |
345 | ||
346 | static struct platform_device kirkwood_nand_flash = { | |
347 | .name = "orion_nand", | |
348 | .id = -1, | |
349 | .dev = { | |
350 | .platform_data = &kirkwood_nand_data, | |
351 | }, | |
352 | .resource = &kirkwood_nand_resource, | |
353 | .num_resources = 1, | |
354 | }; | |
355 | ||
356 | void __init kirkwood_nand_init(struct mtd_partition *parts, int nr_parts, | |
357 | int chip_delay) | |
358 | { | |
359 | kirkwood_nand_data.parts = parts; | |
360 | kirkwood_nand_data.nr_parts = nr_parts; | |
361 | kirkwood_nand_data.chip_delay = chip_delay; | |
362 | platform_device_register(&kirkwood_nand_flash); | |
363 | } | |
364 | ||
010937ec BD |
365 | void __init kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts, |
366 | int (*dev_ready)(struct mtd_info *)) | |
367 | { | |
010937ec BD |
368 | kirkwood_nand_data.parts = parts; |
369 | kirkwood_nand_data.nr_parts = nr_parts; | |
370 | kirkwood_nand_data.dev_ready = dev_ready; | |
371 | platform_device_register(&kirkwood_nand_flash); | |
372 | } | |
fb7b2d3f | 373 | |
651c74c7 SB |
374 | /***************************************************************************** |
375 | * SoC RTC | |
376 | ****************************************************************************/ | |
e871b87a | 377 | static void __init kirkwood_rtc_init(void) |
651c74c7 | 378 | { |
4748058c | 379 | orion_rtc_init(RTC_PHYS_BASE, IRQ_KIRKWOOD_RTC); |
651c74c7 SB |
380 | } |
381 | ||
382 | ||
383 | /***************************************************************************** | |
384 | * SATA | |
385 | ****************************************************************************/ | |
651c74c7 SB |
386 | void __init kirkwood_sata_init(struct mv_sata_platform_data *sata_data) |
387 | { | |
db33f4de | 388 | orion_sata_init(sata_data, SATA_PHYS_BASE, IRQ_KIRKWOOD_SATA); |
651c74c7 SB |
389 | } |
390 | ||
391 | ||
8235ee00 NP |
392 | /***************************************************************************** |
393 | * SD/SDIO/MMC | |
394 | ****************************************************************************/ | |
395 | static struct resource mvsdio_resources[] = { | |
396 | [0] = { | |
397 | .start = SDIO_PHYS_BASE, | |
398 | .end = SDIO_PHYS_BASE + SZ_1K - 1, | |
399 | .flags = IORESOURCE_MEM, | |
400 | }, | |
401 | [1] = { | |
402 | .start = IRQ_KIRKWOOD_SDIO, | |
403 | .end = IRQ_KIRKWOOD_SDIO, | |
404 | .flags = IORESOURCE_IRQ, | |
405 | }, | |
406 | }; | |
407 | ||
5c602551 | 408 | static u64 mvsdio_dmamask = DMA_BIT_MASK(32); |
8235ee00 NP |
409 | |
410 | static struct platform_device kirkwood_sdio = { | |
411 | .name = "mvsdio", | |
412 | .id = -1, | |
413 | .dev = { | |
414 | .dma_mask = &mvsdio_dmamask, | |
5c602551 | 415 | .coherent_dma_mask = DMA_BIT_MASK(32), |
8235ee00 NP |
416 | }, |
417 | .num_resources = ARRAY_SIZE(mvsdio_resources), | |
418 | .resource = mvsdio_resources, | |
419 | }; | |
420 | ||
421 | void __init kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data) | |
422 | { | |
423 | u32 dev, rev; | |
424 | ||
425 | kirkwood_pcie_id(&dev, &rev); | |
1e4d2d3d | 426 | if (rev == 0 && dev != MV88F6282_DEV_ID) /* catch all Kirkwood Z0's */ |
8235ee00 NP |
427 | mvsdio_data->clock = 100000000; |
428 | else | |
429 | mvsdio_data->clock = 200000000; | |
8235ee00 NP |
430 | kirkwood_sdio.dev.platform_data = mvsdio_data; |
431 | platform_device_register(&kirkwood_sdio); | |
432 | } | |
433 | ||
434 | ||
18365d18 LB |
435 | /***************************************************************************** |
436 | * SPI | |
437 | ****************************************************************************/ | |
18365d18 LB |
438 | void __init kirkwood_spi_init() |
439 | { | |
4574b886 | 440 | orion_spi_init(SPI_PHYS_BASE); |
18365d18 LB |
441 | } |
442 | ||
443 | ||
6574e001 MM |
444 | /***************************************************************************** |
445 | * I2C | |
446 | ****************************************************************************/ | |
6574e001 MM |
447 | void __init kirkwood_i2c_init(void) |
448 | { | |
aac7ffa3 | 449 | orion_i2c_init(I2C_PHYS_BASE, IRQ_KIRKWOOD_TWSI, 8); |
6574e001 MM |
450 | } |
451 | ||
452 | ||
651c74c7 SB |
453 | /***************************************************************************** |
454 | * UART0 | |
455 | ****************************************************************************/ | |
651c74c7 SB |
456 | |
457 | void __init kirkwood_uart0_init(void) | |
458 | { | |
28a2b450 | 459 | orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE, |
74c33576 | 460 | IRQ_KIRKWOOD_UART_0, tclk); |
651c74c7 SB |
461 | } |
462 | ||
463 | ||
464 | /***************************************************************************** | |
465 | * UART1 | |
466 | ****************************************************************************/ | |
651c74c7 SB |
467 | void __init kirkwood_uart1_init(void) |
468 | { | |
28a2b450 | 469 | orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE, |
74c33576 | 470 | IRQ_KIRKWOOD_UART_1, tclk); |
651c74c7 SB |
471 | } |
472 | ||
ae5c8c83 NP |
473 | /***************************************************************************** |
474 | * Cryptographic Engines and Security Accelerator (CESA) | |
475 | ****************************************************************************/ | |
ae5c8c83 NP |
476 | void __init kirkwood_crypto_init(void) |
477 | { | |
44350061 AL |
478 | orion_crypto_init(CRYPTO_PHYS_BASE, KIRKWOOD_SRAM_PHYS_BASE, |
479 | KIRKWOOD_SRAM_SIZE, IRQ_KIRKWOOD_CRYPTO); | |
ae5c8c83 NP |
480 | } |
481 | ||
482 | ||
09c0ed2e SB |
483 | /***************************************************************************** |
484 | * XOR0 | |
485 | ****************************************************************************/ | |
2b45e05f | 486 | void __init kirkwood_xor0_init(void) |
09c0ed2e | 487 | { |
db33f4de | 488 | orion_xor0_init(XOR0_PHYS_BASE, XOR0_HIGH_PHYS_BASE, |
ee962723 | 489 | IRQ_KIRKWOOD_XOR_00, IRQ_KIRKWOOD_XOR_01); |
09c0ed2e SB |
490 | } |
491 | ||
492 | ||
493 | /***************************************************************************** | |
494 | * XOR1 | |
495 | ****************************************************************************/ | |
2b45e05f | 496 | void __init kirkwood_xor1_init(void) |
09c0ed2e | 497 | { |
ee962723 AL |
498 | orion_xor1_init(XOR1_PHYS_BASE, XOR1_HIGH_PHYS_BASE, |
499 | IRQ_KIRKWOOD_XOR_10, IRQ_KIRKWOOD_XOR_11); | |
09c0ed2e SB |
500 | } |
501 | ||
502 | ||
054bd3f0 TR |
503 | /***************************************************************************** |
504 | * Watchdog | |
505 | ****************************************************************************/ | |
2b45e05f | 506 | void __init kirkwood_wdt_init(void) |
054bd3f0 | 507 | { |
4f04be62 | 508 | orion_wdt_init(); |
054bd3f0 TR |
509 | } |
510 | ||
511 | ||
651c74c7 SB |
512 | /***************************************************************************** |
513 | * Time handling | |
514 | ****************************************************************************/ | |
4ee1f6b5 LB |
515 | void __init kirkwood_init_early(void) |
516 | { | |
517 | orion_time_set_base(TIMER_VIRT_BASE); | |
518 | } | |
519 | ||
79d4dd77 RS |
520 | int kirkwood_tclk; |
521 | ||
9b8ebfec | 522 | static int __init kirkwood_find_tclk(void) |
79d4dd77 | 523 | { |
b2b3dc2f RS |
524 | u32 dev, rev; |
525 | ||
526 | kirkwood_pcie_id(&dev, &rev); | |
1e4d2d3d | 527 | |
2fa0f939 SG |
528 | if (dev == MV88F6281_DEV_ID || dev == MV88F6282_DEV_ID) |
529 | if (((readl(SAMPLE_AT_RESET) >> 21) & 1) == 0) | |
530 | return 200000000; | |
b2b3dc2f | 531 | |
79d4dd77 RS |
532 | return 166666667; |
533 | } | |
534 | ||
6de95c19 | 535 | static void __init kirkwood_timer_init(void) |
651c74c7 | 536 | { |
79d4dd77 | 537 | kirkwood_tclk = kirkwood_find_tclk(); |
4ee1f6b5 LB |
538 | |
539 | orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR, | |
540 | IRQ_KIRKWOOD_BRIDGE, kirkwood_tclk); | |
651c74c7 SB |
541 | } |
542 | ||
543 | struct sys_timer kirkwood_timer = { | |
544 | .init = kirkwood_timer_init, | |
545 | }; | |
546 | ||
49106c72 | 547 | /***************************************************************************** |
548 | * Audio | |
549 | ****************************************************************************/ | |
550 | static struct resource kirkwood_i2s_resources[] = { | |
551 | [0] = { | |
552 | .start = AUDIO_PHYS_BASE, | |
553 | .end = AUDIO_PHYS_BASE + SZ_16K - 1, | |
554 | .flags = IORESOURCE_MEM, | |
555 | }, | |
556 | [1] = { | |
557 | .start = IRQ_KIRKWOOD_I2S, | |
558 | .end = IRQ_KIRKWOOD_I2S, | |
559 | .flags = IORESOURCE_IRQ, | |
560 | }, | |
561 | }; | |
562 | ||
563 | static struct kirkwood_asoc_platform_data kirkwood_i2s_data = { | |
49106c72 | 564 | .burst = 128, |
565 | }; | |
566 | ||
567 | static struct platform_device kirkwood_i2s_device = { | |
568 | .name = "kirkwood-i2s", | |
569 | .id = -1, | |
570 | .num_resources = ARRAY_SIZE(kirkwood_i2s_resources), | |
571 | .resource = kirkwood_i2s_resources, | |
572 | .dev = { | |
573 | .platform_data = &kirkwood_i2s_data, | |
574 | }, | |
575 | }; | |
576 | ||
f0fba2ad | 577 | static struct platform_device kirkwood_pcm_device = { |
c88e7b93 | 578 | .name = "kirkwood-pcm-audio", |
f0fba2ad LG |
579 | .id = -1, |
580 | }; | |
581 | ||
49106c72 | 582 | void __init kirkwood_audio_init(void) |
583 | { | |
49106c72 | 584 | platform_device_register(&kirkwood_i2s_device); |
f0fba2ad | 585 | platform_device_register(&kirkwood_pcm_device); |
49106c72 | 586 | } |
651c74c7 SB |
587 | |
588 | /***************************************************************************** | |
589 | * General | |
590 | ****************************************************************************/ | |
b2b3dc2f RS |
591 | /* |
592 | * Identify device ID and revision. | |
593 | */ | |
2b45e05f | 594 | char * __init kirkwood_id(void) |
651c74c7 | 595 | { |
b2b3dc2f RS |
596 | u32 dev, rev; |
597 | ||
598 | kirkwood_pcie_id(&dev, &rev); | |
599 | ||
600 | if (dev == MV88F6281_DEV_ID) { | |
601 | if (rev == MV88F6281_REV_Z0) | |
602 | return "MV88F6281-Z0"; | |
603 | else if (rev == MV88F6281_REV_A0) | |
604 | return "MV88F6281-A0"; | |
aec1bad3 SG |
605 | else if (rev == MV88F6281_REV_A1) |
606 | return "MV88F6281-A1"; | |
b2b3dc2f RS |
607 | else |
608 | return "MV88F6281-Rev-Unsupported"; | |
609 | } else if (dev == MV88F6192_DEV_ID) { | |
610 | if (rev == MV88F6192_REV_Z0) | |
611 | return "MV88F6192-Z0"; | |
612 | else if (rev == MV88F6192_REV_A0) | |
613 | return "MV88F6192-A0"; | |
1c2003a1 SB |
614 | else if (rev == MV88F6192_REV_A1) |
615 | return "MV88F6192-A1"; | |
b2b3dc2f RS |
616 | else |
617 | return "MV88F6192-Rev-Unsupported"; | |
618 | } else if (dev == MV88F6180_DEV_ID) { | |
619 | if (rev == MV88F6180_REV_A0) | |
620 | return "MV88F6180-Rev-A0"; | |
1c2003a1 SB |
621 | else if (rev == MV88F6180_REV_A1) |
622 | return "MV88F6180-Rev-A1"; | |
b2b3dc2f RS |
623 | else |
624 | return "MV88F6180-Rev-Unsupported"; | |
1e4d2d3d SB |
625 | } else if (dev == MV88F6282_DEV_ID) { |
626 | if (rev == MV88F6282_REV_A0) | |
627 | return "MV88F6282-Rev-A0"; | |
a87d89e7 MM |
628 | else if (rev == MV88F6282_REV_A1) |
629 | return "MV88F6282-Rev-A1"; | |
1e4d2d3d SB |
630 | else |
631 | return "MV88F6282-Rev-Unsupported"; | |
b2b3dc2f RS |
632 | } else { |
633 | return "Device-Unknown"; | |
651c74c7 | 634 | } |
651c74c7 SB |
635 | } |
636 | ||
2b45e05f | 637 | void __init kirkwood_l2_init(void) |
13387603 | 638 | { |
4360bb41 RS |
639 | #ifdef CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH |
640 | writel(readl(L2_CONFIG_REG) | L2_WRITETHROUGH, L2_CONFIG_REG); | |
641 | feroceon_l2_init(1); | |
642 | #else | |
643 | writel(readl(L2_CONFIG_REG) & ~L2_WRITETHROUGH, L2_CONFIG_REG); | |
644 | feroceon_l2_init(0); | |
645 | #endif | |
13387603 SB |
646 | } |
647 | ||
651c74c7 SB |
648 | void __init kirkwood_init(void) |
649 | { | |
650 | printk(KERN_INFO "Kirkwood: %s, TCLK=%d.\n", | |
79d4dd77 | 651 | kirkwood_id(), kirkwood_tclk); |
651c74c7 | 652 | |
2bf30108 LB |
653 | /* |
654 | * Disable propagation of mbus errors to the CPU local bus, | |
655 | * as this causes mbus errors (which can occur for example | |
656 | * for PCI aborts) to throw CPU aborts, which we're not set | |
657 | * up to deal with. | |
658 | */ | |
659 | writel(readl(CPU_CONFIG) & ~CPU_CONFIG_ERROR_PROP, CPU_CONFIG); | |
660 | ||
651c74c7 SB |
661 | kirkwood_setup_cpu_mbus(); |
662 | ||
663 | #ifdef CONFIG_CACHE_FEROCEON_L2 | |
4360bb41 | 664 | kirkwood_l2_init(); |
651c74c7 | 665 | #endif |
5b99d534 | 666 | |
2f129bf4 AL |
667 | /* Setup root of clk tree */ |
668 | kirkwood_clk_init(); | |
669 | ||
5b99d534 NP |
670 | /* internal devices that every board has */ |
671 | kirkwood_rtc_init(); | |
054bd3f0 | 672 | kirkwood_wdt_init(); |
5b99d534 NP |
673 | kirkwood_xor0_init(); |
674 | kirkwood_xor1_init(); | |
ae5c8c83 | 675 | kirkwood_crypto_init(); |
9c15364f EC |
676 | |
677 | #ifdef CONFIG_KEXEC | |
678 | kexec_reinit = kirkwood_enable_pcie; | |
679 | #endif | |
651c74c7 | 680 | } |
e8b2b7ba | 681 | |
cb15dff4 RK |
682 | void kirkwood_restart(char mode, const char *cmd) |
683 | { | |
684 | /* | |
685 | * Enable soft reset to assert RSTOUTn. | |
686 | */ | |
687 | writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK); | |
688 | ||
689 | /* | |
690 | * Assert soft reset. | |
691 | */ | |
692 | writel(SOFT_RESET, SYSTEM_SOFT_RESET); | |
693 | ||
694 | while (1) | |
695 | ; | |
696 | } |