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Commit | Line | Data |
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651c74c7 SB |
1 | /* |
2 | * arch/arm/mach-kirkwood/common.c | |
3 | * | |
4 | * Core functions for Marvell Kirkwood SoCs | |
5 | * | |
6 | * This file is licensed under the terms of the GNU General Public | |
7 | * License version 2. This program is licensed "as is" without any | |
8 | * warranty of any kind, whether express or implied. | |
9 | */ | |
10 | ||
11 | #include <linux/kernel.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/platform_device.h> | |
14 | #include <linux/serial_8250.h> | |
651c74c7 | 15 | #include <linux/ata_platform.h> |
fb7b2d3f | 16 | #include <linux/mtd/nand.h> |
ee962723 | 17 | #include <linux/dma-mapping.h> |
2f129bf4 AL |
18 | #include <linux/clk-provider.h> |
19 | #include <linux/spinlock.h> | |
dcf1cece | 20 | #include <net/dsa.h> |
651c74c7 SB |
21 | #include <asm/page.h> |
22 | #include <asm/timex.h> | |
9c15364f | 23 | #include <asm/kexec.h> |
651c74c7 SB |
24 | #include <asm/mach/map.h> |
25 | #include <asm/mach/time.h> | |
a09e64fb | 26 | #include <mach/kirkwood.h> |
fdd8b079 | 27 | #include <mach/bridge-regs.h> |
49106c72 | 28 | #include <plat/audio.h> |
6f088f1d | 29 | #include <plat/cache-feroceon-l2.h> |
8235ee00 | 30 | #include <plat/mvsdio.h> |
6f088f1d | 31 | #include <plat/orion_nand.h> |
72053353 | 32 | #include <plat/ehci-orion.h> |
28a2b450 | 33 | #include <plat/common.h> |
6f088f1d | 34 | #include <plat/time.h> |
45173d5e | 35 | #include <plat/addr-map.h> |
2f129bf4 | 36 | #include <plat/mv_xor.h> |
651c74c7 SB |
37 | #include "common.h" |
38 | ||
39 | /***************************************************************************** | |
40 | * I/O Address Mapping | |
41 | ****************************************************************************/ | |
42 | static struct map_desc kirkwood_io_desc[] __initdata = { | |
43 | { | |
44 | .virtual = KIRKWOOD_PCIE_IO_VIRT_BASE, | |
45 | .pfn = __phys_to_pfn(KIRKWOOD_PCIE_IO_PHYS_BASE), | |
46 | .length = KIRKWOOD_PCIE_IO_SIZE, | |
47 | .type = MT_DEVICE, | |
ffd58bd2 SB |
48 | }, { |
49 | .virtual = KIRKWOOD_PCIE1_IO_VIRT_BASE, | |
50 | .pfn = __phys_to_pfn(KIRKWOOD_PCIE1_IO_PHYS_BASE), | |
51 | .length = KIRKWOOD_PCIE1_IO_SIZE, | |
52 | .type = MT_DEVICE, | |
651c74c7 SB |
53 | }, { |
54 | .virtual = KIRKWOOD_REGS_VIRT_BASE, | |
55 | .pfn = __phys_to_pfn(KIRKWOOD_REGS_PHYS_BASE), | |
56 | .length = KIRKWOOD_REGS_SIZE, | |
57 | .type = MT_DEVICE, | |
58 | }, | |
59 | }; | |
60 | ||
61 | void __init kirkwood_map_io(void) | |
62 | { | |
63 | iotable_init(kirkwood_io_desc, ARRAY_SIZE(kirkwood_io_desc)); | |
64 | } | |
65 | ||
e8b2b7ba RK |
66 | /* |
67 | * Default clock control bits. Any bit _not_ set in this variable | |
68 | * will be cleared from the hardware after platform devices have been | |
69 | * registered. Some reserved bits must be set to 1. | |
70 | */ | |
71 | unsigned int kirkwood_clk_ctrl = CGC_DUNIT | CGC_RESERVED; | |
7e3819d8 | 72 | |
651c74c7 | 73 | |
2f129bf4 AL |
74 | /***************************************************************************** |
75 | * CLK tree | |
76 | ****************************************************************************/ | |
77 | static DEFINE_SPINLOCK(gating_lock); | |
78 | static struct clk *tclk; | |
79 | ||
80 | static struct clk __init *kirkwood_register_gate(const char *name, u8 bit_idx) | |
81 | { | |
82 | return clk_register_gate(NULL, name, "tclk", CLK_IGNORE_UNUSED, | |
83 | (void __iomem *)CLOCK_GATING_CTRL, | |
84 | bit_idx, 0, &gating_lock); | |
85 | } | |
86 | ||
87 | void __init kirkwood_clk_init(void) | |
88 | { | |
f4f7561e | 89 | struct clk *runit, *ge0, *ge1, *sata0, *sata1, *usb0, *sdio; |
c510182b | 90 | struct clk *crypto, *xor0, *xor1; |
4574b886 | 91 | |
2f129bf4 AL |
92 | tclk = clk_register_fixed_rate(NULL, "tclk", NULL, |
93 | CLK_IS_ROOT, kirkwood_tclk); | |
94 | ||
4574b886 | 95 | runit = kirkwood_register_gate("runit", CGC_BIT_RUNIT); |
452503eb AL |
96 | ge0 = kirkwood_register_gate("ge0", CGC_BIT_GE0); |
97 | ge1 = kirkwood_register_gate("ge1", CGC_BIT_GE1); | |
eee98990 AL |
98 | sata0 = kirkwood_register_gate("sata0", CGC_BIT_SATA0); |
99 | sata1 = kirkwood_register_gate("sata1", CGC_BIT_SATA1); | |
8c869eda | 100 | usb0 = kirkwood_register_gate("usb0", CGC_BIT_USB0); |
f4f7561e | 101 | sdio = kirkwood_register_gate("sdio", CGC_BIT_SDIO); |
1f80b126 | 102 | crypto = kirkwood_register_gate("crypto", CGC_BIT_CRYPTO); |
c510182b AL |
103 | xor0 = kirkwood_register_gate("xor0", CGC_BIT_XOR0); |
104 | xor1 = kirkwood_register_gate("xor1", CGC_BIT_XOR1); | |
2f129bf4 AL |
105 | kirkwood_register_gate("pex0", CGC_BIT_PEX0); |
106 | kirkwood_register_gate("pex1", CGC_BIT_PEX1); | |
107 | kirkwood_register_gate("audio", CGC_BIT_AUDIO); | |
108 | kirkwood_register_gate("tdm", CGC_BIT_TDM); | |
109 | kirkwood_register_gate("tsu", CGC_BIT_TSU); | |
4574b886 AL |
110 | |
111 | /* clkdev entries, mapping clks to devices */ | |
112 | orion_clkdev_add(NULL, "orion_spi.0", runit); | |
113 | orion_clkdev_add(NULL, "orion_spi.1", runit); | |
452503eb AL |
114 | orion_clkdev_add(NULL, MV643XX_ETH_NAME ".0", ge0); |
115 | orion_clkdev_add(NULL, MV643XX_ETH_NAME ".1", ge1); | |
4f04be62 | 116 | orion_clkdev_add(NULL, "orion_wdt", tclk); |
eee98990 AL |
117 | orion_clkdev_add("0", "sata_mv.0", sata0); |
118 | orion_clkdev_add("1", "sata_mv.0", sata1); | |
8c869eda | 119 | orion_clkdev_add(NULL, "orion-ehci.0", usb0); |
9c2bd504 | 120 | orion_clkdev_add(NULL, "orion_nand", runit); |
f4f7561e | 121 | orion_clkdev_add(NULL, "mvsdio", sdio); |
1f80b126 | 122 | orion_clkdev_add(NULL, "mv_crypto", crypto); |
c510182b AL |
123 | orion_clkdev_add(NULL, MV_XOR_SHARED_NAME ".0", xor0); |
124 | orion_clkdev_add(NULL, MV_XOR_SHARED_NAME ".1", xor1); | |
2f129bf4 AL |
125 | } |
126 | ||
651c74c7 SB |
127 | /***************************************************************************** |
128 | * EHCI0 | |
129 | ****************************************************************************/ | |
651c74c7 SB |
130 | void __init kirkwood_ehci_init(void) |
131 | { | |
e8b2b7ba | 132 | kirkwood_clk_ctrl |= CGC_USB0; |
72053353 | 133 | orion_ehci_init(USB_PHYS_BASE, IRQ_KIRKWOOD_USB, EHCI_PHY_NA); |
651c74c7 SB |
134 | } |
135 | ||
136 | ||
137 | /***************************************************************************** | |
138 | * GE00 | |
139 | ****************************************************************************/ | |
651c74c7 SB |
140 | void __init kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data) |
141 | { | |
e8b2b7ba | 142 | kirkwood_clk_ctrl |= CGC_GE0; |
651c74c7 | 143 | |
db33f4de | 144 | orion_ge00_init(eth_data, |
7e3819d8 | 145 | GE00_PHYS_BASE, IRQ_KIRKWOOD_GE00_SUM, |
452503eb | 146 | IRQ_KIRKWOOD_GE00_ERR); |
651c74c7 SB |
147 | } |
148 | ||
149 | ||
d15fb9ef RS |
150 | /***************************************************************************** |
151 | * GE01 | |
152 | ****************************************************************************/ | |
d15fb9ef RS |
153 | void __init kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data) |
154 | { | |
7e3819d8 | 155 | |
e8b2b7ba | 156 | kirkwood_clk_ctrl |= CGC_GE1; |
d15fb9ef | 157 | |
db33f4de | 158 | orion_ge01_init(eth_data, |
7e3819d8 | 159 | GE01_PHYS_BASE, IRQ_KIRKWOOD_GE01_SUM, |
452503eb | 160 | IRQ_KIRKWOOD_GE01_ERR); |
d15fb9ef RS |
161 | } |
162 | ||
163 | ||
dcf1cece LB |
164 | /***************************************************************************** |
165 | * Ethernet switch | |
166 | ****************************************************************************/ | |
dcf1cece LB |
167 | void __init kirkwood_ge00_switch_init(struct dsa_platform_data *d, int irq) |
168 | { | |
7e3819d8 | 169 | orion_ge00_switch_init(d, irq); |
dcf1cece LB |
170 | } |
171 | ||
172 | ||
fb7b2d3f NP |
173 | /***************************************************************************** |
174 | * NAND flash | |
175 | ****************************************************************************/ | |
176 | static struct resource kirkwood_nand_resource = { | |
177 | .flags = IORESOURCE_MEM, | |
178 | .start = KIRKWOOD_NAND_MEM_PHYS_BASE, | |
179 | .end = KIRKWOOD_NAND_MEM_PHYS_BASE + | |
180 | KIRKWOOD_NAND_MEM_SIZE - 1, | |
181 | }; | |
182 | ||
183 | static struct orion_nand_data kirkwood_nand_data = { | |
184 | .cle = 0, | |
185 | .ale = 1, | |
186 | .width = 8, | |
187 | }; | |
188 | ||
189 | static struct platform_device kirkwood_nand_flash = { | |
190 | .name = "orion_nand", | |
191 | .id = -1, | |
192 | .dev = { | |
193 | .platform_data = &kirkwood_nand_data, | |
194 | }, | |
195 | .resource = &kirkwood_nand_resource, | |
196 | .num_resources = 1, | |
197 | }; | |
198 | ||
199 | void __init kirkwood_nand_init(struct mtd_partition *parts, int nr_parts, | |
200 | int chip_delay) | |
201 | { | |
e8b2b7ba | 202 | kirkwood_clk_ctrl |= CGC_RUNIT; |
fb7b2d3f NP |
203 | kirkwood_nand_data.parts = parts; |
204 | kirkwood_nand_data.nr_parts = nr_parts; | |
205 | kirkwood_nand_data.chip_delay = chip_delay; | |
206 | platform_device_register(&kirkwood_nand_flash); | |
207 | } | |
208 | ||
010937ec BD |
209 | void __init kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts, |
210 | int (*dev_ready)(struct mtd_info *)) | |
211 | { | |
212 | kirkwood_clk_ctrl |= CGC_RUNIT; | |
213 | kirkwood_nand_data.parts = parts; | |
214 | kirkwood_nand_data.nr_parts = nr_parts; | |
215 | kirkwood_nand_data.dev_ready = dev_ready; | |
216 | platform_device_register(&kirkwood_nand_flash); | |
217 | } | |
fb7b2d3f | 218 | |
651c74c7 SB |
219 | /***************************************************************************** |
220 | * SoC RTC | |
221 | ****************************************************************************/ | |
e871b87a | 222 | static void __init kirkwood_rtc_init(void) |
651c74c7 | 223 | { |
4748058c | 224 | orion_rtc_init(RTC_PHYS_BASE, IRQ_KIRKWOOD_RTC); |
651c74c7 SB |
225 | } |
226 | ||
227 | ||
228 | /***************************************************************************** | |
229 | * SATA | |
230 | ****************************************************************************/ | |
651c74c7 SB |
231 | void __init kirkwood_sata_init(struct mv_sata_platform_data *sata_data) |
232 | { | |
e8b2b7ba RK |
233 | kirkwood_clk_ctrl |= CGC_SATA0; |
234 | if (sata_data->n_ports > 1) | |
235 | kirkwood_clk_ctrl |= CGC_SATA1; | |
9e613f8a | 236 | |
db33f4de | 237 | orion_sata_init(sata_data, SATA_PHYS_BASE, IRQ_KIRKWOOD_SATA); |
651c74c7 SB |
238 | } |
239 | ||
240 | ||
8235ee00 NP |
241 | /***************************************************************************** |
242 | * SD/SDIO/MMC | |
243 | ****************************************************************************/ | |
244 | static struct resource mvsdio_resources[] = { | |
245 | [0] = { | |
246 | .start = SDIO_PHYS_BASE, | |
247 | .end = SDIO_PHYS_BASE + SZ_1K - 1, | |
248 | .flags = IORESOURCE_MEM, | |
249 | }, | |
250 | [1] = { | |
251 | .start = IRQ_KIRKWOOD_SDIO, | |
252 | .end = IRQ_KIRKWOOD_SDIO, | |
253 | .flags = IORESOURCE_IRQ, | |
254 | }, | |
255 | }; | |
256 | ||
5c602551 | 257 | static u64 mvsdio_dmamask = DMA_BIT_MASK(32); |
8235ee00 NP |
258 | |
259 | static struct platform_device kirkwood_sdio = { | |
260 | .name = "mvsdio", | |
261 | .id = -1, | |
262 | .dev = { | |
263 | .dma_mask = &mvsdio_dmamask, | |
5c602551 | 264 | .coherent_dma_mask = DMA_BIT_MASK(32), |
8235ee00 NP |
265 | }, |
266 | .num_resources = ARRAY_SIZE(mvsdio_resources), | |
267 | .resource = mvsdio_resources, | |
268 | }; | |
269 | ||
270 | void __init kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data) | |
271 | { | |
272 | u32 dev, rev; | |
273 | ||
274 | kirkwood_pcie_id(&dev, &rev); | |
1e4d2d3d | 275 | if (rev == 0 && dev != MV88F6282_DEV_ID) /* catch all Kirkwood Z0's */ |
8235ee00 NP |
276 | mvsdio_data->clock = 100000000; |
277 | else | |
278 | mvsdio_data->clock = 200000000; | |
e8b2b7ba | 279 | kirkwood_clk_ctrl |= CGC_SDIO; |
8235ee00 NP |
280 | kirkwood_sdio.dev.platform_data = mvsdio_data; |
281 | platform_device_register(&kirkwood_sdio); | |
282 | } | |
283 | ||
284 | ||
18365d18 LB |
285 | /***************************************************************************** |
286 | * SPI | |
287 | ****************************************************************************/ | |
18365d18 LB |
288 | void __init kirkwood_spi_init() |
289 | { | |
e8b2b7ba | 290 | kirkwood_clk_ctrl |= CGC_RUNIT; |
4574b886 | 291 | orion_spi_init(SPI_PHYS_BASE); |
18365d18 LB |
292 | } |
293 | ||
294 | ||
6574e001 MM |
295 | /***************************************************************************** |
296 | * I2C | |
297 | ****************************************************************************/ | |
6574e001 MM |
298 | void __init kirkwood_i2c_init(void) |
299 | { | |
aac7ffa3 | 300 | orion_i2c_init(I2C_PHYS_BASE, IRQ_KIRKWOOD_TWSI, 8); |
6574e001 MM |
301 | } |
302 | ||
303 | ||
651c74c7 SB |
304 | /***************************************************************************** |
305 | * UART0 | |
306 | ****************************************************************************/ | |
651c74c7 SB |
307 | |
308 | void __init kirkwood_uart0_init(void) | |
309 | { | |
28a2b450 | 310 | orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE, |
74c33576 | 311 | IRQ_KIRKWOOD_UART_0, tclk); |
651c74c7 SB |
312 | } |
313 | ||
314 | ||
315 | /***************************************************************************** | |
316 | * UART1 | |
317 | ****************************************************************************/ | |
651c74c7 SB |
318 | void __init kirkwood_uart1_init(void) |
319 | { | |
28a2b450 | 320 | orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE, |
74c33576 | 321 | IRQ_KIRKWOOD_UART_1, tclk); |
651c74c7 SB |
322 | } |
323 | ||
ae5c8c83 NP |
324 | /***************************************************************************** |
325 | * Cryptographic Engines and Security Accelerator (CESA) | |
326 | ****************************************************************************/ | |
ae5c8c83 NP |
327 | void __init kirkwood_crypto_init(void) |
328 | { | |
329 | kirkwood_clk_ctrl |= CGC_CRYPTO; | |
44350061 AL |
330 | orion_crypto_init(CRYPTO_PHYS_BASE, KIRKWOOD_SRAM_PHYS_BASE, |
331 | KIRKWOOD_SRAM_SIZE, IRQ_KIRKWOOD_CRYPTO); | |
ae5c8c83 NP |
332 | } |
333 | ||
334 | ||
09c0ed2e SB |
335 | /***************************************************************************** |
336 | * XOR0 | |
337 | ****************************************************************************/ | |
2b45e05f | 338 | void __init kirkwood_xor0_init(void) |
09c0ed2e | 339 | { |
e8b2b7ba | 340 | kirkwood_clk_ctrl |= CGC_XOR0; |
db33f4de | 341 | orion_xor0_init(XOR0_PHYS_BASE, XOR0_HIGH_PHYS_BASE, |
ee962723 | 342 | IRQ_KIRKWOOD_XOR_00, IRQ_KIRKWOOD_XOR_01); |
09c0ed2e SB |
343 | } |
344 | ||
345 | ||
346 | /***************************************************************************** | |
347 | * XOR1 | |
348 | ****************************************************************************/ | |
2b45e05f | 349 | void __init kirkwood_xor1_init(void) |
09c0ed2e | 350 | { |
e8b2b7ba | 351 | kirkwood_clk_ctrl |= CGC_XOR1; |
ee962723 AL |
352 | orion_xor1_init(XOR1_PHYS_BASE, XOR1_HIGH_PHYS_BASE, |
353 | IRQ_KIRKWOOD_XOR_10, IRQ_KIRKWOOD_XOR_11); | |
09c0ed2e SB |
354 | } |
355 | ||
356 | ||
054bd3f0 TR |
357 | /***************************************************************************** |
358 | * Watchdog | |
359 | ****************************************************************************/ | |
2b45e05f | 360 | void __init kirkwood_wdt_init(void) |
054bd3f0 | 361 | { |
4f04be62 | 362 | orion_wdt_init(); |
054bd3f0 TR |
363 | } |
364 | ||
365 | ||
651c74c7 SB |
366 | /***************************************************************************** |
367 | * Time handling | |
368 | ****************************************************************************/ | |
4ee1f6b5 LB |
369 | void __init kirkwood_init_early(void) |
370 | { | |
371 | orion_time_set_base(TIMER_VIRT_BASE); | |
372 | } | |
373 | ||
79d4dd77 RS |
374 | int kirkwood_tclk; |
375 | ||
9b8ebfec | 376 | static int __init kirkwood_find_tclk(void) |
79d4dd77 | 377 | { |
b2b3dc2f RS |
378 | u32 dev, rev; |
379 | ||
380 | kirkwood_pcie_id(&dev, &rev); | |
1e4d2d3d | 381 | |
2fa0f939 SG |
382 | if (dev == MV88F6281_DEV_ID || dev == MV88F6282_DEV_ID) |
383 | if (((readl(SAMPLE_AT_RESET) >> 21) & 1) == 0) | |
384 | return 200000000; | |
b2b3dc2f | 385 | |
79d4dd77 RS |
386 | return 166666667; |
387 | } | |
388 | ||
6de95c19 | 389 | static void __init kirkwood_timer_init(void) |
651c74c7 | 390 | { |
79d4dd77 | 391 | kirkwood_tclk = kirkwood_find_tclk(); |
4ee1f6b5 LB |
392 | |
393 | orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR, | |
394 | IRQ_KIRKWOOD_BRIDGE, kirkwood_tclk); | |
651c74c7 SB |
395 | } |
396 | ||
397 | struct sys_timer kirkwood_timer = { | |
398 | .init = kirkwood_timer_init, | |
399 | }; | |
400 | ||
49106c72 | 401 | /***************************************************************************** |
402 | * Audio | |
403 | ****************************************************************************/ | |
404 | static struct resource kirkwood_i2s_resources[] = { | |
405 | [0] = { | |
406 | .start = AUDIO_PHYS_BASE, | |
407 | .end = AUDIO_PHYS_BASE + SZ_16K - 1, | |
408 | .flags = IORESOURCE_MEM, | |
409 | }, | |
410 | [1] = { | |
411 | .start = IRQ_KIRKWOOD_I2S, | |
412 | .end = IRQ_KIRKWOOD_I2S, | |
413 | .flags = IORESOURCE_IRQ, | |
414 | }, | |
415 | }; | |
416 | ||
417 | static struct kirkwood_asoc_platform_data kirkwood_i2s_data = { | |
49106c72 | 418 | .burst = 128, |
419 | }; | |
420 | ||
421 | static struct platform_device kirkwood_i2s_device = { | |
422 | .name = "kirkwood-i2s", | |
423 | .id = -1, | |
424 | .num_resources = ARRAY_SIZE(kirkwood_i2s_resources), | |
425 | .resource = kirkwood_i2s_resources, | |
426 | .dev = { | |
427 | .platform_data = &kirkwood_i2s_data, | |
428 | }, | |
429 | }; | |
430 | ||
f0fba2ad | 431 | static struct platform_device kirkwood_pcm_device = { |
c88e7b93 | 432 | .name = "kirkwood-pcm-audio", |
f0fba2ad LG |
433 | .id = -1, |
434 | }; | |
435 | ||
49106c72 | 436 | void __init kirkwood_audio_init(void) |
437 | { | |
438 | kirkwood_clk_ctrl |= CGC_AUDIO; | |
439 | platform_device_register(&kirkwood_i2s_device); | |
f0fba2ad | 440 | platform_device_register(&kirkwood_pcm_device); |
49106c72 | 441 | } |
651c74c7 SB |
442 | |
443 | /***************************************************************************** | |
444 | * General | |
445 | ****************************************************************************/ | |
b2b3dc2f RS |
446 | /* |
447 | * Identify device ID and revision. | |
448 | */ | |
2b45e05f | 449 | char * __init kirkwood_id(void) |
651c74c7 | 450 | { |
b2b3dc2f RS |
451 | u32 dev, rev; |
452 | ||
453 | kirkwood_pcie_id(&dev, &rev); | |
454 | ||
455 | if (dev == MV88F6281_DEV_ID) { | |
456 | if (rev == MV88F6281_REV_Z0) | |
457 | return "MV88F6281-Z0"; | |
458 | else if (rev == MV88F6281_REV_A0) | |
459 | return "MV88F6281-A0"; | |
aec1bad3 SG |
460 | else if (rev == MV88F6281_REV_A1) |
461 | return "MV88F6281-A1"; | |
b2b3dc2f RS |
462 | else |
463 | return "MV88F6281-Rev-Unsupported"; | |
464 | } else if (dev == MV88F6192_DEV_ID) { | |
465 | if (rev == MV88F6192_REV_Z0) | |
466 | return "MV88F6192-Z0"; | |
467 | else if (rev == MV88F6192_REV_A0) | |
468 | return "MV88F6192-A0"; | |
1c2003a1 SB |
469 | else if (rev == MV88F6192_REV_A1) |
470 | return "MV88F6192-A1"; | |
b2b3dc2f RS |
471 | else |
472 | return "MV88F6192-Rev-Unsupported"; | |
473 | } else if (dev == MV88F6180_DEV_ID) { | |
474 | if (rev == MV88F6180_REV_A0) | |
475 | return "MV88F6180-Rev-A0"; | |
1c2003a1 SB |
476 | else if (rev == MV88F6180_REV_A1) |
477 | return "MV88F6180-Rev-A1"; | |
b2b3dc2f RS |
478 | else |
479 | return "MV88F6180-Rev-Unsupported"; | |
1e4d2d3d SB |
480 | } else if (dev == MV88F6282_DEV_ID) { |
481 | if (rev == MV88F6282_REV_A0) | |
482 | return "MV88F6282-Rev-A0"; | |
a87d89e7 MM |
483 | else if (rev == MV88F6282_REV_A1) |
484 | return "MV88F6282-Rev-A1"; | |
1e4d2d3d SB |
485 | else |
486 | return "MV88F6282-Rev-Unsupported"; | |
b2b3dc2f RS |
487 | } else { |
488 | return "Device-Unknown"; | |
651c74c7 | 489 | } |
651c74c7 SB |
490 | } |
491 | ||
2b45e05f | 492 | void __init kirkwood_l2_init(void) |
13387603 | 493 | { |
4360bb41 RS |
494 | #ifdef CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH |
495 | writel(readl(L2_CONFIG_REG) | L2_WRITETHROUGH, L2_CONFIG_REG); | |
496 | feroceon_l2_init(1); | |
497 | #else | |
498 | writel(readl(L2_CONFIG_REG) & ~L2_WRITETHROUGH, L2_CONFIG_REG); | |
499 | feroceon_l2_init(0); | |
500 | #endif | |
13387603 SB |
501 | } |
502 | ||
651c74c7 SB |
503 | void __init kirkwood_init(void) |
504 | { | |
505 | printk(KERN_INFO "Kirkwood: %s, TCLK=%d.\n", | |
79d4dd77 | 506 | kirkwood_id(), kirkwood_tclk); |
651c74c7 | 507 | |
2bf30108 LB |
508 | /* |
509 | * Disable propagation of mbus errors to the CPU local bus, | |
510 | * as this causes mbus errors (which can occur for example | |
511 | * for PCI aborts) to throw CPU aborts, which we're not set | |
512 | * up to deal with. | |
513 | */ | |
514 | writel(readl(CPU_CONFIG) & ~CPU_CONFIG_ERROR_PROP, CPU_CONFIG); | |
515 | ||
651c74c7 SB |
516 | kirkwood_setup_cpu_mbus(); |
517 | ||
518 | #ifdef CONFIG_CACHE_FEROCEON_L2 | |
4360bb41 | 519 | kirkwood_l2_init(); |
651c74c7 | 520 | #endif |
5b99d534 | 521 | |
2f129bf4 AL |
522 | /* Setup root of clk tree */ |
523 | kirkwood_clk_init(); | |
524 | ||
5b99d534 NP |
525 | /* internal devices that every board has */ |
526 | kirkwood_rtc_init(); | |
054bd3f0 | 527 | kirkwood_wdt_init(); |
5b99d534 NP |
528 | kirkwood_xor0_init(); |
529 | kirkwood_xor1_init(); | |
ae5c8c83 | 530 | kirkwood_crypto_init(); |
9c15364f EC |
531 | |
532 | #ifdef CONFIG_KEXEC | |
533 | kexec_reinit = kirkwood_enable_pcie; | |
534 | #endif | |
651c74c7 | 535 | } |
e8b2b7ba RK |
536 | |
537 | static int __init kirkwood_clock_gate(void) | |
538 | { | |
539 | unsigned int curr = readl(CLOCK_GATING_CTRL); | |
ffd58bd2 | 540 | u32 dev, rev; |
e8b2b7ba | 541 | |
ffd58bd2 | 542 | kirkwood_pcie_id(&dev, &rev); |
e8b2b7ba RK |
543 | printk(KERN_DEBUG "Gating clock of unused units\n"); |
544 | printk(KERN_DEBUG "before: 0x%08x\n", curr); | |
545 | ||
546 | /* Make sure those units are accessible */ | |
ffd58bd2 | 547 | writel(curr | CGC_SATA0 | CGC_SATA1 | CGC_PEX0 | CGC_PEX1, CLOCK_GATING_CTRL); |
e8b2b7ba RK |
548 | |
549 | /* For SATA: first shutdown the phy */ | |
550 | if (!(kirkwood_clk_ctrl & CGC_SATA0)) { | |
551 | /* Disable PLL and IVREF */ | |
552 | writel(readl(SATA0_PHY_MODE_2) & ~0xf, SATA0_PHY_MODE_2); | |
553 | /* Disable PHY */ | |
554 | writel(readl(SATA0_IF_CTRL) | 0x200, SATA0_IF_CTRL); | |
555 | } | |
556 | if (!(kirkwood_clk_ctrl & CGC_SATA1)) { | |
557 | /* Disable PLL and IVREF */ | |
558 | writel(readl(SATA1_PHY_MODE_2) & ~0xf, SATA1_PHY_MODE_2); | |
559 | /* Disable PHY */ | |
560 | writel(readl(SATA1_IF_CTRL) | 0x200, SATA1_IF_CTRL); | |
561 | } | |
562 | ||
563 | /* For PCIe: first shutdown the phy */ | |
564 | if (!(kirkwood_clk_ctrl & CGC_PEX0)) { | |
565 | writel(readl(PCIE_LINK_CTRL) | 0x10, PCIE_LINK_CTRL); | |
566 | while (1) | |
567 | if (readl(PCIE_STATUS) & 0x1) | |
568 | break; | |
569 | writel(readl(PCIE_LINK_CTRL) & ~0x10, PCIE_LINK_CTRL); | |
570 | } | |
571 | ||
ffd58bd2 SB |
572 | /* For PCIe 1: first shutdown the phy */ |
573 | if (dev == MV88F6282_DEV_ID) { | |
574 | if (!(kirkwood_clk_ctrl & CGC_PEX1)) { | |
575 | writel(readl(PCIE1_LINK_CTRL) | 0x10, PCIE1_LINK_CTRL); | |
576 | while (1) | |
577 | if (readl(PCIE1_STATUS) & 0x1) | |
578 | break; | |
579 | writel(readl(PCIE1_LINK_CTRL) & ~0x10, PCIE1_LINK_CTRL); | |
580 | } | |
581 | } else /* keep this bit set for devices that don't have PCIe1 */ | |
582 | kirkwood_clk_ctrl |= CGC_PEX1; | |
583 | ||
e8b2b7ba RK |
584 | /* Now gate clock the required units */ |
585 | writel(kirkwood_clk_ctrl, CLOCK_GATING_CTRL); | |
586 | printk(KERN_DEBUG " after: 0x%08x\n", readl(CLOCK_GATING_CTRL)); | |
587 | ||
588 | return 0; | |
589 | } | |
590 | late_initcall(kirkwood_clock_gate); | |
cb15dff4 RK |
591 | |
592 | void kirkwood_restart(char mode, const char *cmd) | |
593 | { | |
594 | /* | |
595 | * Enable soft reset to assert RSTOUTn. | |
596 | */ | |
597 | writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK); | |
598 | ||
599 | /* | |
600 | * Assert soft reset. | |
601 | */ | |
602 | writel(SOFT_RESET, SYSTEM_SOFT_RESET); | |
603 | ||
604 | while (1) | |
605 | ; | |
606 | } |