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Commit | Line | Data |
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651c74c7 SB |
1 | /* |
2 | * arch/arm/mach-kirkwood/common.c | |
3 | * | |
4 | * Core functions for Marvell Kirkwood SoCs | |
5 | * | |
6 | * This file is licensed under the terms of the GNU General Public | |
7 | * License version 2. This program is licensed "as is" without any | |
8 | * warranty of any kind, whether express or implied. | |
9 | */ | |
10 | ||
11 | #include <linux/kernel.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/platform_device.h> | |
14 | #include <linux/serial_8250.h> | |
651c74c7 | 15 | #include <linux/ata_platform.h> |
fb7b2d3f | 16 | #include <linux/mtd/nand.h> |
ee962723 | 17 | #include <linux/dma-mapping.h> |
2f129bf4 AL |
18 | #include <linux/clk-provider.h> |
19 | #include <linux/spinlock.h> | |
e91cac0a | 20 | #include <linux/mv643xx_i2c.h> |
dcf1cece | 21 | #include <net/dsa.h> |
651c74c7 SB |
22 | #include <asm/page.h> |
23 | #include <asm/timex.h> | |
9c15364f | 24 | #include <asm/kexec.h> |
651c74c7 SB |
25 | #include <asm/mach/map.h> |
26 | #include <asm/mach/time.h> | |
a09e64fb | 27 | #include <mach/kirkwood.h> |
fdd8b079 | 28 | #include <mach/bridge-regs.h> |
c02cecb9 | 29 | #include <linux/platform_data/asoc-kirkwood.h> |
6f088f1d | 30 | #include <plat/cache-feroceon-l2.h> |
c02cecb9 AB |
31 | #include <linux/platform_data/mmc-mvsdio.h> |
32 | #include <linux/platform_data/mtd-orion_nand.h> | |
33 | #include <linux/platform_data/usb-ehci-orion.h> | |
28a2b450 | 34 | #include <plat/common.h> |
6f088f1d | 35 | #include <plat/time.h> |
45173d5e | 36 | #include <plat/addr-map.h> |
c02cecb9 | 37 | #include <linux/platform_data/dma-mv_xor.h> |
651c74c7 SB |
38 | #include "common.h" |
39 | ||
40 | /***************************************************************************** | |
41 | * I/O Address Mapping | |
42 | ****************************************************************************/ | |
43 | static struct map_desc kirkwood_io_desc[] __initdata = { | |
44 | { | |
060f3d19 | 45 | .virtual = (unsigned long) KIRKWOOD_REGS_VIRT_BASE, |
651c74c7 SB |
46 | .pfn = __phys_to_pfn(KIRKWOOD_REGS_PHYS_BASE), |
47 | .length = KIRKWOOD_REGS_SIZE, | |
48 | .type = MT_DEVICE, | |
49 | }, | |
50 | }; | |
51 | ||
52 | void __init kirkwood_map_io(void) | |
53 | { | |
54 | iotable_init(kirkwood_io_desc, ARRAY_SIZE(kirkwood_io_desc)); | |
55 | } | |
56 | ||
2f129bf4 AL |
57 | /***************************************************************************** |
58 | * CLK tree | |
59 | ****************************************************************************/ | |
98d9986c | 60 | |
b5409430 SB |
61 | static void enable_sata0(void) |
62 | { | |
63 | /* Enable PLL and IVREF */ | |
64 | writel(readl(SATA0_PHY_MODE_2) | 0xf, SATA0_PHY_MODE_2); | |
65 | /* Enable PHY */ | |
66 | writel(readl(SATA0_IF_CTRL) & ~0x200, SATA0_IF_CTRL); | |
67 | } | |
68 | ||
98d9986c AL |
69 | static void disable_sata0(void) |
70 | { | |
71 | /* Disable PLL and IVREF */ | |
72 | writel(readl(SATA0_PHY_MODE_2) & ~0xf, SATA0_PHY_MODE_2); | |
73 | /* Disable PHY */ | |
74 | writel(readl(SATA0_IF_CTRL) | 0x200, SATA0_IF_CTRL); | |
75 | } | |
76 | ||
b5409430 SB |
77 | static void enable_sata1(void) |
78 | { | |
79 | /* Enable PLL and IVREF */ | |
80 | writel(readl(SATA1_PHY_MODE_2) | 0xf, SATA1_PHY_MODE_2); | |
81 | /* Enable PHY */ | |
82 | writel(readl(SATA1_IF_CTRL) & ~0x200, SATA1_IF_CTRL); | |
83 | } | |
84 | ||
98d9986c AL |
85 | static void disable_sata1(void) |
86 | { | |
87 | /* Disable PLL and IVREF */ | |
88 | writel(readl(SATA1_PHY_MODE_2) & ~0xf, SATA1_PHY_MODE_2); | |
89 | /* Disable PHY */ | |
90 | writel(readl(SATA1_IF_CTRL) | 0x200, SATA1_IF_CTRL); | |
91 | } | |
92 | ||
93 | static void disable_pcie0(void) | |
94 | { | |
95 | writel(readl(PCIE_LINK_CTRL) | 0x10, PCIE_LINK_CTRL); | |
96 | while (1) | |
97 | if (readl(PCIE_STATUS) & 0x1) | |
98 | break; | |
99 | writel(readl(PCIE_LINK_CTRL) & ~0x10, PCIE_LINK_CTRL); | |
100 | } | |
101 | ||
102 | static void disable_pcie1(void) | |
103 | { | |
104 | u32 dev, rev; | |
105 | ||
106 | kirkwood_pcie_id(&dev, &rev); | |
107 | ||
108 | if (dev == MV88F6282_DEV_ID) { | |
109 | writel(readl(PCIE1_LINK_CTRL) | 0x10, PCIE1_LINK_CTRL); | |
110 | while (1) | |
111 | if (readl(PCIE1_STATUS) & 0x1) | |
112 | break; | |
113 | writel(readl(PCIE1_LINK_CTRL) & ~0x10, PCIE1_LINK_CTRL); | |
114 | } | |
115 | } | |
116 | ||
b5409430 SB |
117 | /* An extended version of the gated clk. This calls fn_en()/fn_dis |
118 | * before enabling/disabling the clock. We use this to turn on/off | |
119 | * PHYs etc. */ | |
98d9986c AL |
120 | struct clk_gate_fn { |
121 | struct clk_gate gate; | |
b5409430 SB |
122 | void (*fn_en)(void); |
123 | void (*fn_dis)(void); | |
98d9986c AL |
124 | }; |
125 | ||
126 | #define to_clk_gate_fn(_gate) container_of(_gate, struct clk_gate_fn, gate) | |
127 | #define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw) | |
128 | ||
b5409430 SB |
129 | static int clk_gate_fn_enable(struct clk_hw *hw) |
130 | { | |
131 | struct clk_gate *gate = to_clk_gate(hw); | |
132 | struct clk_gate_fn *gate_fn = to_clk_gate_fn(gate); | |
133 | int ret; | |
134 | ||
135 | ret = clk_gate_ops.enable(hw); | |
136 | if (!ret && gate_fn->fn_en) | |
137 | gate_fn->fn_en(); | |
138 | ||
139 | return ret; | |
140 | } | |
141 | ||
98d9986c AL |
142 | static void clk_gate_fn_disable(struct clk_hw *hw) |
143 | { | |
144 | struct clk_gate *gate = to_clk_gate(hw); | |
145 | struct clk_gate_fn *gate_fn = to_clk_gate_fn(gate); | |
146 | ||
b5409430 SB |
147 | if (gate_fn->fn_dis) |
148 | gate_fn->fn_dis(); | |
98d9986c AL |
149 | |
150 | clk_gate_ops.disable(hw); | |
151 | } | |
152 | ||
153 | static struct clk_ops clk_gate_fn_ops; | |
154 | ||
155 | static struct clk __init *clk_register_gate_fn(struct device *dev, | |
156 | const char *name, | |
157 | const char *parent_name, unsigned long flags, | |
158 | void __iomem *reg, u8 bit_idx, | |
159 | u8 clk_gate_flags, spinlock_t *lock, | |
b5409430 | 160 | void (*fn_en)(void), void (*fn_dis)(void)) |
98d9986c AL |
161 | { |
162 | struct clk_gate_fn *gate_fn; | |
163 | struct clk *clk; | |
164 | struct clk_init_data init; | |
165 | ||
166 | gate_fn = kzalloc(sizeof(struct clk_gate_fn), GFP_KERNEL); | |
167 | if (!gate_fn) { | |
168 | pr_err("%s: could not allocate gated clk\n", __func__); | |
169 | return ERR_PTR(-ENOMEM); | |
170 | } | |
171 | ||
172 | init.name = name; | |
173 | init.ops = &clk_gate_fn_ops; | |
174 | init.flags = flags; | |
175 | init.parent_names = (parent_name ? &parent_name : NULL); | |
176 | init.num_parents = (parent_name ? 1 : 0); | |
177 | ||
178 | /* struct clk_gate assignments */ | |
179 | gate_fn->gate.reg = reg; | |
180 | gate_fn->gate.bit_idx = bit_idx; | |
181 | gate_fn->gate.flags = clk_gate_flags; | |
182 | gate_fn->gate.lock = lock; | |
183 | gate_fn->gate.hw.init = &init; | |
b5409430 SB |
184 | gate_fn->fn_en = fn_en; |
185 | gate_fn->fn_dis = fn_dis; | |
98d9986c | 186 | |
b5409430 SB |
187 | /* ops is the gate ops, but with our enable/disable functions */ |
188 | if (clk_gate_fn_ops.enable != clk_gate_fn_enable || | |
189 | clk_gate_fn_ops.disable != clk_gate_fn_disable) { | |
98d9986c | 190 | clk_gate_fn_ops = clk_gate_ops; |
b5409430 | 191 | clk_gate_fn_ops.enable = clk_gate_fn_enable; |
98d9986c AL |
192 | clk_gate_fn_ops.disable = clk_gate_fn_disable; |
193 | } | |
194 | ||
195 | clk = clk_register(dev, &gate_fn->gate.hw); | |
196 | ||
197 | if (IS_ERR(clk)) | |
198 | kfree(gate_fn); | |
199 | ||
200 | return clk; | |
201 | } | |
202 | ||
2f129bf4 AL |
203 | static DEFINE_SPINLOCK(gating_lock); |
204 | static struct clk *tclk; | |
205 | ||
206 | static struct clk __init *kirkwood_register_gate(const char *name, u8 bit_idx) | |
207 | { | |
060f3d19 | 208 | return clk_register_gate(NULL, name, "tclk", 0, CLOCK_GATING_CTRL, |
2f129bf4 AL |
209 | bit_idx, 0, &gating_lock); |
210 | } | |
211 | ||
98d9986c AL |
212 | static struct clk __init *kirkwood_register_gate_fn(const char *name, |
213 | u8 bit_idx, | |
b5409430 SB |
214 | void (*fn_en)(void), |
215 | void (*fn_dis)(void)) | |
98d9986c | 216 | { |
060f3d19 | 217 | return clk_register_gate_fn(NULL, name, "tclk", 0, CLOCK_GATING_CTRL, |
b5409430 | 218 | bit_idx, 0, &gating_lock, fn_en, fn_dis); |
98d9986c AL |
219 | } |
220 | ||
128789a8 AL |
221 | static struct clk *ge0, *ge1; |
222 | ||
2f129bf4 AL |
223 | void __init kirkwood_clk_init(void) |
224 | { | |
128789a8 | 225 | struct clk *runit, *sata0, *sata1, *usb0, *sdio; |
e919c716 | 226 | struct clk *crypto, *xor0, *xor1, *pex0, *pex1, *audio; |
4574b886 | 227 | |
2f129bf4 AL |
228 | tclk = clk_register_fixed_rate(NULL, "tclk", NULL, |
229 | CLK_IS_ROOT, kirkwood_tclk); | |
230 | ||
4574b886 | 231 | runit = kirkwood_register_gate("runit", CGC_BIT_RUNIT); |
452503eb AL |
232 | ge0 = kirkwood_register_gate("ge0", CGC_BIT_GE0); |
233 | ge1 = kirkwood_register_gate("ge1", CGC_BIT_GE1); | |
98d9986c | 234 | sata0 = kirkwood_register_gate_fn("sata0", CGC_BIT_SATA0, |
b5409430 | 235 | enable_sata0, disable_sata0); |
98d9986c | 236 | sata1 = kirkwood_register_gate_fn("sata1", CGC_BIT_SATA1, |
b5409430 | 237 | enable_sata1, disable_sata1); |
8c869eda | 238 | usb0 = kirkwood_register_gate("usb0", CGC_BIT_USB0); |
f4f7561e | 239 | sdio = kirkwood_register_gate("sdio", CGC_BIT_SDIO); |
1f80b126 | 240 | crypto = kirkwood_register_gate("crypto", CGC_BIT_CRYPTO); |
c510182b AL |
241 | xor0 = kirkwood_register_gate("xor0", CGC_BIT_XOR0); |
242 | xor1 = kirkwood_register_gate("xor1", CGC_BIT_XOR1); | |
98d9986c | 243 | pex0 = kirkwood_register_gate_fn("pex0", CGC_BIT_PEX0, |
b5409430 | 244 | NULL, disable_pcie0); |
98d9986c | 245 | pex1 = kirkwood_register_gate_fn("pex1", CGC_BIT_PEX1, |
b5409430 | 246 | NULL, disable_pcie1); |
e919c716 | 247 | audio = kirkwood_register_gate("audio", CGC_BIT_AUDIO); |
2f129bf4 AL |
248 | kirkwood_register_gate("tdm", CGC_BIT_TDM); |
249 | kirkwood_register_gate("tsu", CGC_BIT_TSU); | |
4574b886 AL |
250 | |
251 | /* clkdev entries, mapping clks to devices */ | |
252 | orion_clkdev_add(NULL, "orion_spi.0", runit); | |
253 | orion_clkdev_add(NULL, "orion_spi.1", runit); | |
452503eb AL |
254 | orion_clkdev_add(NULL, MV643XX_ETH_NAME ".0", ge0); |
255 | orion_clkdev_add(NULL, MV643XX_ETH_NAME ".1", ge1); | |
4f04be62 | 256 | orion_clkdev_add(NULL, "orion_wdt", tclk); |
eee98990 AL |
257 | orion_clkdev_add("0", "sata_mv.0", sata0); |
258 | orion_clkdev_add("1", "sata_mv.0", sata1); | |
8c869eda | 259 | orion_clkdev_add(NULL, "orion-ehci.0", usb0); |
9c2bd504 | 260 | orion_clkdev_add(NULL, "orion_nand", runit); |
f4f7561e | 261 | orion_clkdev_add(NULL, "mvsdio", sdio); |
1f80b126 | 262 | orion_clkdev_add(NULL, "mv_crypto", crypto); |
c510182b AL |
263 | orion_clkdev_add(NULL, MV_XOR_SHARED_NAME ".0", xor0); |
264 | orion_clkdev_add(NULL, MV_XOR_SHARED_NAME ".1", xor1); | |
27e53cfb AL |
265 | orion_clkdev_add("0", "pcie", pex0); |
266 | orion_clkdev_add("1", "pcie", pex1); | |
e919c716 | 267 | orion_clkdev_add(NULL, "kirkwood-i2s", audio); |
e91cac0a | 268 | orion_clkdev_add(NULL, MV64XXX_I2C_CTLR_NAME ".0", runit); |
f479db44 AL |
269 | |
270 | /* Marvell says runit is used by SPI, UART, NAND, TWSI, ..., | |
271 | * so should never be gated. | |
272 | */ | |
273 | clk_prepare_enable(runit); | |
2f129bf4 AL |
274 | } |
275 | ||
651c74c7 SB |
276 | /***************************************************************************** |
277 | * EHCI0 | |
278 | ****************************************************************************/ | |
651c74c7 SB |
279 | void __init kirkwood_ehci_init(void) |
280 | { | |
72053353 | 281 | orion_ehci_init(USB_PHYS_BASE, IRQ_KIRKWOOD_USB, EHCI_PHY_NA); |
651c74c7 SB |
282 | } |
283 | ||
284 | ||
285 | /***************************************************************************** | |
286 | * GE00 | |
287 | ****************************************************************************/ | |
651c74c7 SB |
288 | void __init kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data) |
289 | { | |
db33f4de | 290 | orion_ge00_init(eth_data, |
7e3819d8 | 291 | GE00_PHYS_BASE, IRQ_KIRKWOOD_GE00_SUM, |
58569aee | 292 | IRQ_KIRKWOOD_GE00_ERR, 1600); |
128789a8 AL |
293 | /* The interface forgets the MAC address assigned by u-boot if |
294 | the clock is turned off, so claim the clk now. */ | |
295 | clk_prepare_enable(ge0); | |
651c74c7 SB |
296 | } |
297 | ||
298 | ||
d15fb9ef RS |
299 | /***************************************************************************** |
300 | * GE01 | |
301 | ****************************************************************************/ | |
d15fb9ef RS |
302 | void __init kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data) |
303 | { | |
db33f4de | 304 | orion_ge01_init(eth_data, |
7e3819d8 | 305 | GE01_PHYS_BASE, IRQ_KIRKWOOD_GE01_SUM, |
58569aee | 306 | IRQ_KIRKWOOD_GE01_ERR, 1600); |
128789a8 | 307 | clk_prepare_enable(ge1); |
d15fb9ef RS |
308 | } |
309 | ||
310 | ||
dcf1cece LB |
311 | /***************************************************************************** |
312 | * Ethernet switch | |
313 | ****************************************************************************/ | |
dcf1cece LB |
314 | void __init kirkwood_ge00_switch_init(struct dsa_platform_data *d, int irq) |
315 | { | |
7e3819d8 | 316 | orion_ge00_switch_init(d, irq); |
dcf1cece LB |
317 | } |
318 | ||
319 | ||
fb7b2d3f NP |
320 | /***************************************************************************** |
321 | * NAND flash | |
322 | ****************************************************************************/ | |
323 | static struct resource kirkwood_nand_resource = { | |
324 | .flags = IORESOURCE_MEM, | |
325 | .start = KIRKWOOD_NAND_MEM_PHYS_BASE, | |
326 | .end = KIRKWOOD_NAND_MEM_PHYS_BASE + | |
327 | KIRKWOOD_NAND_MEM_SIZE - 1, | |
328 | }; | |
329 | ||
330 | static struct orion_nand_data kirkwood_nand_data = { | |
331 | .cle = 0, | |
332 | .ale = 1, | |
333 | .width = 8, | |
334 | }; | |
335 | ||
336 | static struct platform_device kirkwood_nand_flash = { | |
337 | .name = "orion_nand", | |
338 | .id = -1, | |
339 | .dev = { | |
340 | .platform_data = &kirkwood_nand_data, | |
341 | }, | |
342 | .resource = &kirkwood_nand_resource, | |
343 | .num_resources = 1, | |
344 | }; | |
345 | ||
346 | void __init kirkwood_nand_init(struct mtd_partition *parts, int nr_parts, | |
347 | int chip_delay) | |
348 | { | |
349 | kirkwood_nand_data.parts = parts; | |
350 | kirkwood_nand_data.nr_parts = nr_parts; | |
351 | kirkwood_nand_data.chip_delay = chip_delay; | |
352 | platform_device_register(&kirkwood_nand_flash); | |
353 | } | |
354 | ||
010937ec BD |
355 | void __init kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts, |
356 | int (*dev_ready)(struct mtd_info *)) | |
357 | { | |
010937ec BD |
358 | kirkwood_nand_data.parts = parts; |
359 | kirkwood_nand_data.nr_parts = nr_parts; | |
360 | kirkwood_nand_data.dev_ready = dev_ready; | |
361 | platform_device_register(&kirkwood_nand_flash); | |
362 | } | |
fb7b2d3f | 363 | |
651c74c7 SB |
364 | /***************************************************************************** |
365 | * SoC RTC | |
366 | ****************************************************************************/ | |
e871b87a | 367 | static void __init kirkwood_rtc_init(void) |
651c74c7 | 368 | { |
4748058c | 369 | orion_rtc_init(RTC_PHYS_BASE, IRQ_KIRKWOOD_RTC); |
651c74c7 SB |
370 | } |
371 | ||
372 | ||
373 | /***************************************************************************** | |
374 | * SATA | |
375 | ****************************************************************************/ | |
651c74c7 SB |
376 | void __init kirkwood_sata_init(struct mv_sata_platform_data *sata_data) |
377 | { | |
db33f4de | 378 | orion_sata_init(sata_data, SATA_PHYS_BASE, IRQ_KIRKWOOD_SATA); |
651c74c7 SB |
379 | } |
380 | ||
381 | ||
8235ee00 NP |
382 | /***************************************************************************** |
383 | * SD/SDIO/MMC | |
384 | ****************************************************************************/ | |
385 | static struct resource mvsdio_resources[] = { | |
386 | [0] = { | |
387 | .start = SDIO_PHYS_BASE, | |
388 | .end = SDIO_PHYS_BASE + SZ_1K - 1, | |
389 | .flags = IORESOURCE_MEM, | |
390 | }, | |
391 | [1] = { | |
392 | .start = IRQ_KIRKWOOD_SDIO, | |
393 | .end = IRQ_KIRKWOOD_SDIO, | |
394 | .flags = IORESOURCE_IRQ, | |
395 | }, | |
396 | }; | |
397 | ||
5c602551 | 398 | static u64 mvsdio_dmamask = DMA_BIT_MASK(32); |
8235ee00 NP |
399 | |
400 | static struct platform_device kirkwood_sdio = { | |
401 | .name = "mvsdio", | |
402 | .id = -1, | |
403 | .dev = { | |
404 | .dma_mask = &mvsdio_dmamask, | |
5c602551 | 405 | .coherent_dma_mask = DMA_BIT_MASK(32), |
8235ee00 NP |
406 | }, |
407 | .num_resources = ARRAY_SIZE(mvsdio_resources), | |
408 | .resource = mvsdio_resources, | |
409 | }; | |
410 | ||
411 | void __init kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data) | |
412 | { | |
413 | u32 dev, rev; | |
414 | ||
415 | kirkwood_pcie_id(&dev, &rev); | |
1e4d2d3d | 416 | if (rev == 0 && dev != MV88F6282_DEV_ID) /* catch all Kirkwood Z0's */ |
8235ee00 NP |
417 | mvsdio_data->clock = 100000000; |
418 | else | |
419 | mvsdio_data->clock = 200000000; | |
8235ee00 NP |
420 | kirkwood_sdio.dev.platform_data = mvsdio_data; |
421 | platform_device_register(&kirkwood_sdio); | |
422 | } | |
423 | ||
424 | ||
18365d18 LB |
425 | /***************************************************************************** |
426 | * SPI | |
427 | ****************************************************************************/ | |
18365d18 LB |
428 | void __init kirkwood_spi_init() |
429 | { | |
4574b886 | 430 | orion_spi_init(SPI_PHYS_BASE); |
18365d18 LB |
431 | } |
432 | ||
433 | ||
6574e001 MM |
434 | /***************************************************************************** |
435 | * I2C | |
436 | ****************************************************************************/ | |
6574e001 MM |
437 | void __init kirkwood_i2c_init(void) |
438 | { | |
aac7ffa3 | 439 | orion_i2c_init(I2C_PHYS_BASE, IRQ_KIRKWOOD_TWSI, 8); |
6574e001 MM |
440 | } |
441 | ||
442 | ||
651c74c7 SB |
443 | /***************************************************************************** |
444 | * UART0 | |
445 | ****************************************************************************/ | |
651c74c7 SB |
446 | |
447 | void __init kirkwood_uart0_init(void) | |
448 | { | |
28a2b450 | 449 | orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE, |
74c33576 | 450 | IRQ_KIRKWOOD_UART_0, tclk); |
651c74c7 SB |
451 | } |
452 | ||
453 | ||
454 | /***************************************************************************** | |
455 | * UART1 | |
456 | ****************************************************************************/ | |
651c74c7 SB |
457 | void __init kirkwood_uart1_init(void) |
458 | { | |
28a2b450 | 459 | orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE, |
74c33576 | 460 | IRQ_KIRKWOOD_UART_1, tclk); |
651c74c7 SB |
461 | } |
462 | ||
ae5c8c83 NP |
463 | /***************************************************************************** |
464 | * Cryptographic Engines and Security Accelerator (CESA) | |
465 | ****************************************************************************/ | |
ae5c8c83 NP |
466 | void __init kirkwood_crypto_init(void) |
467 | { | |
44350061 AL |
468 | orion_crypto_init(CRYPTO_PHYS_BASE, KIRKWOOD_SRAM_PHYS_BASE, |
469 | KIRKWOOD_SRAM_SIZE, IRQ_KIRKWOOD_CRYPTO); | |
ae5c8c83 NP |
470 | } |
471 | ||
472 | ||
09c0ed2e SB |
473 | /***************************************************************************** |
474 | * XOR0 | |
475 | ****************************************************************************/ | |
2b45e05f | 476 | void __init kirkwood_xor0_init(void) |
09c0ed2e | 477 | { |
db33f4de | 478 | orion_xor0_init(XOR0_PHYS_BASE, XOR0_HIGH_PHYS_BASE, |
ee962723 | 479 | IRQ_KIRKWOOD_XOR_00, IRQ_KIRKWOOD_XOR_01); |
09c0ed2e SB |
480 | } |
481 | ||
482 | ||
483 | /***************************************************************************** | |
484 | * XOR1 | |
485 | ****************************************************************************/ | |
2b45e05f | 486 | void __init kirkwood_xor1_init(void) |
09c0ed2e | 487 | { |
ee962723 AL |
488 | orion_xor1_init(XOR1_PHYS_BASE, XOR1_HIGH_PHYS_BASE, |
489 | IRQ_KIRKWOOD_XOR_10, IRQ_KIRKWOOD_XOR_11); | |
09c0ed2e SB |
490 | } |
491 | ||
492 | ||
054bd3f0 TR |
493 | /***************************************************************************** |
494 | * Watchdog | |
495 | ****************************************************************************/ | |
2b45e05f | 496 | void __init kirkwood_wdt_init(void) |
054bd3f0 | 497 | { |
4f04be62 | 498 | orion_wdt_init(); |
054bd3f0 TR |
499 | } |
500 | ||
501 | ||
651c74c7 SB |
502 | /***************************************************************************** |
503 | * Time handling | |
504 | ****************************************************************************/ | |
4ee1f6b5 LB |
505 | void __init kirkwood_init_early(void) |
506 | { | |
507 | orion_time_set_base(TIMER_VIRT_BASE); | |
cb01b633 MS |
508 | |
509 | /* | |
510 | * Some Kirkwood devices allocate their coherent buffers from atomic | |
511 | * context. Increase size of atomic coherent pool to make sure such | |
512 | * the allocations won't fail. | |
513 | */ | |
514 | init_dma_coherent_pool_size(SZ_1M); | |
4ee1f6b5 LB |
515 | } |
516 | ||
79d4dd77 RS |
517 | int kirkwood_tclk; |
518 | ||
9b8ebfec | 519 | static int __init kirkwood_find_tclk(void) |
79d4dd77 | 520 | { |
b2b3dc2f RS |
521 | u32 dev, rev; |
522 | ||
523 | kirkwood_pcie_id(&dev, &rev); | |
1e4d2d3d | 524 | |
2fa0f939 SG |
525 | if (dev == MV88F6281_DEV_ID || dev == MV88F6282_DEV_ID) |
526 | if (((readl(SAMPLE_AT_RESET) >> 21) & 1) == 0) | |
527 | return 200000000; | |
b2b3dc2f | 528 | |
79d4dd77 RS |
529 | return 166666667; |
530 | } | |
531 | ||
6de95c19 | 532 | static void __init kirkwood_timer_init(void) |
651c74c7 | 533 | { |
79d4dd77 | 534 | kirkwood_tclk = kirkwood_find_tclk(); |
4ee1f6b5 LB |
535 | |
536 | orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR, | |
537 | IRQ_KIRKWOOD_BRIDGE, kirkwood_tclk); | |
651c74c7 SB |
538 | } |
539 | ||
540 | struct sys_timer kirkwood_timer = { | |
541 | .init = kirkwood_timer_init, | |
542 | }; | |
543 | ||
49106c72 | 544 | /***************************************************************************** |
545 | * Audio | |
546 | ****************************************************************************/ | |
547 | static struct resource kirkwood_i2s_resources[] = { | |
548 | [0] = { | |
549 | .start = AUDIO_PHYS_BASE, | |
550 | .end = AUDIO_PHYS_BASE + SZ_16K - 1, | |
551 | .flags = IORESOURCE_MEM, | |
552 | }, | |
553 | [1] = { | |
554 | .start = IRQ_KIRKWOOD_I2S, | |
555 | .end = IRQ_KIRKWOOD_I2S, | |
556 | .flags = IORESOURCE_IRQ, | |
557 | }, | |
558 | }; | |
559 | ||
560 | static struct kirkwood_asoc_platform_data kirkwood_i2s_data = { | |
49106c72 | 561 | .burst = 128, |
562 | }; | |
563 | ||
564 | static struct platform_device kirkwood_i2s_device = { | |
565 | .name = "kirkwood-i2s", | |
566 | .id = -1, | |
567 | .num_resources = ARRAY_SIZE(kirkwood_i2s_resources), | |
568 | .resource = kirkwood_i2s_resources, | |
569 | .dev = { | |
570 | .platform_data = &kirkwood_i2s_data, | |
571 | }, | |
572 | }; | |
573 | ||
f0fba2ad | 574 | static struct platform_device kirkwood_pcm_device = { |
c88e7b93 | 575 | .name = "kirkwood-pcm-audio", |
f0fba2ad LG |
576 | .id = -1, |
577 | }; | |
578 | ||
49106c72 | 579 | void __init kirkwood_audio_init(void) |
580 | { | |
49106c72 | 581 | platform_device_register(&kirkwood_i2s_device); |
f0fba2ad | 582 | platform_device_register(&kirkwood_pcm_device); |
49106c72 | 583 | } |
651c74c7 SB |
584 | |
585 | /***************************************************************************** | |
586 | * General | |
587 | ****************************************************************************/ | |
b2b3dc2f RS |
588 | /* |
589 | * Identify device ID and revision. | |
590 | */ | |
2b45e05f | 591 | char * __init kirkwood_id(void) |
651c74c7 | 592 | { |
b2b3dc2f RS |
593 | u32 dev, rev; |
594 | ||
595 | kirkwood_pcie_id(&dev, &rev); | |
596 | ||
597 | if (dev == MV88F6281_DEV_ID) { | |
598 | if (rev == MV88F6281_REV_Z0) | |
599 | return "MV88F6281-Z0"; | |
600 | else if (rev == MV88F6281_REV_A0) | |
601 | return "MV88F6281-A0"; | |
aec1bad3 SG |
602 | else if (rev == MV88F6281_REV_A1) |
603 | return "MV88F6281-A1"; | |
b2b3dc2f RS |
604 | else |
605 | return "MV88F6281-Rev-Unsupported"; | |
606 | } else if (dev == MV88F6192_DEV_ID) { | |
607 | if (rev == MV88F6192_REV_Z0) | |
608 | return "MV88F6192-Z0"; | |
609 | else if (rev == MV88F6192_REV_A0) | |
610 | return "MV88F6192-A0"; | |
1c2003a1 SB |
611 | else if (rev == MV88F6192_REV_A1) |
612 | return "MV88F6192-A1"; | |
b2b3dc2f RS |
613 | else |
614 | return "MV88F6192-Rev-Unsupported"; | |
615 | } else if (dev == MV88F6180_DEV_ID) { | |
616 | if (rev == MV88F6180_REV_A0) | |
617 | return "MV88F6180-Rev-A0"; | |
1c2003a1 SB |
618 | else if (rev == MV88F6180_REV_A1) |
619 | return "MV88F6180-Rev-A1"; | |
b2b3dc2f RS |
620 | else |
621 | return "MV88F6180-Rev-Unsupported"; | |
1e4d2d3d SB |
622 | } else if (dev == MV88F6282_DEV_ID) { |
623 | if (rev == MV88F6282_REV_A0) | |
624 | return "MV88F6282-Rev-A0"; | |
a87d89e7 MM |
625 | else if (rev == MV88F6282_REV_A1) |
626 | return "MV88F6282-Rev-A1"; | |
1e4d2d3d SB |
627 | else |
628 | return "MV88F6282-Rev-Unsupported"; | |
b2b3dc2f RS |
629 | } else { |
630 | return "Device-Unknown"; | |
651c74c7 | 631 | } |
651c74c7 SB |
632 | } |
633 | ||
2b45e05f | 634 | void __init kirkwood_l2_init(void) |
13387603 | 635 | { |
4360bb41 RS |
636 | #ifdef CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH |
637 | writel(readl(L2_CONFIG_REG) | L2_WRITETHROUGH, L2_CONFIG_REG); | |
638 | feroceon_l2_init(1); | |
639 | #else | |
640 | writel(readl(L2_CONFIG_REG) & ~L2_WRITETHROUGH, L2_CONFIG_REG); | |
641 | feroceon_l2_init(0); | |
642 | #endif | |
13387603 SB |
643 | } |
644 | ||
651c74c7 SB |
645 | void __init kirkwood_init(void) |
646 | { | |
647 | printk(KERN_INFO "Kirkwood: %s, TCLK=%d.\n", | |
79d4dd77 | 648 | kirkwood_id(), kirkwood_tclk); |
651c74c7 | 649 | |
2bf30108 LB |
650 | /* |
651 | * Disable propagation of mbus errors to the CPU local bus, | |
652 | * as this causes mbus errors (which can occur for example | |
653 | * for PCI aborts) to throw CPU aborts, which we're not set | |
654 | * up to deal with. | |
655 | */ | |
656 | writel(readl(CPU_CONFIG) & ~CPU_CONFIG_ERROR_PROP, CPU_CONFIG); | |
657 | ||
651c74c7 SB |
658 | kirkwood_setup_cpu_mbus(); |
659 | ||
660 | #ifdef CONFIG_CACHE_FEROCEON_L2 | |
4360bb41 | 661 | kirkwood_l2_init(); |
651c74c7 | 662 | #endif |
5b99d534 | 663 | |
2f129bf4 AL |
664 | /* Setup root of clk tree */ |
665 | kirkwood_clk_init(); | |
666 | ||
5b99d534 NP |
667 | /* internal devices that every board has */ |
668 | kirkwood_rtc_init(); | |
054bd3f0 | 669 | kirkwood_wdt_init(); |
5b99d534 NP |
670 | kirkwood_xor0_init(); |
671 | kirkwood_xor1_init(); | |
ae5c8c83 | 672 | kirkwood_crypto_init(); |
9c15364f EC |
673 | |
674 | #ifdef CONFIG_KEXEC | |
675 | kexec_reinit = kirkwood_enable_pcie; | |
676 | #endif | |
651c74c7 | 677 | } |
e8b2b7ba | 678 | |
cb15dff4 RK |
679 | void kirkwood_restart(char mode, const char *cmd) |
680 | { | |
681 | /* | |
682 | * Enable soft reset to assert RSTOUTn. | |
683 | */ | |
684 | writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK); | |
685 | ||
686 | /* | |
687 | * Assert soft reset. | |
688 | */ | |
689 | writel(SOFT_RESET, SYSTEM_SOFT_RESET); | |
690 | ||
691 | while (1) | |
692 | ; | |
693 | } |