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1a59d1b8 | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
c53c9cf6 AV |
2 | /* |
3 | * arch/arm/mach-ks8695/time.c | |
4 | * | |
5 | * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk> | |
6 | * Copyright (C) 2006 Simtec Electronics | |
c53c9cf6 AV |
7 | */ |
8 | ||
9 | #include <linux/init.h> | |
10 | #include <linux/interrupt.h> | |
11 | #include <linux/irq.h> | |
12 | #include <linux/kernel.h> | |
13 | #include <linux/sched.h> | |
fced80c7 | 14 | #include <linux/io.h> |
c7e783d6 | 15 | #include <linux/clockchips.h> |
c53c9cf6 | 16 | |
c53c9cf6 | 17 | #include <asm/mach/time.h> |
9f97da78 | 18 | #include <asm/system_misc.h> |
c53c9cf6 | 19 | |
a09e64fb | 20 | #include <mach/regs-irq.h> |
c53c9cf6 AV |
21 | |
22 | #include "generic.h" | |
23 | ||
70adc3f3 LW |
24 | #define KS8695_TMR_OFFSET (0xF0000 + 0xE400) |
25 | #define KS8695_TMR_VA (KS8695_IO_VA + KS8695_TMR_OFFSET) | |
26 | #define KS8695_TMR_PA (KS8695_IO_PA + KS8695_TMR_OFFSET) | |
27 | ||
28 | /* | |
29 | * Timer registers | |
30 | */ | |
31 | #define KS8695_TMCON (0x00) /* Timer Control Register */ | |
32 | #define KS8695_T1TC (0x04) /* Timer 1 Timeout Count Register */ | |
33 | #define KS8695_T0TC (0x08) /* Timer 0 Timeout Count Register */ | |
34 | #define KS8695_T1PD (0x0C) /* Timer 1 Pulse Count Register */ | |
35 | #define KS8695_T0PD (0x10) /* Timer 0 Pulse Count Register */ | |
36 | ||
37 | /* Timer Control Register */ | |
38 | #define TMCON_T1EN (1 << 1) /* Timer 1 Enable */ | |
39 | #define TMCON_T0EN (1 << 0) /* Timer 0 Enable */ | |
40 | ||
41 | /* Timer0 Timeout Counter Register */ | |
42 | #define T0TC_WATCHDOG (0xff) /* Enable watchdog mode */ | |
43 | ||
7cfa3c69 | 44 | static int ks8695_set_periodic(struct clock_event_device *evt) |
c53c9cf6 | 45 | { |
7cfa3c69 VK |
46 | u32 rate = DIV_ROUND_CLOSEST(KS8695_CLOCK_RATE, HZ); |
47 | u32 half = DIV_ROUND_CLOSEST(rate, 2); | |
c7e783d6 | 48 | u32 tmcon; |
c53c9cf6 | 49 | |
7cfa3c69 VK |
50 | /* Disable timer 1 */ |
51 | tmcon = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON); | |
52 | tmcon &= ~TMCON_T1EN; | |
53 | writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON); | |
c7e783d6 | 54 | |
7cfa3c69 VK |
55 | /* Both registers need to count down */ |
56 | writel_relaxed(half, KS8695_TMR_VA + KS8695_T1TC); | |
57 | writel_relaxed(half, KS8695_TMR_VA + KS8695_T1PD); | |
c7e783d6 | 58 | |
7cfa3c69 VK |
59 | /* Re-enable timer1 */ |
60 | tmcon |= TMCON_T1EN; | |
61 | writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON); | |
62 | return 0; | |
c7e783d6 LW |
63 | } |
64 | ||
65 | static int ks8695_set_next_event(unsigned long cycles, | |
66 | struct clock_event_device *evt) | |
67 | ||
68 | { | |
69 | u32 half = DIV_ROUND_CLOSEST(cycles, 2); | |
70 | u32 tmcon; | |
71 | ||
72 | /* Disable timer 1 */ | |
73 | tmcon = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON); | |
74 | tmcon &= ~TMCON_T1EN; | |
75 | writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON); | |
76 | ||
77 | /* Both registers need to count down */ | |
78 | writel_relaxed(half, KS8695_TMR_VA + KS8695_T1TC); | |
79 | writel_relaxed(half, KS8695_TMR_VA + KS8695_T1PD); | |
80 | ||
81 | /* Re-enable timer1 */ | |
82 | tmcon |= TMCON_T1EN; | |
83 | writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON); | |
84 | ||
85 | return 0; | |
c53c9cf6 AV |
86 | } |
87 | ||
c7e783d6 | 88 | static struct clock_event_device clockevent_ks8695 = { |
7cfa3c69 VK |
89 | .name = "ks8695_t1tc", |
90 | /* Reasonably fast and accurate clock event */ | |
91 | .rating = 300, | |
92 | .features = CLOCK_EVT_FEAT_ONESHOT | | |
93 | CLOCK_EVT_FEAT_PERIODIC, | |
94 | .set_next_event = ks8695_set_next_event, | |
95 | .set_state_periodic = ks8695_set_periodic, | |
c7e783d6 LW |
96 | }; |
97 | ||
c53c9cf6 AV |
98 | /* |
99 | * IRQ handler for the timer. | |
100 | */ | |
101 | static irqreturn_t ks8695_timer_interrupt(int irq, void *dev_id) | |
102 | { | |
c7e783d6 LW |
103 | struct clock_event_device *evt = &clockevent_ks8695; |
104 | ||
105 | evt->event_handler(evt); | |
c53c9cf6 AV |
106 | return IRQ_HANDLED; |
107 | } | |
108 | ||
109 | static struct irqaction ks8695_timer_irq = { | |
110 | .name = "ks8695_tick", | |
78f6db99 | 111 | .flags = IRQF_TIMER, |
c53c9cf6 AV |
112 | .handler = ks8695_timer_interrupt, |
113 | }; | |
114 | ||
115 | static void ks8695_timer_setup(void) | |
116 | { | |
c53c9cf6 AV |
117 | unsigned long tmcon; |
118 | ||
c7e783d6 | 119 | /* Disable timer 0 and 1 */ |
487748ca | 120 | tmcon = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON); |
c7e783d6 LW |
121 | tmcon &= ~TMCON_T0EN; |
122 | tmcon &= ~TMCON_T1EN; | |
123 | writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON); | |
c53c9cf6 | 124 | |
c7e783d6 LW |
125 | /* |
126 | * Use timer 1 to fire IRQs on the timeline, minimum 2 cycles | |
127 | * (one on each counter) maximum 2*2^32, but the API will only | |
128 | * accept up to a 32bit full word (0xFFFFFFFFU). | |
129 | */ | |
130 | clockevents_config_and_register(&clockevent_ks8695, | |
131 | KS8695_CLOCK_RATE, 2, | |
132 | 0xFFFFFFFFU); | |
c53c9cf6 AV |
133 | } |
134 | ||
6bb27d73 | 135 | void __init ks8695_timer_init(void) |
c53c9cf6 AV |
136 | { |
137 | ks8695_timer_setup(); | |
138 | ||
139 | /* Enable timer interrupts */ | |
140 | setup_irq(KS8695_IRQ_TIMER1, &ks8695_timer_irq); | |
141 | } | |
142 | ||
7b6d864b | 143 | void ks8695_restart(enum reboot_mode reboot_mode, const char *cmd) |
114c19b7 RK |
144 | { |
145 | unsigned int reg; | |
146 | ||
7b6d864b | 147 | if (reboot_mode == REBOOT_SOFT) |
114c19b7 RK |
148 | soft_restart(0); |
149 | ||
150 | /* disable timer0 */ | |
487748ca LW |
151 | reg = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON); |
152 | writel_relaxed(reg & ~TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON); | |
114c19b7 RK |
153 | |
154 | /* enable watchdog mode */ | |
487748ca | 155 | writel_relaxed((10 << 8) | T0TC_WATCHDOG, KS8695_TMR_VA + KS8695_T0TC); |
114c19b7 RK |
156 | |
157 | /* re-enable timer0 */ | |
487748ca | 158 | writel_relaxed(reg | TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON); |
114c19b7 | 159 | } |