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c942fddf | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
f682a218 MB |
2 | /* |
3 | * Device Tree support for Mediatek SoCs | |
4 | * | |
5 | * Copyright (c) 2014 MundoReader S.L. | |
6 | * Author: Matthias Brugger <matthias.bgg@gmail.com> | |
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7 | */ |
8 | #include <linux/init.h> | |
62e59c4e | 9 | #include <linux/io.h> |
f682a218 | 10 | #include <asm/mach/arch.h> |
9821e545 MB |
11 | #include <linux/of.h> |
12 | #include <linux/clk-provider.h> | |
13 | #include <linux/clocksource.h> | |
14 | ||
15 | ||
16 | #define GPT6_CON_MT65xx 0x10008060 | |
17 | #define GPT_ENABLE 0x31 | |
18 | ||
19 | static void __init mediatek_timer_init(void) | |
20 | { | |
21 | void __iomem *gpt_base; | |
22 | ||
23 | if (of_machine_is_compatible("mediatek,mt6589") || | |
601bac76 | 24 | of_machine_is_compatible("mediatek,mt7623") || |
9821e545 MB |
25 | of_machine_is_compatible("mediatek,mt8135") || |
26 | of_machine_is_compatible("mediatek,mt8127")) { | |
27 | /* turn on GPT6 which ungates arch timer clocks */ | |
28 | gpt_base = ioremap(GPT6_CON_MT65xx, 0x04); | |
29 | ||
30 | /* enable clock and set to free-run */ | |
31 | writel(GPT_ENABLE, gpt_base); | |
32 | iounmap(gpt_base); | |
33 | } | |
34 | ||
35 | of_clk_init(NULL); | |
ba5d08c0 | 36 | timer_probe(); |
9821e545 | 37 | }; |
f682a218 MB |
38 | |
39 | static const char * const mediatek_board_dt_compat[] = { | |
74d25721 | 40 | "mediatek,mt2701", |
f682a218 | 41 | "mediatek,mt6589", |
4542172e | 42 | "mediatek,mt6592", |
31ac0d69 | 43 | "mediatek,mt7623", |
a43379dd | 44 | "mediatek,mt7629", |
1ccd653c | 45 | "mediatek,mt8127", |
0c3fb203 | 46 | "mediatek,mt8135", |
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47 | NULL, |
48 | }; | |
49 | ||
50 | DT_MACHINE_START(MEDIATEK_DT, "Mediatek Cortex-A7 (Device Tree)") | |
51 | .dt_compat = mediatek_board_dt_compat, | |
9821e545 | 52 | .init_time = mediatek_timer_init, |
f682a218 | 53 | MACHINE_END |