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50d0e244 CX |
1 | #include <linux/module.h> |
2 | #include <linux/kernel.h> | |
3 | #include <linux/init.h> | |
4 | #include <linux/list.h> | |
5 | #include <linux/io.h> | |
6 | #include <linux/clk.h> | |
7 | ||
8 | #include <mach/addr-map.h> | |
9 | ||
10 | #include "common.h" | |
11 | #include "clock.h" | |
12 | ||
13 | /* | |
14 | * APB clock register offsets for PXA168 | |
15 | */ | |
16 | #define APBC_UART1 APBC_REG(0x000) | |
17 | #define APBC_UART2 APBC_REG(0x004) | |
18 | #define APBC_GPIO APBC_REG(0x008) | |
19 | #define APBC_PWM1 APBC_REG(0x00c) | |
20 | #define APBC_PWM2 APBC_REG(0x010) | |
21 | #define APBC_PWM3 APBC_REG(0x014) | |
22 | #define APBC_PWM4 APBC_REG(0x018) | |
23 | #define APBC_RTC APBC_REG(0x028) | |
24 | #define APBC_TWSI0 APBC_REG(0x02c) | |
25 | #define APBC_KPC APBC_REG(0x030) | |
26 | #define APBC_TWSI1 APBC_REG(0x06c) | |
27 | #define APBC_UART3 APBC_REG(0x070) | |
28 | #define APBC_SSP1 APBC_REG(0x81c) | |
29 | #define APBC_SSP2 APBC_REG(0x820) | |
30 | #define APBC_SSP3 APBC_REG(0x84c) | |
31 | #define APBC_SSP4 APBC_REG(0x858) | |
32 | #define APBC_SSP5 APBC_REG(0x85c) | |
33 | ||
34 | #define APMU_NAND APMU_REG(0x060) | |
35 | #define APMU_LCD APMU_REG(0x04c) | |
36 | #define APMU_ETH APMU_REG(0x0fc) | |
37 | #define APMU_USB APMU_REG(0x05c) | |
38 | ||
39 | /* APB peripheral clocks */ | |
40 | static APBC_CLK(uart1, UART1, 1, 14745600); | |
41 | static APBC_CLK(uart2, UART2, 1, 14745600); | |
42 | static APBC_CLK(uart3, UART3, 1, 14745600); | |
43 | static APBC_CLK(twsi0, TWSI0, 1, 33000000); | |
44 | static APBC_CLK(twsi1, TWSI1, 1, 33000000); | |
45 | static APBC_CLK(pwm1, PWM1, 1, 13000000); | |
46 | static APBC_CLK(pwm2, PWM2, 1, 13000000); | |
47 | static APBC_CLK(pwm3, PWM3, 1, 13000000); | |
48 | static APBC_CLK(pwm4, PWM4, 1, 13000000); | |
49 | static APBC_CLK(ssp1, SSP1, 4, 0); | |
50 | static APBC_CLK(ssp2, SSP2, 4, 0); | |
51 | static APBC_CLK(ssp3, SSP3, 4, 0); | |
52 | static APBC_CLK(ssp4, SSP4, 4, 0); | |
53 | static APBC_CLK(ssp5, SSP5, 4, 0); | |
54 | static APBC_CLK(gpio, GPIO, 0, 13000000); | |
55 | static APBC_CLK(keypad, KPC, 0, 32000); | |
56 | static APBC_CLK(rtc, RTC, 8, 32768); | |
57 | ||
58 | static APMU_CLK(nand, NAND, 0x19b, 156000000); | |
59 | static APMU_CLK(lcd, LCD, 0x7f, 312000000); | |
60 | static APMU_CLK(eth, ETH, 0x09, 0); | |
61 | static APMU_CLK(usb, USB, 0x12, 0); | |
62 | ||
63 | /* device and clock bindings */ | |
64 | static struct clk_lookup pxa168_clkregs[] = { | |
65 | INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL), | |
66 | INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL), | |
67 | INIT_CLKREG(&clk_uart3, "pxa2xx-uart.2", NULL), | |
68 | INIT_CLKREG(&clk_twsi0, "pxa2xx-i2c.0", NULL), | |
69 | INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.1", NULL), | |
70 | INIT_CLKREG(&clk_pwm1, "pxa168-pwm.0", NULL), | |
71 | INIT_CLKREG(&clk_pwm2, "pxa168-pwm.1", NULL), | |
72 | INIT_CLKREG(&clk_pwm3, "pxa168-pwm.2", NULL), | |
73 | INIT_CLKREG(&clk_pwm4, "pxa168-pwm.3", NULL), | |
74 | INIT_CLKREG(&clk_ssp1, "pxa168-ssp.0", NULL), | |
75 | INIT_CLKREG(&clk_ssp2, "pxa168-ssp.1", NULL), | |
76 | INIT_CLKREG(&clk_ssp3, "pxa168-ssp.2", NULL), | |
77 | INIT_CLKREG(&clk_ssp4, "pxa168-ssp.3", NULL), | |
78 | INIT_CLKREG(&clk_ssp5, "pxa168-ssp.4", NULL), | |
79 | INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL), | |
80 | INIT_CLKREG(&clk_lcd, "pxa168-fb", NULL), | |
2cab0292 | 81 | INIT_CLKREG(&clk_gpio, "mmp-gpio", NULL), |
50d0e244 CX |
82 | INIT_CLKREG(&clk_keypad, "pxa27x-keypad", NULL), |
83 | INIT_CLKREG(&clk_eth, "pxa168-eth", "MFUCLK"), | |
84 | INIT_CLKREG(&clk_usb, NULL, "PXA168-USBCLK"), | |
85 | INIT_CLKREG(&clk_rtc, "sa1100-rtc", NULL), | |
86 | }; | |
87 | ||
88 | void __init pxa168_clk_init(void) | |
89 | { | |
90 | clkdev_add_table(ARRAY_AND_SIZE(pxa168_clkregs)); | |
91 | } |