[mirror_ubuntu-artful-kernel.git] / arch / arm / mach-mmp / irq-mmp2.c

/*
 *  linux/arch/arm/mach-mmp/irq-mmp2.c
 *
 *  Generic IRQ handling, GPIO IRQ demultiplexing, etc.
 *
 *  Author:	Haojian Zhuang <haojian.zhuang@marvell.com>
 *  Copyright:	Marvell International Ltd.
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License version 2 as
 *  published by the Free Software Foundation.
 */

#include <linux/init.h>
#include <linux/irq.h>
#include <linux/io.h>

#include <mach/regs-icu.h>
#include <mach/mmp2.h>

#include "common.h"

static void icu_mask_irq(struct irq_data *d)
{
	uint32_t r = __raw_readl(ICU_INT_CONF(d->irq));

	r &= ~ICU_INT_ROUTE_PJ4_IRQ;
	__raw_writel(r, ICU_INT_CONF(d->irq));
}

static void icu_unmask_irq(struct irq_data *d)
{
	uint32_t r = __raw_readl(ICU_INT_CONF(d->irq));

	r |= ICU_INT_ROUTE_PJ4_IRQ;
	__raw_writel(r, ICU_INT_CONF(d->irq));
}

static struct irq_chip icu_irq_chip = {
	.name		= "icu_irq",
	.irq_mask	= icu_mask_irq,
	.irq_mask_ack	= icu_mask_irq,
	.irq_unmask	= icu_unmask_irq,
};

static void pmic_irq_ack(struct irq_data *d)
{
	if (d->irq == IRQ_MMP2_PMIC)
		mmp2_clear_pmic_int();
}

#define SECOND_IRQ_MASK(_name_, irq_base, prefix)			\
static void _name_##_mask_irq(struct irq_data *d)			\
{									\
	uint32_t r;							\
	r = __raw_readl(prefix##_MASK) | (1 << (d->irq - irq_base));	\
	__raw_writel(r, prefix##_MASK);					\
}

#define SECOND_IRQ_UNMASK(_name_, irq_base, prefix)			\
static void _name_##_unmask_irq(struct irq_data *d)			\
{									\
	uint32_t r;							\
	r = __raw_readl(prefix##_MASK) & ~(1 << (d->irq - irq_base));	\
	__raw_writel(r, prefix##_MASK);					\
}

#define SECOND_IRQ_DEMUX(_name_, irq_base, prefix)			\
static void _name_##_irq_demux(unsigned int irq, struct irq_desc *desc)	\
{									\
	unsigned long status, mask, n;					\
	mask = __raw_readl(prefix##_MASK);				\
	while (1) {							\
		status = __raw_readl(prefix##_STATUS) & ~mask;		\
		if (status == 0)					\
			break;						\
		n = find_first_bit(&status, BITS_PER_LONG);		\
		while (n < BITS_PER_LONG) {				\
			generic_handle_irq(irq_base + n);		\
			n = find_next_bit(&status, BITS_PER_LONG, n+1);	\
		}							\
	}								\
}

#define SECOND_IRQ_CHIP(_name_, irq_base, prefix)			\
SECOND_IRQ_MASK(_name_, irq_base, prefix)				\
SECOND_IRQ_UNMASK(_name_, irq_base, prefix)				\
SECOND_IRQ_DEMUX(_name_, irq_base, prefix)				\
static struct irq_chip _name_##_irq_chip = {				\
	.name		= #_name_,					\
	.irq_mask	= _name_##_mask_irq,				\
	.irq_unmask	= _name_##_unmask_irq,				\
}

SECOND_IRQ_CHIP(pmic, IRQ_MMP2_PMIC_BASE, MMP2_ICU_INT4);
SECOND_IRQ_CHIP(rtc,  IRQ_MMP2_RTC_BASE,  MMP2_ICU_INT5);
SECOND_IRQ_CHIP(twsi, IRQ_MMP2_TWSI_BASE, MMP2_ICU_INT17);
SECOND_IRQ_CHIP(misc, IRQ_MMP2_MISC_BASE, MMP2_ICU_INT35);
SECOND_IRQ_CHIP(ssp,  IRQ_MMP2_SSP_BASE,  MMP2_ICU_INT51);

static void init_mux_irq(struct irq_chip *chip, int start, int num)
{
	int irq;

	for (irq = start; num > 0; irq++, num--) {
		struct irq_data *d = irq_get_irq_data(irq);

		/* mask and clear the IRQ */
		chip->irq_mask(d);
		if (chip->irq_ack)
			chip->irq_ack(d);

		irq_set_chip(irq, chip);
		set_irq_flags(irq, IRQF_VALID);
		irq_set_handler(irq, handle_level_irq);
	}
}

void __init mmp2_init_icu(void)
{
	int irq;

	for (irq = 0; irq < IRQ_MMP2_MUX_BASE; irq++) {
		icu_mask_irq(irq_get_irq_data(irq));
		irq_set_chip(irq, &icu_irq_chip);
		set_irq_flags(irq, IRQF_VALID);

		switch (irq) {
		case IRQ_MMP2_PMIC_MUX:
		case IRQ_MMP2_RTC_MUX:
		case IRQ_MMP2_TWSI_MUX:
		case IRQ_MMP2_MISC_MUX:
		case IRQ_MMP2_SSP_MUX:
			break;
		default:
			irq_set_handler(irq, handle_level_irq);
			break;
		}
	}

	/* NOTE: IRQ_MMP2_PMIC requires the PMIC MFPR register
	 * to be written to clear the interrupt
	 */
	pmic_irq_chip.irq_ack = pmic_irq_ack;

	init_mux_irq(&pmic_irq_chip, IRQ_MMP2_PMIC_BASE, 2);
	init_mux_irq(&rtc_irq_chip, IRQ_MMP2_RTC_BASE, 2);
	init_mux_irq(&twsi_irq_chip, IRQ_MMP2_TWSI_BASE, 5);
	init_mux_irq(&misc_irq_chip, IRQ_MMP2_MISC_BASE, 15);
	init_mux_irq(&ssp_irq_chip, IRQ_MMP2_SSP_BASE, 2);

	irq_set_chained_handler(IRQ_MMP2_PMIC_MUX, pmic_irq_demux);
	irq_set_chained_handler(IRQ_MMP2_RTC_MUX, rtc_irq_demux);
	irq_set_chained_handler(IRQ_MMP2_TWSI_MUX, twsi_irq_demux);
	irq_set_chained_handler(IRQ_MMP2_MISC_MUX, misc_irq_demux);
	irq_set_chained_handler(IRQ_MMP2_SSP_MUX, ssp_irq_demux);
}
Commit	Line	Data
2f7e8fae HZ	1	/*
	2	* linux/arch/arm/mach-mmp/irq-mmp2.c
	3	*
	4	* Generic IRQ handling, GPIO IRQ demultiplexing, etc.
	5	*
	6	* Author: Haojian Zhuang <haojian.zhuang@marvell.com>
	7	* Copyright: Marvell International Ltd.
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*/
	13
	14	#include <linux/init.h>
	15	#include <linux/irq.h>
	16	#include <linux/io.h>
	17
	18	#include <mach/regs-icu.h>
2728701d	19	#include <mach/mmp2.h>
2f7e8fae HZ	20
	21	#include "common.h"
	22
a157f26b	23	static void icu_mask_irq(struct irq_data *d)
2f7e8fae	24	{
a157f26b	25	uint32_t r = __raw_readl(ICU_INT_CONF(d->irq));
2f7e8fae HZ	26
2f7e8fae HZ	27	r &= ~ICU_INT_ROUTE_PJ4_IRQ;
a157f26b	28	__raw_writel(r, ICU_INT_CONF(d->irq));
2f7e8fae HZ	29	}
2f7e8fae HZ	30
a157f26b	31	static void icu_unmask_irq(struct irq_data *d)
2f7e8fae	32	{
a157f26b	33	uint32_t r = __raw_readl(ICU_INT_CONF(d->irq));
2f7e8fae HZ	34
2f7e8fae HZ	35	r \|= ICU_INT_ROUTE_PJ4_IRQ;
a157f26b	36	__raw_writel(r, ICU_INT_CONF(d->irq));
2f7e8fae HZ	37	}
	38
	39	static struct irq_chip icu_irq_chip = {
	40	.name = "icu_irq",
a157f26b LB	41	.irq_mask = icu_mask_irq,
	42	.irq_mask_ack = icu_mask_irq,
	43	.irq_unmask = icu_unmask_irq,
2f7e8fae HZ	44	};
2f7e8fae HZ	45
a157f26b	46	static void pmic_irq_ack(struct irq_data *d)
df0c3824	47	{
a157f26b	48	if (d->irq == IRQ_MMP2_PMIC)
df0c3824 HZ	49	mmp2_clear_pmic_int();
	50	}
	51
2f7e8fae	52	#define SECOND_IRQ_MASK(_name_, irq_base, prefix) \
a157f26b	53	static void _name_##_mask_irq(struct irq_data *d) \
2f7e8fae HZ	54	{ \
2f7e8fae HZ	55	uint32_t r; \
a157f26b	56	r = __raw_readl(prefix##_MASK) \| (1 << (d->irq - irq_base)); \
2f7e8fae HZ	57	__raw_writel(r, prefix##_MASK); \
	58	}
	59
	60	#define SECOND_IRQ_UNMASK(_name_, irq_base, prefix) \
a157f26b	61	static void _name_##_unmask_irq(struct irq_data *d) \
2f7e8fae HZ	62	{ \
2f7e8fae HZ	63	uint32_t r; \
a157f26b	64	r = __raw_readl(prefix##_MASK) & ~(1 << (d->irq - irq_base)); \
2f7e8fae HZ	65	__raw_writel(r, prefix##_MASK); \
	66	}
	67
	68	#define SECOND_IRQ_DEMUX(_name_, irq_base, prefix) \
	69	static void _name_##_irq_demux(unsigned int irq, struct irq_desc *desc) \
	70	{ \
	71	unsigned long status, mask, n; \
	72	mask = __raw_readl(prefix##_MASK); \
	73	while (1) { \
	74	status = __raw_readl(prefix##_STATUS) & ~mask; \
	75	if (status == 0) \
	76	break; \
	77	n = find_first_bit(&status, BITS_PER_LONG); \
	78	while (n < BITS_PER_LONG) { \
	79	generic_handle_irq(irq_base + n); \
	80	n = find_next_bit(&status, BITS_PER_LONG, n+1); \
	81	} \
	82	} \
	83	}
	84
	85	#define SECOND_IRQ_CHIP(_name_, irq_base, prefix) \
	86	SECOND_IRQ_MASK(_name_, irq_base, prefix) \
	87	SECOND_IRQ_UNMASK(_name_, irq_base, prefix) \
	88	SECOND_IRQ_DEMUX(_name_, irq_base, prefix) \
	89	static struct irq_chip _name_##_irq_chip = { \
	90	.name = #_name_, \
a157f26b LB	91	.irq_mask = _name_##_mask_irq, \
a157f26b LB	92	.irq_unmask = _name_##_unmask_irq, \
2f7e8fae HZ	93	}
	94
	95	SECOND_IRQ_CHIP(pmic, IRQ_MMP2_PMIC_BASE, MMP2_ICU_INT4);
	96	SECOND_IRQ_CHIP(rtc, IRQ_MMP2_RTC_BASE, MMP2_ICU_INT5);
	97	SECOND_IRQ_CHIP(twsi, IRQ_MMP2_TWSI_BASE, MMP2_ICU_INT17);
	98	SECOND_IRQ_CHIP(misc, IRQ_MMP2_MISC_BASE, MMP2_ICU_INT35);
	99	SECOND_IRQ_CHIP(ssp, IRQ_MMP2_SSP_BASE, MMP2_ICU_INT51);
	100
	101	static void init_mux_irq(struct irq_chip *chip, int start, int num)
	102	{
	103	int irq;
	104
	105	for (irq = start; num > 0; irq++, num--) {
a157f26b LB	106	struct irq_data *d = irq_get_irq_data(irq);
a157f26b LB	107
2029e564	108	/* mask and clear the IRQ */
a157f26b LB	109	chip->irq_mask(d);
	110	if (chip->irq_ack)
	111	chip->irq_ack(d);
2029e564	112
6845664a	113	irq_set_chip(irq, chip);
2f7e8fae	114	set_irq_flags(irq, IRQF_VALID);
6845664a	115	irq_set_handler(irq, handle_level_irq);
2f7e8fae HZ	116	}
	117	}
	118
16144bfb	119	void __init mmp2_init_icu(void)
2f7e8fae HZ	120	{
	121	int irq;
	122
	123	for (irq = 0; irq < IRQ_MMP2_MUX_BASE; irq++) {
a157f26b	124	icu_mask_irq(irq_get_irq_data(irq));
6845664a	125	irq_set_chip(irq, &icu_irq_chip);
2f7e8fae HZ	126	set_irq_flags(irq, IRQF_VALID);
	127
	128	switch (irq) {
	129	case IRQ_MMP2_PMIC_MUX:
	130	case IRQ_MMP2_RTC_MUX:
	131	case IRQ_MMP2_TWSI_MUX:
	132	case IRQ_MMP2_MISC_MUX:
	133	case IRQ_MMP2_SSP_MUX:
	134	break;
	135	default:
6845664a	136	irq_set_handler(irq, handle_level_irq);
2f7e8fae HZ	137	break;
	138	}
	139	}
	140
df0c3824 HZ	141	/* NOTE: IRQ_MMP2_PMIC requires the PMIC MFPR register
	142	* to be written to clear the interrupt
	143	*/
a157f26b	144	pmic_irq_chip.irq_ack = pmic_irq_ack;
df0c3824	145
2f7e8fae HZ	146	init_mux_irq(&pmic_irq_chip, IRQ_MMP2_PMIC_BASE, 2);
	147	init_mux_irq(&rtc_irq_chip, IRQ_MMP2_RTC_BASE, 2);
	148	init_mux_irq(&twsi_irq_chip, IRQ_MMP2_TWSI_BASE, 5);
	149	init_mux_irq(&misc_irq_chip, IRQ_MMP2_MISC_BASE, 15);
	150	init_mux_irq(&ssp_irq_chip, IRQ_MMP2_SSP_BASE, 2);
	151
6845664a TG	152	irq_set_chained_handler(IRQ_MMP2_PMIC_MUX, pmic_irq_demux);
	153	irq_set_chained_handler(IRQ_MMP2_RTC_MUX, rtc_irq_demux);
	154	irq_set_chained_handler(IRQ_MMP2_TWSI_MUX, twsi_irq_demux);
	155	irq_set_chained_handler(IRQ_MMP2_MISC_MUX, misc_irq_demux);
	156	irq_set_chained_handler(IRQ_MMP2_SSP_MUX, ssp_irq_demux);
2f7e8fae	157	}