]>
Commit | Line | Data |
---|---|---|
49cbe786 EM |
1 | /* |
2 | * linux/arch/arm/mach-mmp/pxa168.c | |
3 | * | |
4 | * Code specific to PXA168 | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
2f8163ba | 10 | #include <linux/gpio.h> |
49cbe786 EM |
11 | #include <linux/module.h> |
12 | #include <linux/kernel.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/list.h> | |
e2bb6650 | 15 | #include <linux/io.h> |
49cbe786 EM |
16 | #include <linux/clk.h> |
17 | ||
18 | #include <asm/mach/time.h> | |
19 | #include <mach/addr-map.h> | |
20 | #include <mach/cputype.h> | |
21 | #include <mach/regs-apbc.h> | |
a0f266c1 | 22 | #include <mach/regs-apmu.h> |
49cbe786 EM |
23 | #include <mach/irqs.h> |
24 | #include <mach/dma.h> | |
25 | #include <mach/devices.h> | |
a7a89d96 | 26 | #include <mach/mfp.h> |
49cbe786 EM |
27 | |
28 | #include "common.h" | |
29 | #include "clock.h" | |
30 | ||
a7a89d96 EM |
31 | #define MFPR_VIRT_BASE (APB_VIRT_BASE + 0x1e000) |
32 | ||
33 | static struct mfp_addr_map pxa168_mfp_addr_map[] __initdata = | |
34 | { | |
35 | MFP_ADDR_X(GPIO0, GPIO36, 0x04c), | |
36 | MFP_ADDR_X(GPIO37, GPIO55, 0x000), | |
37 | MFP_ADDR_X(GPIO56, GPIO123, 0x0e0), | |
38 | MFP_ADDR_X(GPIO124, GPIO127, 0x0f4), | |
39 | ||
40 | MFP_ADDR_END, | |
41 | }; | |
42 | ||
e2bb6650 EM |
43 | #define APMASK(i) (GPIO_REGS_VIRT + BANK_OFF(i) + 0x09c) |
44 | ||
45 | static void __init pxa168_init_gpio(void) | |
46 | { | |
47 | int i; | |
48 | ||
49 | /* enable GPIO clock */ | |
50 | __raw_writel(APBC_APBCLK | APBC_FNCLK, APBC_PXA168_GPIO); | |
51 | ||
52 | /* unmask GPIO edge detection for all 4 banks - APMASKx */ | |
53 | for (i = 0; i < 4; i++) | |
54 | __raw_writel(0xffffffff, APMASK(i)); | |
55 | ||
56 | pxa_init_gpio(IRQ_PXA168_GPIOX, 0, 127, NULL); | |
57 | } | |
58 | ||
49cbe786 EM |
59 | void __init pxa168_init_irq(void) |
60 | { | |
61 | icu_init_irq(); | |
e2bb6650 | 62 | pxa168_init_gpio(); |
49cbe786 EM |
63 | } |
64 | ||
65 | /* APB peripheral clocks */ | |
66 | static APBC_CLK(uart1, PXA168_UART1, 1, 14745600); | |
67 | static APBC_CLK(uart2, PXA168_UART2, 1, 14745600); | |
26407f81 | 68 | static APBC_CLK(uart3, PXA168_UART3, 1, 14745600); |
1a77920e EM |
69 | static APBC_CLK(twsi0, PXA168_TWSI0, 1, 33000000); |
70 | static APBC_CLK(twsi1, PXA168_TWSI1, 1, 33000000); | |
a27ba768 EM |
71 | static APBC_CLK(pwm1, PXA168_PWM1, 1, 13000000); |
72 | static APBC_CLK(pwm2, PXA168_PWM2, 1, 13000000); | |
73 | static APBC_CLK(pwm3, PXA168_PWM3, 1, 13000000); | |
74 | static APBC_CLK(pwm4, PXA168_PWM4, 1, 13000000); | |
7e499228 HZ |
75 | static APBC_CLK(ssp1, PXA168_SSP1, 4, 0); |
76 | static APBC_CLK(ssp2, PXA168_SSP2, 4, 0); | |
77 | static APBC_CLK(ssp3, PXA168_SSP3, 4, 0); | |
78 | static APBC_CLK(ssp4, PXA168_SSP4, 4, 0); | |
79 | static APBC_CLK(ssp5, PXA168_SSP5, 4, 0); | |
6d109465 | 80 | static APBC_CLK(keypad, PXA168_KPC, 0, 32000); |
49cbe786 | 81 | |
6662498e | 82 | static APMU_CLK(nand, NAND, 0x19b, 156000000); |
58cf68b8 | 83 | static APMU_CLK(lcd, LCD, 0x7f, 312000000); |
80def0dc | 84 | static APMU_CLK(eth, ETH, 0x09, 0); |
a0f266c1 | 85 | |
49cbe786 EM |
86 | /* device and clock bindings */ |
87 | static struct clk_lookup pxa168_clkregs[] = { | |
88 | INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL), | |
89 | INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL), | |
26407f81 | 90 | INIT_CLKREG(&clk_uart3, "pxa2xx-uart.2", NULL), |
1a77920e EM |
91 | INIT_CLKREG(&clk_twsi0, "pxa2xx-i2c.0", NULL), |
92 | INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.1", NULL), | |
a27ba768 EM |
93 | INIT_CLKREG(&clk_pwm1, "pxa168-pwm.0", NULL), |
94 | INIT_CLKREG(&clk_pwm2, "pxa168-pwm.1", NULL), | |
95 | INIT_CLKREG(&clk_pwm3, "pxa168-pwm.2", NULL), | |
96 | INIT_CLKREG(&clk_pwm4, "pxa168-pwm.3", NULL), | |
7e499228 HZ |
97 | INIT_CLKREG(&clk_ssp1, "pxa168-ssp.0", NULL), |
98 | INIT_CLKREG(&clk_ssp2, "pxa168-ssp.1", NULL), | |
99 | INIT_CLKREG(&clk_ssp3, "pxa168-ssp.2", NULL), | |
100 | INIT_CLKREG(&clk_ssp4, "pxa168-ssp.3", NULL), | |
101 | INIT_CLKREG(&clk_ssp5, "pxa168-ssp.4", NULL), | |
a0f266c1 | 102 | INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL), |
58cf68b8 | 103 | INIT_CLKREG(&clk_lcd, "pxa168-fb", NULL), |
6d109465 | 104 | INIT_CLKREG(&clk_keypad, "pxa27x-keypad", NULL), |
80def0dc | 105 | INIT_CLKREG(&clk_eth, "pxa168-eth", "MFUCLK"), |
49cbe786 EM |
106 | }; |
107 | ||
108 | static int __init pxa168_init(void) | |
109 | { | |
110 | if (cpu_is_pxa168()) { | |
a7a89d96 EM |
111 | mfp_init_base(MFPR_VIRT_BASE); |
112 | mfp_init_addr(pxa168_mfp_addr_map); | |
49cbe786 | 113 | pxa_init_dma(IRQ_PXA168_DMA_INT0, 32); |
0a0300dc | 114 | clkdev_add_table(ARRAY_AND_SIZE(pxa168_clkregs)); |
49cbe786 EM |
115 | } |
116 | ||
117 | return 0; | |
118 | } | |
119 | postcore_initcall(pxa168_init); | |
120 | ||
121 | /* system timer - clock enabled, 3.25MHz */ | |
122 | #define TIMER_CLK_RST (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3)) | |
123 | ||
124 | static void __init pxa168_timer_init(void) | |
125 | { | |
126 | /* this is early, we have to initialize the CCU registers by | |
127 | * ourselves instead of using clk_* API. Clock rate is defined | |
128 | * by APBC_TIMERS_CLK_RST (3.25MHz) and enabled free-running | |
129 | */ | |
130 | __raw_writel(APBC_APBCLK | APBC_RST, APBC_PXA168_TIMERS); | |
131 | ||
132 | /* 3.25MHz, bus/functional clock enabled, release reset */ | |
133 | __raw_writel(TIMER_CLK_RST, APBC_PXA168_TIMERS); | |
134 | ||
135 | timer_init(IRQ_PXA168_TIMER1); | |
136 | } | |
137 | ||
138 | struct sys_timer pxa168_timer = { | |
139 | .init = pxa168_timer_init, | |
140 | }; | |
141 | ||
ab5739a1 MB |
142 | void pxa168_clear_keypad_wakeup(void) |
143 | { | |
144 | uint32_t val; | |
145 | uint32_t mask = APMU_PXA168_KP_WAKE_CLR; | |
146 | ||
147 | /* wake event clear is needed in order to clear keypad interrupt */ | |
148 | val = __raw_readl(APMU_WAKE_CLR); | |
149 | __raw_writel(val | mask, APMU_WAKE_CLR); | |
150 | } | |
151 | ||
49cbe786 EM |
152 | /* on-chip devices */ |
153 | PXA168_DEVICE(uart1, "pxa2xx-uart", 0, UART1, 0xd4017000, 0x30, 21, 22); | |
154 | PXA168_DEVICE(uart2, "pxa2xx-uart", 1, UART2, 0xd4018000, 0x30, 23, 24); | |
26407f81 | 155 | PXA168_DEVICE(uart3, "pxa2xx-uart", 2, UART3, 0xd4026000, 0x30, 23, 24); |
1a77920e EM |
156 | PXA168_DEVICE(twsi0, "pxa2xx-i2c", 0, TWSI0, 0xd4011000, 0x28); |
157 | PXA168_DEVICE(twsi1, "pxa2xx-i2c", 1, TWSI1, 0xd4025000, 0x28); | |
a27ba768 EM |
158 | PXA168_DEVICE(pwm1, "pxa168-pwm", 0, NONE, 0xd401a000, 0x10); |
159 | PXA168_DEVICE(pwm2, "pxa168-pwm", 1, NONE, 0xd401a400, 0x10); | |
160 | PXA168_DEVICE(pwm3, "pxa168-pwm", 2, NONE, 0xd401a800, 0x10); | |
161 | PXA168_DEVICE(pwm4, "pxa168-pwm", 3, NONE, 0xd401ac00, 0x10); | |
a0f266c1 | 162 | PXA168_DEVICE(nand, "pxa3xx-nand", -1, NAND, 0xd4283000, 0x80, 97, 99); |
7e499228 HZ |
163 | PXA168_DEVICE(ssp1, "pxa168-ssp", 0, SSP1, 0xd401b000, 0x40, 52, 53); |
164 | PXA168_DEVICE(ssp2, "pxa168-ssp", 1, SSP2, 0xd401c000, 0x40, 54, 55); | |
165 | PXA168_DEVICE(ssp3, "pxa168-ssp", 2, SSP3, 0xd401f000, 0x40, 56, 57); | |
166 | PXA168_DEVICE(ssp4, "pxa168-ssp", 3, SSP4, 0xd4020000, 0x40, 58, 59); | |
167 | PXA168_DEVICE(ssp5, "pxa168-ssp", 4, SSP5, 0xd4021000, 0x40, 60, 61); | |
58cf68b8 | 168 | PXA168_DEVICE(fb, "pxa168-fb", -1, LCD, 0xd420b000, 0x1c8); |
6d109465 | 169 | PXA168_DEVICE(keypad, "pxa27x-keypad", -1, KEYPAD, 0xd4012000, 0x4c); |
80def0dc | 170 | PXA168_DEVICE(eth, "pxa168-eth", -1, MFU, 0xc0800000, 0x0fff); |