[mirror_ubuntu-zesty-kernel.git] / arch / arm / mach-msm / board-qsd8x50.c

/* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
 * 02110-1301, USA.
 */
#include <linux/gpio.h>
#include <linux/kernel.h>
#include <linux/irq.h>
#include <linux/gpio.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/usb/msm_hsusb.h>
#include <linux/err.h>
#include <linux/clkdev.h>

#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/io.h>
#include <asm/setup.h>

#include <mach/board.h>
#include <mach/irqs.h>
#include <mach/sirc.h>
#include <mach/vreg.h>
#include <mach/mmc.h>

#include "devices.h"

extern struct sys_timer msm_timer;

static const resource_size_t qsd8x50_surf_smc91x_base __initdata = 0x70000300;
static const unsigned        qsd8x50_surf_smc91x_gpio __initdata = 156;

/* Leave smc91x resources empty here, as we'll fill them in
 * at run-time: they vary from board to board, and the true
 * configuration won't be known until boot.
 */
static struct resource smc91x_resources[] = {
	[0] = {
		.flags = IORESOURCE_MEM,
	},
	[1] = {
		.flags = IORESOURCE_IRQ,
	},
};

static struct platform_device smc91x_device = {
	.name           = "smc91x",
	.id             = 0,
	.num_resources  = ARRAY_SIZE(smc91x_resources),
	.resource       = smc91x_resources,
};

static int __init msm_init_smc91x(void)
{
	if (machine_is_qsd8x50_surf()) {
		smc91x_resources[0].start = qsd8x50_surf_smc91x_base;
		smc91x_resources[0].end   = qsd8x50_surf_smc91x_base + 0xff;
		smc91x_resources[1].start =
			gpio_to_irq(qsd8x50_surf_smc91x_gpio);
		smc91x_resources[1].end   =
			gpio_to_irq(qsd8x50_surf_smc91x_gpio);
		platform_device_register(&smc91x_device);
	}

	return 0;
}
module_init(msm_init_smc91x);

static int hsusb_phy_init_seq[] = {
	0x08, 0x31,	/* Increase HS Driver Amplitude */
	0x20, 0x32,	/* Enable and set Pre-Emphasis Depth to 10% */
	-1
};

static struct msm_otg_platform_data msm_otg_pdata = {
	.phy_init_seq		= hsusb_phy_init_seq,
	.mode                   = USB_PERIPHERAL,
	.otg_control		= OTG_PHY_CONTROL,
};

static struct platform_device *devices[] __initdata = {
	&msm_device_uart3,
	&msm_device_smd,
	&msm_device_otg,
	&msm_device_hsusb,
	&msm_device_hsusb_host,
};

static struct msm_mmc_gpio sdc1_gpio_cfg[] = {
	{51, "sdc1_dat_3"},
	{52, "sdc1_dat_2"},
	{53, "sdc1_dat_1"},
	{54, "sdc1_dat_0"},
	{55, "sdc1_cmd"},
	{56, "sdc1_clk"}
};

static struct vreg *vreg_mmc;
static unsigned long vreg_sts;

static uint32_t msm_sdcc_setup_power(struct device *dv, unsigned int vdd)
{
	int rc = 0;
	struct platform_device *pdev;

	pdev = container_of(dv, struct platform_device, dev);

	if (vdd == 0) {
		if (!vreg_sts)
			return 0;

		clear_bit(pdev->id, &vreg_sts);

		if (!vreg_sts) {
			rc = vreg_disable(vreg_mmc);
			if (rc)
				pr_err("vreg_mmc disable failed for slot "
						"%d: %d\n", pdev->id, rc);
		}
		return 0;
	}

	if (!vreg_sts) {
		rc = vreg_set_level(vreg_mmc, 2900);
		if (rc)
			pr_err("vreg_mmc set level failed for slot %d: %d\n",
					pdev->id, rc);
		rc = vreg_enable(vreg_mmc);
		if (rc)
			pr_err("vreg_mmc enable failed for slot %d: %d\n",
					pdev->id, rc);
	}
	set_bit(pdev->id, &vreg_sts);
	return 0;
}

static struct msm_mmc_gpio_data sdc1_gpio = {
	.gpio = sdc1_gpio_cfg,
	.size = ARRAY_SIZE(sdc1_gpio_cfg),
};

static struct msm_mmc_platform_data qsd8x50_sdc1_data = {
	.ocr_mask	= MMC_VDD_27_28 | MMC_VDD_28_29,
	.translate_vdd	= msm_sdcc_setup_power,
	.gpio_data = &sdc1_gpio,
};

static void __init qsd8x50_init_mmc(void)
{
	vreg_mmc = vreg_get(NULL, "gp5");

	if (IS_ERR(vreg_mmc)) {
		pr_err("vreg get for vreg_mmc failed (%ld)\n",
				PTR_ERR(vreg_mmc));
		return;
	}

	msm_add_sdcc(1, &qsd8x50_sdc1_data, 0, 0);
}

static void __init qsd8x50_map_io(void)
{
	msm_map_qsd8x50_io();
	msm_clock_init(msm_clocks_8x50, msm_num_clocks_8x50);
}

static void __init qsd8x50_init_irq(void)
{
	msm_init_irq();
	msm_init_sirc();
}

static void __init qsd8x50_init(void)
{
	msm_device_otg.dev.platform_data = &msm_otg_pdata;
	msm_device_hsusb.dev.parent = &msm_device_otg.dev;
	msm_device_hsusb_host.dev.parent = &msm_device_otg.dev;
	platform_add_devices(devices, ARRAY_SIZE(devices));
	qsd8x50_init_mmc();
}

MACHINE_START(QSD8X50_SURF, "QCT QSD8X50 SURF")
	.boot_params = PLAT_PHYS_OFFSET + 0x100,
	.map_io = qsd8x50_map_io,
	.init_irq = qsd8x50_init_irq,
	.init_machine = qsd8x50_init,
	.timer = &msm_timer,
MACHINE_END

MACHINE_START(QSD8X50A_ST1_5, "QCT QSD8X50A ST1.5")
	.boot_params = PLAT_PHYS_OFFSET + 0x100,
	.map_io = qsd8x50_map_io,
	.init_irq = qsd8x50_init_irq,
	.init_machine = qsd8x50_init,
	.timer = &msm_timer,
MACHINE_END
Commit	Line	Data
8b4d95fc	1	/* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
a32d2feb DW	2	*
	3	* This program is free software; you can redistribute it and/or modify
	4	* it under the terms of the GNU General Public License version 2 and
	5	* only version 2 as published by the Free Software Foundation.
	6	*
	7	* This program is distributed in the hope that it will be useful,
	8	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	9	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	10	* GNU General Public License for more details.
	11	*
	12	* You should have received a copy of the GNU General Public License
	13	* along with this program; if not, write to the Free Software
	14	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
	15	* 02110-1301, USA.
	16	*/
2f8163ba	17	#include <linux/gpio.h>
a32d2feb DW	18	#include <linux/kernel.h>
	19	#include <linux/irq.h>
	20	#include <linux/gpio.h>
	21	#include <linux/platform_device.h>
a32d2feb	22	#include <linux/delay.h>
7032d512	23	#include <linux/usb/msm_hsusb.h>
8b4d95fc	24	#include <linux/err.h>
bd32344a	25	#include <linux/clkdev.h>
a32d2feb DW	26
	27	#include <asm/mach-types.h>
	28	#include <asm/mach/arch.h>
	29	#include <asm/io.h>
	30	#include <asm/setup.h>
	31
a32d2feb	32	#include <mach/board.h>
d1c0d43d DW	33	#include <mach/irqs.h>
d1c0d43d DW	34	#include <mach/sirc.h>
8b4d95fc ST	35	#include <mach/vreg.h>
8b4d95fc ST	36	#include <mach/mmc.h>
a32d2feb DW	37
a32d2feb DW	38	#include "devices.h"
a32d2feb	39
d1c0d43d	40	extern struct sys_timer msm_timer;
a32d2feb	41
5d73c53b GB	42	static const resource_size_t qsd8x50_surf_smc91x_base __initdata = 0x70000300;
	43	static const unsigned qsd8x50_surf_smc91x_gpio __initdata = 156;
	44
	45	/* Leave smc91x resources empty here, as we'll fill them in
	46	* at run-time: they vary from board to board, and the true
	47	* configuration won't be known until boot.
	48	*/
7c63dedc	49	static struct resource smc91x_resources[] = {
5d73c53b GB	50	[0] = {
	51	.flags = IORESOURCE_MEM,
	52	},
	53	[1] = {
	54	.flags = IORESOURCE_IRQ,
	55	},
	56	};
	57
7c63dedc	58	static struct platform_device smc91x_device = {
5d73c53b GB	59	.name = "smc91x",
	60	.id = 0,
	61	.num_resources = ARRAY_SIZE(smc91x_resources),
	62	.resource = smc91x_resources,
	63	};
	64
	65	static int __init msm_init_smc91x(void)
	66	{
	67	if (machine_is_qsd8x50_surf()) {
	68	smc91x_resources[0].start = qsd8x50_surf_smc91x_base;
	69	smc91x_resources[0].end = qsd8x50_surf_smc91x_base + 0xff;
	70	smc91x_resources[1].start =
	71	gpio_to_irq(qsd8x50_surf_smc91x_gpio);
	72	smc91x_resources[1].end =
	73	gpio_to_irq(qsd8x50_surf_smc91x_gpio);
	74	platform_device_register(&smc91x_device);
	75	}
	76
	77	return 0;
	78	}
	79	module_init(msm_init_smc91x);
	80
7032d512 PK	81	static int hsusb_phy_init_seq[] = {
	82	0x08, 0x31, /* Increase HS Driver Amplitude */
	83	0x20, 0x32, /* Enable and set Pre-Emphasis Depth to 10% */
	84	-1
	85	};
	86
	87	static struct msm_otg_platform_data msm_otg_pdata = {
	88	.phy_init_seq = hsusb_phy_init_seq,
	89	.mode = USB_PERIPHERAL,
	90	.otg_control = OTG_PHY_CONTROL,
	91	};
	92
a32d2feb	93	static struct platform_device *devices[] __initdata = {
d1c0d43d	94	&msm_device_uart3,
88b52277	95	&msm_device_smd,
7032d512 PK	96	&msm_device_otg,
	97	&msm_device_hsusb,
	98	&msm_device_hsusb_host,
a32d2feb DW	99	};
a32d2feb DW	100
8b4d95fc ST	101	static struct msm_mmc_gpio sdc1_gpio_cfg[] = {
	102	{51, "sdc1_dat_3"},
	103	{52, "sdc1_dat_2"},
	104	{53, "sdc1_dat_1"},
	105	{54, "sdc1_dat_0"},
	106	{55, "sdc1_cmd"},
	107	{56, "sdc1_clk"}
	108	};
	109
	110	static struct vreg *vreg_mmc;
	111	static unsigned long vreg_sts;
	112
	113	static uint32_t msm_sdcc_setup_power(struct device *dv, unsigned int vdd)
	114	{
	115	int rc = 0;
	116	struct platform_device *pdev;
	117
	118	pdev = container_of(dv, struct platform_device, dev);
	119
	120	if (vdd == 0) {
	121	if (!vreg_sts)
	122	return 0;
	123
	124	clear_bit(pdev->id, &vreg_sts);
	125
	126	if (!vreg_sts) {
	127	rc = vreg_disable(vreg_mmc);
	128	if (rc)
	129	pr_err("vreg_mmc disable failed for slot "
	130	"%d: %d\n", pdev->id, rc);
	131	}
	132	return 0;
	133	}
	134
	135	if (!vreg_sts) {
	136	rc = vreg_set_level(vreg_mmc, 2900);
	137	if (rc)
	138	pr_err("vreg_mmc set level failed for slot %d: %d\n",
	139	pdev->id, rc);
	140	rc = vreg_enable(vreg_mmc);
	141	if (rc)
	142	pr_err("vreg_mmc enable failed for slot %d: %d\n",
	143	pdev->id, rc);
	144	}
	145	set_bit(pdev->id, &vreg_sts);
	146	return 0;
	147	}
	148
	149	static struct msm_mmc_gpio_data sdc1_gpio = {
	150	.gpio = sdc1_gpio_cfg,
	151	.size = ARRAY_SIZE(sdc1_gpio_cfg),
	152	};
	153
	154	static struct msm_mmc_platform_data qsd8x50_sdc1_data = {
	155	.ocr_mask = MMC_VDD_27_28 \| MMC_VDD_28_29,
	156	.translate_vdd = msm_sdcc_setup_power,
	157	.gpio_data = &sdc1_gpio,
	158	};
	159
	160	static void __init qsd8x50_init_mmc(void)
	161	{
62f0988e	162	vreg_mmc = vreg_get(NULL, "gp5");
8b4d95fc ST	163
	164	if (IS_ERR(vreg_mmc)) {
	165	pr_err("vreg get for vreg_mmc failed (%ld)\n",
	166	PTR_ERR(vreg_mmc));
	167	return;
	168	}
	169
	170	msm_add_sdcc(1, &qsd8x50_sdc1_data, 0, 0);
	171	}
	172
d1c0d43d	173	static void __init qsd8x50_map_io(void)
a32d2feb	174	{
d1c0d43d DW	175	msm_map_qsd8x50_io();
d1c0d43d DW	176	msm_clock_init(msm_clocks_8x50, msm_num_clocks_8x50);
a32d2feb DW	177	}
a32d2feb DW	178
d1c0d43d	179	static void __init qsd8x50_init_irq(void)
a32d2feb	180	{
d1c0d43d DW	181	msm_init_irq();
d1c0d43d DW	182	msm_init_sirc();
a32d2feb DW	183	}
	184
	185	static void __init qsd8x50_init(void)
	186	{
7032d512 PK	187	msm_device_otg.dev.platform_data = &msm_otg_pdata;
	188	msm_device_hsusb.dev.parent = &msm_device_otg.dev;
	189	msm_device_hsusb_host.dev.parent = &msm_device_otg.dev;
a32d2feb	190	platform_add_devices(devices, ARRAY_SIZE(devices));
8b4d95fc	191	qsd8x50_init_mmc();
a32d2feb DW	192	}
a32d2feb DW	193
a32d2feb	194	MACHINE_START(QSD8X50_SURF, "QCT QSD8X50 SURF")
b75c178a	195	.boot_params = PLAT_PHYS_OFFSET + 0x100,
a32d2feb DW	196	.map_io = qsd8x50_map_io,
	197	.init_irq = qsd8x50_init_irq,
	198	.init_machine = qsd8x50_init,
	199	.timer = &msm_timer,
	200	MACHINE_END
	201
d1c0d43d	202	MACHINE_START(QSD8X50A_ST1_5, "QCT QSD8X50A ST1.5")
b75c178a	203	.boot_params = PLAT_PHYS_OFFSET + 0x100,
a32d2feb DW	204	.map_io = qsd8x50_map_io,
	205	.init_irq = qsd8x50_init_irq,
	206	.init_machine = qsd8x50_init,
	207	.timer = &msm_timer,
	208	MACHINE_END