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0cc2fc1f GB |
1 | /* Copyright (c) 2010, Code Aurora Forum. All rights reserved. |
2 | * | |
3 | * This program is free software; you can redistribute it and/or modify | |
4 | * it under the terms of the GNU General Public License version 2 and | |
5 | * only version 2 as published by the Free Software Foundation. | |
6 | * | |
7 | * This program is distributed in the hope that it will be useful, | |
8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
10 | * GNU General Public License for more details. | |
11 | * | |
12 | * You should have received a copy of the GNU General Public License | |
13 | * along with this program; if not, write to the Free Software | |
14 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA | |
15 | * 02110-1301, USA. | |
16 | * | |
17 | */ | |
70cc2c00 GB |
18 | #define pr_fmt(fmt) "%s: " fmt, __func__ |
19 | ||
20 | #include <linux/bitmap.h> | |
21 | #include <linux/bitops.h> | |
0cc2fc1f | 22 | #include <linux/gpio.h> |
70cc2c00 GB |
23 | #include <linux/init.h> |
24 | #include <linux/interrupt.h> | |
0cc2fc1f GB |
25 | #include <linux/io.h> |
26 | #include <linux/irq.h> | |
27 | #include <linux/module.h> | |
28 | #include <linux/platform_device.h> | |
29 | #include <linux/spinlock.h> | |
30 | #include <mach/msm_iomap.h> | |
31 | #include "gpiomux.h" | |
32 | ||
33 | /* Bits of interest in the GPIO_IN_OUT register. | |
34 | */ | |
35 | enum { | |
70cc2c00 GB |
36 | GPIO_IN = 0, |
37 | GPIO_OUT = 1 | |
38 | }; | |
39 | ||
40 | /* Bits of interest in the GPIO_INTR_STATUS register. | |
41 | */ | |
42 | enum { | |
43 | INTR_STATUS = 0, | |
0cc2fc1f GB |
44 | }; |
45 | ||
46 | /* Bits of interest in the GPIO_CFG register. | |
47 | */ | |
48 | enum { | |
70cc2c00 GB |
49 | GPIO_OE = 9, |
50 | }; | |
51 | ||
52 | /* Bits of interest in the GPIO_INTR_CFG register. | |
53 | * When a GPIO triggers, two separate decisions are made, controlled | |
54 | * by two separate flags. | |
55 | * | |
56 | * - First, INTR_RAW_STATUS_EN controls whether or not the GPIO_INTR_STATUS | |
57 | * register for that GPIO will be updated to reflect the triggering of that | |
58 | * gpio. If this bit is 0, this register will not be updated. | |
59 | * - Second, INTR_ENABLE controls whether an interrupt is triggered. | |
60 | * | |
61 | * If INTR_ENABLE is set and INTR_RAW_STATUS_EN is NOT set, an interrupt | |
62 | * can be triggered but the status register will not reflect it. | |
63 | */ | |
64 | enum { | |
65 | INTR_ENABLE = 0, | |
66 | INTR_POL_CTL = 1, | |
67 | INTR_DECT_CTL = 2, | |
68 | INTR_RAW_STATUS_EN = 3, | |
69 | }; | |
70 | ||
71 | /* Codes of interest in GPIO_INTR_CFG_SU. | |
72 | */ | |
73 | enum { | |
74 | TARGET_PROC_SCORPION = 4, | |
75 | TARGET_PROC_NONE = 7, | |
0cc2fc1f GB |
76 | }; |
77 | ||
70cc2c00 GB |
78 | |
79 | #define GPIO_INTR_CFG_SU(gpio) (MSM_TLMM_BASE + 0x0400 + (0x04 * (gpio))) | |
0cc2fc1f GB |
80 | #define GPIO_CONFIG(gpio) (MSM_TLMM_BASE + 0x1000 + (0x10 * (gpio))) |
81 | #define GPIO_IN_OUT(gpio) (MSM_TLMM_BASE + 0x1004 + (0x10 * (gpio))) | |
70cc2c00 GB |
82 | #define GPIO_INTR_CFG(gpio) (MSM_TLMM_BASE + 0x1008 + (0x10 * (gpio))) |
83 | #define GPIO_INTR_STATUS(gpio) (MSM_TLMM_BASE + 0x100c + (0x10 * (gpio))) | |
84 | ||
85 | /** | |
86 | * struct msm_gpio_dev: the MSM8660 SoC GPIO device structure | |
87 | * | |
88 | * @enabled_irqs: a bitmap used to optimize the summary-irq handler. By | |
89 | * keeping track of which gpios are unmasked as irq sources, we avoid | |
90 | * having to do readl calls on hundreds of iomapped registers each time | |
91 | * the summary interrupt fires in order to locate the active interrupts. | |
92 | * | |
93 | * @wake_irqs: a bitmap for tracking which interrupt lines are enabled | |
94 | * as wakeup sources. When the device is suspended, interrupts which are | |
95 | * not wakeup sources are disabled. | |
96 | * | |
97 | * @dual_edge_irqs: a bitmap used to track which irqs are configured | |
98 | * as dual-edge, as this is not supported by the hardware and requires | |
99 | * some special handling in the driver. | |
100 | */ | |
101 | struct msm_gpio_dev { | |
102 | struct gpio_chip gpio_chip; | |
103 | DECLARE_BITMAP(enabled_irqs, NR_GPIO_IRQS); | |
104 | DECLARE_BITMAP(wake_irqs, NR_GPIO_IRQS); | |
105 | DECLARE_BITMAP(dual_edge_irqs, NR_GPIO_IRQS); | |
106 | }; | |
0cc2fc1f GB |
107 | |
108 | static DEFINE_SPINLOCK(tlmm_lock); | |
109 | ||
70cc2c00 GB |
110 | static inline struct msm_gpio_dev *to_msm_gpio_dev(struct gpio_chip *chip) |
111 | { | |
112 | return container_of(chip, struct msm_gpio_dev, gpio_chip); | |
113 | } | |
114 | ||
115 | static inline void set_gpio_bits(unsigned n, void __iomem *reg) | |
116 | { | |
117 | writel(readl(reg) | n, reg); | |
118 | } | |
119 | ||
120 | static inline void clear_gpio_bits(unsigned n, void __iomem *reg) | |
121 | { | |
122 | writel(readl(reg) & ~n, reg); | |
123 | } | |
124 | ||
0cc2fc1f GB |
125 | static int msm_gpio_get(struct gpio_chip *chip, unsigned offset) |
126 | { | |
70cc2c00 | 127 | return readl(GPIO_IN_OUT(offset)) & BIT(GPIO_IN); |
0cc2fc1f GB |
128 | } |
129 | ||
130 | static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int val) | |
131 | { | |
70cc2c00 | 132 | writel(val ? BIT(GPIO_OUT) : 0, GPIO_IN_OUT(offset)); |
0cc2fc1f GB |
133 | } |
134 | ||
135 | static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset) | |
136 | { | |
137 | unsigned long irq_flags; | |
138 | ||
139 | spin_lock_irqsave(&tlmm_lock, irq_flags); | |
70cc2c00 | 140 | clear_gpio_bits(BIT(GPIO_OE), GPIO_CONFIG(offset)); |
0cc2fc1f GB |
141 | spin_unlock_irqrestore(&tlmm_lock, irq_flags); |
142 | return 0; | |
143 | } | |
144 | ||
145 | static int msm_gpio_direction_output(struct gpio_chip *chip, | |
146 | unsigned offset, | |
147 | int val) | |
148 | { | |
149 | unsigned long irq_flags; | |
150 | ||
151 | spin_lock_irqsave(&tlmm_lock, irq_flags); | |
152 | msm_gpio_set(chip, offset, val); | |
70cc2c00 | 153 | set_gpio_bits(BIT(GPIO_OE), GPIO_CONFIG(offset)); |
0cc2fc1f GB |
154 | spin_unlock_irqrestore(&tlmm_lock, irq_flags); |
155 | return 0; | |
156 | } | |
157 | ||
158 | static int msm_gpio_request(struct gpio_chip *chip, unsigned offset) | |
159 | { | |
160 | return msm_gpiomux_get(chip->base + offset); | |
161 | } | |
162 | ||
163 | static void msm_gpio_free(struct gpio_chip *chip, unsigned offset) | |
164 | { | |
165 | msm_gpiomux_put(chip->base + offset); | |
166 | } | |
167 | ||
70cc2c00 GB |
168 | static int msm_gpio_to_irq(struct gpio_chip *chip, unsigned offset) |
169 | { | |
170 | return MSM_GPIO_TO_INT(chip->base + offset); | |
171 | } | |
172 | ||
173 | static inline int msm_irq_to_gpio(struct gpio_chip *chip, unsigned irq) | |
174 | { | |
175 | return irq - MSM_GPIO_TO_INT(chip->base); | |
176 | } | |
177 | ||
178 | static struct msm_gpio_dev msm_gpio = { | |
179 | .gpio_chip = { | |
180 | .base = 0, | |
181 | .ngpio = NR_GPIO_IRQS, | |
182 | .direction_input = msm_gpio_direction_input, | |
183 | .direction_output = msm_gpio_direction_output, | |
184 | .get = msm_gpio_get, | |
185 | .set = msm_gpio_set, | |
186 | .to_irq = msm_gpio_to_irq, | |
187 | .request = msm_gpio_request, | |
188 | .free = msm_gpio_free, | |
189 | }, | |
190 | }; | |
191 | ||
192 | /* For dual-edge interrupts in software, since the hardware has no | |
193 | * such support: | |
194 | * | |
195 | * At appropriate moments, this function may be called to flip the polarity | |
196 | * settings of both-edge irq lines to try and catch the next edge. | |
197 | * | |
198 | * The attempt is considered successful if: | |
199 | * - the status bit goes high, indicating that an edge was caught, or | |
200 | * - the input value of the gpio doesn't change during the attempt. | |
201 | * If the value changes twice during the process, that would cause the first | |
202 | * test to fail but would force the second, as two opposite | |
203 | * transitions would cause a detection no matter the polarity setting. | |
204 | * | |
205 | * The do-loop tries to sledge-hammer closed the timing hole between | |
206 | * the initial value-read and the polarity-write - if the line value changes | |
207 | * during that window, an interrupt is lost, the new polarity setting is | |
208 | * incorrect, and the first success test will fail, causing a retry. | |
209 | * | |
210 | * Algorithm comes from Google's msmgpio driver, see mach-msm/gpio.c. | |
211 | */ | |
212 | static void msm_gpio_update_dual_edge_pos(unsigned gpio) | |
213 | { | |
214 | int loop_limit = 100; | |
215 | unsigned val, val2, intstat; | |
216 | ||
217 | do { | |
218 | val = readl(GPIO_IN_OUT(gpio)) & BIT(GPIO_IN); | |
219 | if (val) | |
220 | clear_gpio_bits(BIT(INTR_POL_CTL), GPIO_INTR_CFG(gpio)); | |
221 | else | |
222 | set_gpio_bits(BIT(INTR_POL_CTL), GPIO_INTR_CFG(gpio)); | |
223 | val2 = readl(GPIO_IN_OUT(gpio)) & BIT(GPIO_IN); | |
224 | intstat = readl(GPIO_INTR_STATUS(gpio)) & BIT(INTR_STATUS); | |
225 | if (intstat || val == val2) | |
226 | return; | |
227 | } while (loop_limit-- > 0); | |
228 | pr_err("dual-edge irq failed to stabilize, " | |
229 | "interrupts dropped. %#08x != %#08x\n", | |
230 | val, val2); | |
231 | } | |
232 | ||
233 | static void msm_gpio_irq_ack(unsigned int irq) | |
234 | { | |
235 | int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq); | |
236 | ||
237 | writel(BIT(INTR_STATUS), GPIO_INTR_STATUS(gpio)); | |
238 | if (test_bit(gpio, msm_gpio.dual_edge_irqs)) | |
239 | msm_gpio_update_dual_edge_pos(gpio); | |
240 | } | |
241 | ||
242 | static void msm_gpio_irq_mask(unsigned int irq) | |
243 | { | |
244 | int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq); | |
245 | unsigned long irq_flags; | |
246 | ||
247 | spin_lock_irqsave(&tlmm_lock, irq_flags); | |
248 | writel(TARGET_PROC_NONE, GPIO_INTR_CFG_SU(gpio)); | |
249 | clear_gpio_bits(INTR_RAW_STATUS_EN | INTR_ENABLE, GPIO_INTR_CFG(gpio)); | |
250 | __clear_bit(gpio, msm_gpio.enabled_irqs); | |
251 | spin_unlock_irqrestore(&tlmm_lock, irq_flags); | |
252 | } | |
253 | ||
254 | static void msm_gpio_irq_unmask(unsigned int irq) | |
255 | { | |
256 | int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq); | |
257 | unsigned long irq_flags; | |
258 | ||
259 | spin_lock_irqsave(&tlmm_lock, irq_flags); | |
260 | __set_bit(gpio, msm_gpio.enabled_irqs); | |
261 | set_gpio_bits(INTR_RAW_STATUS_EN | INTR_ENABLE, GPIO_INTR_CFG(gpio)); | |
262 | writel(TARGET_PROC_SCORPION, GPIO_INTR_CFG_SU(gpio)); | |
263 | spin_unlock_irqrestore(&tlmm_lock, irq_flags); | |
264 | } | |
265 | ||
266 | static int msm_gpio_irq_set_type(unsigned int irq, unsigned int flow_type) | |
267 | { | |
268 | int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq); | |
269 | unsigned long irq_flags; | |
270 | uint32_t bits; | |
271 | ||
272 | spin_lock_irqsave(&tlmm_lock, irq_flags); | |
273 | ||
274 | bits = readl(GPIO_INTR_CFG(gpio)); | |
275 | ||
276 | if (flow_type & IRQ_TYPE_EDGE_BOTH) { | |
277 | bits |= BIT(INTR_DECT_CTL); | |
278 | irq_desc[irq].handle_irq = handle_edge_irq; | |
279 | if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) | |
280 | __set_bit(gpio, msm_gpio.dual_edge_irqs); | |
281 | else | |
282 | __clear_bit(gpio, msm_gpio.dual_edge_irqs); | |
283 | } else { | |
284 | bits &= ~BIT(INTR_DECT_CTL); | |
285 | irq_desc[irq].handle_irq = handle_level_irq; | |
286 | __clear_bit(gpio, msm_gpio.dual_edge_irqs); | |
287 | } | |
288 | ||
289 | if (flow_type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_HIGH)) | |
290 | bits |= BIT(INTR_POL_CTL); | |
291 | else | |
292 | bits &= ~BIT(INTR_POL_CTL); | |
293 | ||
294 | writel(bits, GPIO_INTR_CFG(gpio)); | |
295 | ||
296 | if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) | |
297 | msm_gpio_update_dual_edge_pos(gpio); | |
298 | ||
299 | spin_unlock_irqrestore(&tlmm_lock, irq_flags); | |
300 | ||
301 | return 0; | |
302 | } | |
303 | ||
304 | /* | |
305 | * When the summary IRQ is raised, any number of GPIO lines may be high. | |
306 | * It is the job of the summary handler to find all those GPIO lines | |
307 | * which have been set as summary IRQ lines and which are triggered, | |
308 | * and to call their interrupt handlers. | |
309 | */ | |
310 | static void msm_summary_irq_handler(unsigned int irq, struct irq_desc *desc) | |
311 | { | |
312 | unsigned long i; | |
313 | ||
314 | for (i = find_first_bit(msm_gpio.enabled_irqs, NR_GPIO_IRQS); | |
315 | i < NR_GPIO_IRQS; | |
316 | i = find_next_bit(msm_gpio.enabled_irqs, NR_GPIO_IRQS, i + 1)) { | |
317 | if (readl(GPIO_INTR_STATUS(i)) & BIT(INTR_STATUS)) | |
318 | generic_handle_irq(msm_gpio_to_irq(&msm_gpio.gpio_chip, | |
319 | i)); | |
320 | } | |
321 | desc->chip->ack(irq); | |
322 | } | |
323 | ||
324 | static int msm_gpio_irq_set_wake(unsigned int irq, unsigned int on) | |
325 | { | |
326 | int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq); | |
327 | ||
328 | if (on) { | |
329 | if (bitmap_empty(msm_gpio.wake_irqs, NR_GPIO_IRQS)) | |
330 | set_irq_wake(TLMM_SCSS_SUMMARY_IRQ, 1); | |
331 | set_bit(gpio, msm_gpio.wake_irqs); | |
332 | } else { | |
333 | clear_bit(gpio, msm_gpio.wake_irqs); | |
334 | if (bitmap_empty(msm_gpio.wake_irqs, NR_GPIO_IRQS)) | |
335 | set_irq_wake(TLMM_SCSS_SUMMARY_IRQ, 0); | |
336 | } | |
337 | ||
338 | return 0; | |
339 | } | |
340 | ||
341 | static struct irq_chip msm_gpio_irq_chip = { | |
342 | .name = "msmgpio", | |
343 | .mask = msm_gpio_irq_mask, | |
344 | .unmask = msm_gpio_irq_unmask, | |
345 | .ack = msm_gpio_irq_ack, | |
346 | .set_type = msm_gpio_irq_set_type, | |
347 | .set_wake = msm_gpio_irq_set_wake, | |
0cc2fc1f GB |
348 | }; |
349 | ||
350 | static int __devinit msm_gpio_probe(struct platform_device *dev) | |
351 | { | |
70cc2c00 GB |
352 | int i, irq, ret; |
353 | ||
354 | bitmap_zero(msm_gpio.enabled_irqs, NR_GPIO_IRQS); | |
355 | bitmap_zero(msm_gpio.wake_irqs, NR_GPIO_IRQS); | |
356 | bitmap_zero(msm_gpio.dual_edge_irqs, NR_GPIO_IRQS); | |
357 | msm_gpio.gpio_chip.label = dev->name; | |
358 | ret = gpiochip_add(&msm_gpio.gpio_chip); | |
359 | if (ret < 0) | |
360 | return ret; | |
0cc2fc1f | 361 | |
70cc2c00 GB |
362 | for (i = 0; i < msm_gpio.gpio_chip.ngpio; ++i) { |
363 | irq = msm_gpio_to_irq(&msm_gpio.gpio_chip, i); | |
364 | set_irq_chip(irq, &msm_gpio_irq_chip); | |
365 | set_irq_handler(irq, handle_level_irq); | |
366 | set_irq_flags(irq, IRQF_VALID); | |
367 | } | |
0cc2fc1f | 368 | |
70cc2c00 GB |
369 | set_irq_chained_handler(TLMM_SCSS_SUMMARY_IRQ, |
370 | msm_summary_irq_handler); | |
371 | return 0; | |
0cc2fc1f GB |
372 | } |
373 | ||
374 | static int __devexit msm_gpio_remove(struct platform_device *dev) | |
375 | { | |
70cc2c00 | 376 | int ret = gpiochip_remove(&msm_gpio.gpio_chip); |
0cc2fc1f GB |
377 | |
378 | if (ret < 0) | |
379 | return ret; | |
380 | ||
381 | set_irq_handler(TLMM_SCSS_SUMMARY_IRQ, NULL); | |
382 | ||
383 | return 0; | |
384 | } | |
385 | ||
386 | static struct platform_driver msm_gpio_driver = { | |
387 | .probe = msm_gpio_probe, | |
388 | .remove = __devexit_p(msm_gpio_remove), | |
389 | .driver = { | |
390 | .name = "msmgpio", | |
391 | .owner = THIS_MODULE, | |
392 | }, | |
393 | }; | |
394 | ||
395 | static struct platform_device msm_device_gpio = { | |
396 | .name = "msmgpio", | |
397 | .id = -1, | |
398 | }; | |
399 | ||
400 | static int __init msm_gpio_init(void) | |
401 | { | |
402 | int rc; | |
403 | ||
404 | rc = platform_driver_register(&msm_gpio_driver); | |
405 | if (!rc) { | |
406 | rc = platform_device_register(&msm_device_gpio); | |
407 | if (rc) | |
408 | platform_driver_unregister(&msm_gpio_driver); | |
409 | } | |
410 | ||
411 | return rc; | |
412 | } | |
413 | ||
414 | static void __exit msm_gpio_exit(void) | |
415 | { | |
416 | platform_device_unregister(&msm_device_gpio); | |
417 | platform_driver_unregister(&msm_gpio_driver); | |
418 | } | |
419 | ||
420 | postcore_initcall(msm_gpio_init); | |
421 | module_exit(msm_gpio_exit); | |
422 | ||
423 | MODULE_AUTHOR("Gregory Bean <gbean@codeaurora.org>"); | |
424 | MODULE_DESCRIPTION("Driver for Qualcomm MSM TLMMv2 SoC GPIOs"); | |
425 | MODULE_LICENSE("GPL v2"); | |
426 | MODULE_ALIAS("platform:msmgpio"); |