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1 | /* linux/arch/arm/mach-msm/gpio.c |
2 | * | |
3 | * Copyright (C) 2007 Google, Inc. | |
4 | * Copyright (c) 2009-2010, Code Aurora Forum. All rights reserved. | |
5 | * | |
6 | * This software is licensed under the terms of the GNU General Public | |
7 | * License version 2, as published by the Free Software Foundation, and | |
8 | * may be copied, distributed, and modified under those terms. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | */ | |
16 | ||
17 | #include <linux/bitops.h> | |
18 | #include <linux/gpio.h> | |
19 | #include <linux/interrupt.h> | |
20 | #include <linux/io.h> | |
21 | #include <linux/irq.h> | |
22 | #include <linux/module.h> | |
23 | #include "gpio_hw.h" | |
24 | ||
25 | #define FIRST_GPIO_IRQ MSM_GPIO_TO_INT(0) | |
26 | ||
27 | #define MSM_GPIO_BANK(bank, first, last) \ | |
28 | { \ | |
29 | .regs = { \ | |
30 | .out = MSM_GPIO_OUT_##bank, \ | |
31 | .in = MSM_GPIO_IN_##bank, \ | |
32 | .int_status = MSM_GPIO_INT_STATUS_##bank, \ | |
33 | .int_clear = MSM_GPIO_INT_CLEAR_##bank, \ | |
34 | .int_en = MSM_GPIO_INT_EN_##bank, \ | |
35 | .int_edge = MSM_GPIO_INT_EDGE_##bank, \ | |
36 | .int_pos = MSM_GPIO_INT_POS_##bank, \ | |
37 | .oe = MSM_GPIO_OE_##bank, \ | |
38 | }, \ | |
39 | .chip = { \ | |
40 | .base = (first), \ | |
41 | .ngpio = (last) - (first) + 1, \ | |
42 | .get = msm_gpio_get, \ | |
43 | .set = msm_gpio_set, \ | |
44 | .direction_input = msm_gpio_direction_input, \ | |
45 | .direction_output = msm_gpio_direction_output, \ | |
46 | .to_irq = msm_gpio_to_irq, \ | |
47 | } \ | |
48 | } | |
49 | ||
50 | #define MSM_GPIO_BROKEN_INT_CLEAR 1 | |
51 | ||
52 | struct msm_gpio_regs { | |
53 | void __iomem *out; | |
54 | void __iomem *in; | |
55 | void __iomem *int_status; | |
56 | void __iomem *int_clear; | |
57 | void __iomem *int_en; | |
58 | void __iomem *int_edge; | |
59 | void __iomem *int_pos; | |
60 | void __iomem *oe; | |
61 | }; | |
62 | ||
63 | struct msm_gpio_chip { | |
64 | spinlock_t lock; | |
65 | struct gpio_chip chip; | |
66 | struct msm_gpio_regs regs; | |
67 | #if MSM_GPIO_BROKEN_INT_CLEAR | |
68 | unsigned int_status_copy; | |
69 | #endif | |
70 | unsigned int both_edge_detect; | |
71 | unsigned int int_enable[2]; /* 0: awake, 1: sleep */ | |
72 | }; | |
73 | ||
74 | static int msm_gpio_write(struct msm_gpio_chip *msm_chip, | |
75 | unsigned offset, unsigned on) | |
76 | { | |
77 | unsigned mask = BIT(offset); | |
78 | unsigned val; | |
79 | ||
80 | val = readl(msm_chip->regs.out); | |
81 | if (on) | |
82 | writel(val | mask, msm_chip->regs.out); | |
83 | else | |
84 | writel(val & ~mask, msm_chip->regs.out); | |
85 | return 0; | |
86 | } | |
87 | ||
88 | static void msm_gpio_update_both_edge_detect(struct msm_gpio_chip *msm_chip) | |
89 | { | |
90 | int loop_limit = 100; | |
91 | unsigned pol, val, val2, intstat; | |
92 | do { | |
93 | val = readl(msm_chip->regs.in); | |
94 | pol = readl(msm_chip->regs.int_pos); | |
95 | pol = (pol & ~msm_chip->both_edge_detect) | | |
96 | (~val & msm_chip->both_edge_detect); | |
97 | writel(pol, msm_chip->regs.int_pos); | |
98 | intstat = readl(msm_chip->regs.int_status); | |
99 | val2 = readl(msm_chip->regs.in); | |
100 | if (((val ^ val2) & msm_chip->both_edge_detect & ~intstat) == 0) | |
101 | return; | |
102 | } while (loop_limit-- > 0); | |
103 | printk(KERN_ERR "msm_gpio_update_both_edge_detect, " | |
104 | "failed to reach stable state %x != %x\n", val, val2); | |
105 | } | |
106 | ||
107 | static int msm_gpio_clear_detect_status(struct msm_gpio_chip *msm_chip, | |
108 | unsigned offset) | |
109 | { | |
110 | unsigned bit = BIT(offset); | |
111 | ||
112 | #if MSM_GPIO_BROKEN_INT_CLEAR | |
113 | /* Save interrupts that already triggered before we loose them. */ | |
114 | /* Any interrupt that triggers between the read of int_status */ | |
115 | /* and the write to int_clear will still be lost though. */ | |
116 | msm_chip->int_status_copy |= readl(msm_chip->regs.int_status); | |
117 | msm_chip->int_status_copy &= ~bit; | |
118 | #endif | |
119 | writel(bit, msm_chip->regs.int_clear); | |
120 | msm_gpio_update_both_edge_detect(msm_chip); | |
121 | return 0; | |
122 | } | |
123 | ||
124 | static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset) | |
125 | { | |
126 | struct msm_gpio_chip *msm_chip; | |
127 | unsigned long irq_flags; | |
128 | ||
129 | msm_chip = container_of(chip, struct msm_gpio_chip, chip); | |
130 | spin_lock_irqsave(&msm_chip->lock, irq_flags); | |
131 | writel(readl(msm_chip->regs.oe) & ~BIT(offset), msm_chip->regs.oe); | |
132 | spin_unlock_irqrestore(&msm_chip->lock, irq_flags); | |
133 | return 0; | |
134 | } | |
135 | ||
136 | static int | |
137 | msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value) | |
138 | { | |
139 | struct msm_gpio_chip *msm_chip; | |
140 | unsigned long irq_flags; | |
141 | ||
142 | msm_chip = container_of(chip, struct msm_gpio_chip, chip); | |
143 | spin_lock_irqsave(&msm_chip->lock, irq_flags); | |
144 | msm_gpio_write(msm_chip, offset, value); | |
145 | writel(readl(msm_chip->regs.oe) | BIT(offset), msm_chip->regs.oe); | |
146 | spin_unlock_irqrestore(&msm_chip->lock, irq_flags); | |
147 | return 0; | |
148 | } | |
149 | ||
150 | static int msm_gpio_get(struct gpio_chip *chip, unsigned offset) | |
151 | { | |
152 | struct msm_gpio_chip *msm_chip; | |
153 | ||
154 | msm_chip = container_of(chip, struct msm_gpio_chip, chip); | |
155 | return (readl(msm_chip->regs.in) & (1U << offset)) ? 1 : 0; | |
156 | } | |
157 | ||
158 | static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value) | |
159 | { | |
160 | struct msm_gpio_chip *msm_chip; | |
161 | unsigned long irq_flags; | |
162 | ||
163 | msm_chip = container_of(chip, struct msm_gpio_chip, chip); | |
164 | spin_lock_irqsave(&msm_chip->lock, irq_flags); | |
165 | msm_gpio_write(msm_chip, offset, value); | |
166 | spin_unlock_irqrestore(&msm_chip->lock, irq_flags); | |
167 | } | |
168 | ||
169 | static int msm_gpio_to_irq(struct gpio_chip *chip, unsigned offset) | |
170 | { | |
171 | return MSM_GPIO_TO_INT(chip->base + offset); | |
172 | } | |
173 | ||
174 | struct msm_gpio_chip msm_gpio_chips[] = { | |
175 | #if defined(CONFIG_ARCH_MSM7X00A) | |
176 | MSM_GPIO_BANK(0, 0, 15), | |
177 | MSM_GPIO_BANK(1, 16, 42), | |
178 | MSM_GPIO_BANK(2, 43, 67), | |
179 | MSM_GPIO_BANK(3, 68, 94), | |
180 | MSM_GPIO_BANK(4, 95, 106), | |
181 | MSM_GPIO_BANK(5, 107, 121), | |
182 | #elif defined(CONFIG_ARCH_MSM7X25) || defined(CONFIG_ARCH_MSM7X27) | |
183 | MSM_GPIO_BANK(0, 0, 15), | |
184 | MSM_GPIO_BANK(1, 16, 42), | |
185 | MSM_GPIO_BANK(2, 43, 67), | |
186 | MSM_GPIO_BANK(3, 68, 94), | |
187 | MSM_GPIO_BANK(4, 95, 106), | |
188 | MSM_GPIO_BANK(5, 107, 132), | |
189 | #elif defined(CONFIG_ARCH_MSM7X30) | |
190 | MSM_GPIO_BANK(0, 0, 15), | |
191 | MSM_GPIO_BANK(1, 16, 43), | |
192 | MSM_GPIO_BANK(2, 44, 67), | |
193 | MSM_GPIO_BANK(3, 68, 94), | |
194 | MSM_GPIO_BANK(4, 95, 106), | |
195 | MSM_GPIO_BANK(5, 107, 133), | |
196 | MSM_GPIO_BANK(6, 134, 150), | |
197 | MSM_GPIO_BANK(7, 151, 181), | |
198 | #elif defined(CONFIG_ARCH_QSD8X50) | |
199 | MSM_GPIO_BANK(0, 0, 15), | |
200 | MSM_GPIO_BANK(1, 16, 42), | |
201 | MSM_GPIO_BANK(2, 43, 67), | |
202 | MSM_GPIO_BANK(3, 68, 94), | |
203 | MSM_GPIO_BANK(4, 95, 103), | |
204 | MSM_GPIO_BANK(5, 104, 121), | |
205 | MSM_GPIO_BANK(6, 122, 152), | |
206 | MSM_GPIO_BANK(7, 153, 164), | |
207 | #endif | |
208 | }; | |
209 | ||
210 | static void msm_gpio_irq_ack(unsigned int irq) | |
211 | { | |
212 | unsigned long irq_flags; | |
213 | struct msm_gpio_chip *msm_chip = get_irq_chip_data(irq); | |
214 | spin_lock_irqsave(&msm_chip->lock, irq_flags); | |
215 | msm_gpio_clear_detect_status(msm_chip, | |
216 | irq - gpio_to_irq(msm_chip->chip.base)); | |
217 | spin_unlock_irqrestore(&msm_chip->lock, irq_flags); | |
218 | } | |
219 | ||
220 | static void msm_gpio_irq_mask(unsigned int irq) | |
221 | { | |
222 | unsigned long irq_flags; | |
223 | struct msm_gpio_chip *msm_chip = get_irq_chip_data(irq); | |
224 | unsigned offset = irq - gpio_to_irq(msm_chip->chip.base); | |
225 | ||
226 | spin_lock_irqsave(&msm_chip->lock, irq_flags); | |
227 | /* level triggered interrupts are also latched */ | |
228 | if (!(readl(msm_chip->regs.int_edge) & BIT(offset))) | |
229 | msm_gpio_clear_detect_status(msm_chip, offset); | |
230 | msm_chip->int_enable[0] &= ~BIT(offset); | |
231 | writel(msm_chip->int_enable[0], msm_chip->regs.int_en); | |
232 | spin_unlock_irqrestore(&msm_chip->lock, irq_flags); | |
233 | } | |
234 | ||
235 | static void msm_gpio_irq_unmask(unsigned int irq) | |
236 | { | |
237 | unsigned long irq_flags; | |
238 | struct msm_gpio_chip *msm_chip = get_irq_chip_data(irq); | |
239 | unsigned offset = irq - gpio_to_irq(msm_chip->chip.base); | |
240 | ||
241 | spin_lock_irqsave(&msm_chip->lock, irq_flags); | |
242 | /* level triggered interrupts are also latched */ | |
243 | if (!(readl(msm_chip->regs.int_edge) & BIT(offset))) | |
244 | msm_gpio_clear_detect_status(msm_chip, offset); | |
245 | msm_chip->int_enable[0] |= BIT(offset); | |
246 | writel(msm_chip->int_enable[0], msm_chip->regs.int_en); | |
247 | spin_unlock_irqrestore(&msm_chip->lock, irq_flags); | |
248 | } | |
249 | ||
250 | static int msm_gpio_irq_set_wake(unsigned int irq, unsigned int on) | |
251 | { | |
252 | unsigned long irq_flags; | |
253 | struct msm_gpio_chip *msm_chip = get_irq_chip_data(irq); | |
254 | unsigned offset = irq - gpio_to_irq(msm_chip->chip.base); | |
255 | ||
256 | spin_lock_irqsave(&msm_chip->lock, irq_flags); | |
257 | ||
258 | if (on) | |
259 | msm_chip->int_enable[1] |= BIT(offset); | |
260 | else | |
261 | msm_chip->int_enable[1] &= ~BIT(offset); | |
262 | ||
263 | spin_unlock_irqrestore(&msm_chip->lock, irq_flags); | |
264 | return 0; | |
265 | } | |
266 | ||
267 | static int msm_gpio_irq_set_type(unsigned int irq, unsigned int flow_type) | |
268 | { | |
269 | unsigned long irq_flags; | |
270 | struct msm_gpio_chip *msm_chip = get_irq_chip_data(irq); | |
271 | unsigned offset = irq - gpio_to_irq(msm_chip->chip.base); | |
272 | unsigned val, mask = BIT(offset); | |
273 | ||
274 | spin_lock_irqsave(&msm_chip->lock, irq_flags); | |
275 | val = readl(msm_chip->regs.int_edge); | |
276 | if (flow_type & IRQ_TYPE_EDGE_BOTH) { | |
277 | writel(val | mask, msm_chip->regs.int_edge); | |
278 | irq_desc[irq].handle_irq = handle_edge_irq; | |
279 | } else { | |
280 | writel(val & ~mask, msm_chip->regs.int_edge); | |
281 | irq_desc[irq].handle_irq = handle_level_irq; | |
282 | } | |
283 | if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { | |
284 | msm_chip->both_edge_detect |= mask; | |
285 | msm_gpio_update_both_edge_detect(msm_chip); | |
286 | } else { | |
287 | msm_chip->both_edge_detect &= ~mask; | |
288 | val = readl(msm_chip->regs.int_pos); | |
289 | if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_HIGH)) | |
290 | writel(val | mask, msm_chip->regs.int_pos); | |
291 | else | |
292 | writel(val & ~mask, msm_chip->regs.int_pos); | |
293 | } | |
294 | spin_unlock_irqrestore(&msm_chip->lock, irq_flags); | |
295 | return 0; | |
296 | } | |
297 | ||
298 | static void msm_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) | |
299 | { | |
300 | int i, j, mask; | |
301 | unsigned val; | |
302 | ||
303 | for (i = 0; i < ARRAY_SIZE(msm_gpio_chips); i++) { | |
304 | struct msm_gpio_chip *msm_chip = &msm_gpio_chips[i]; | |
305 | val = readl(msm_chip->regs.int_status); | |
306 | val &= msm_chip->int_enable[0]; | |
307 | while (val) { | |
308 | mask = val & -val; | |
309 | j = fls(mask) - 1; | |
310 | /* printk("%s %08x %08x bit %d gpio %d irq %d\n", | |
311 | __func__, v, m, j, msm_chip->chip.start + j, | |
312 | FIRST_GPIO_IRQ + msm_chip->chip.start + j); */ | |
313 | val &= ~mask; | |
314 | generic_handle_irq(FIRST_GPIO_IRQ + | |
315 | msm_chip->chip.base + j); | |
316 | } | |
317 | } | |
318 | desc->chip->ack(irq); | |
319 | } | |
320 | ||
321 | static struct irq_chip msm_gpio_irq_chip = { | |
322 | .name = "msmgpio", | |
323 | .ack = msm_gpio_irq_ack, | |
324 | .mask = msm_gpio_irq_mask, | |
325 | .unmask = msm_gpio_irq_unmask, | |
326 | .set_wake = msm_gpio_irq_set_wake, | |
327 | .set_type = msm_gpio_irq_set_type, | |
328 | }; | |
329 | ||
330 | static int __init msm_init_gpio(void) | |
331 | { | |
332 | int i, j = 0; | |
333 | ||
334 | for (i = FIRST_GPIO_IRQ; i < FIRST_GPIO_IRQ + NR_GPIO_IRQS; i++) { | |
335 | if (i - FIRST_GPIO_IRQ >= | |
336 | msm_gpio_chips[j].chip.base + | |
337 | msm_gpio_chips[j].chip.ngpio) | |
338 | j++; | |
339 | set_irq_chip_data(i, &msm_gpio_chips[j]); | |
340 | set_irq_chip(i, &msm_gpio_irq_chip); | |
341 | set_irq_handler(i, handle_edge_irq); | |
342 | set_irq_flags(i, IRQF_VALID); | |
343 | } | |
344 | ||
345 | for (i = 0; i < ARRAY_SIZE(msm_gpio_chips); i++) { | |
346 | spin_lock_init(&msm_gpio_chips[i].lock); | |
347 | writel(0, msm_gpio_chips[i].regs.int_en); | |
348 | gpiochip_add(&msm_gpio_chips[i].chip); | |
349 | } | |
350 | ||
351 | set_irq_chained_handler(INT_GPIO_GROUP1, msm_gpio_irq_handler); | |
352 | set_irq_chained_handler(INT_GPIO_GROUP2, msm_gpio_irq_handler); | |
353 | set_irq_wake(INT_GPIO_GROUP1, 1); | |
354 | set_irq_wake(INT_GPIO_GROUP2, 2); | |
355 | return 0; | |
356 | } | |
357 | ||
358 | postcore_initcall(msm_init_gpio); |