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msm: gpio: Fold register defs into C file
[mirror_ubuntu-artful-kernel.git] / arch / arm / mach-msm / gpio.c
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2783cc26
GB		 1/* linux/arch/arm/mach-msm/gpio.c
2 *
3 * Copyright (C) 2007 Google, Inc.
4 * Copyright (c) 2009-2010, Code Aurora Forum. All rights reserved.
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#include <linux/bitops.h>
18#include <linux/gpio.h>
19#include <linux/interrupt.h>
20#include <linux/io.h>
21#include <linux/irq.h>
22#include <linux/module.h>
10eb5f6b 23#include <mach/cpu.h>
030a77fc 24#include <mach/msm_gpiomux.h>
9def3efc
DB		 25#include <mach/msm_iomap.h>
26
27/* see 80-VA736-2 Rev C pp 695-751
28**
29** These are actually the *shadow* gpio registers, since the
30** real ones (which allow full access) are only available to the
31** ARM9 side of the world.
32**
33** Since the _BASE need to be page-aligned when we're mapping them
34** to virtual addresses, adjust for the additional offset in these
35** macros.
36*/
37
38#define MSM_GPIO1_REG(off) (MSM_GPIO1_BASE + (off))
39#define MSM_GPIO2_REG(off) (MSM_GPIO2_BASE + 0x400 + (off))
40#define MSM_GPIO1_SHADOW_REG(off) (MSM_GPIO1_BASE + 0x800 + (off))
41#define MSM_GPIO2_SHADOW_REG(off) (MSM_GPIO2_BASE + 0xC00 + (off))
42
43/*
44 * MSM7X00 registers
45 */
46/* output value */
47#define MSM7X00_GPIO_OUT_0 MSM_GPIO1_SHADOW_REG(0x00) /* gpio 15-0 */
48#define MSM7X00_GPIO_OUT_1 MSM_GPIO2_SHADOW_REG(0x00) /* gpio 42-16 */
49#define MSM7X00_GPIO_OUT_2 MSM_GPIO1_SHADOW_REG(0x04) /* gpio 67-43 */
50#define MSM7X00_GPIO_OUT_3 MSM_GPIO1_SHADOW_REG(0x08) /* gpio 94-68 */
51#define MSM7X00_GPIO_OUT_4 MSM_GPIO1_SHADOW_REG(0x0C) /* gpio 106-95 */
52#define MSM7X00_GPIO_OUT_5 MSM_GPIO1_SHADOW_REG(0x50) /* gpio 107-121 */
53
54/* same pin map as above, output enable */
55#define MSM7X00_GPIO_OE_0 MSM_GPIO1_SHADOW_REG(0x10)
56#define MSM7X00_GPIO_OE_1 MSM_GPIO2_SHADOW_REG(0x08)
57#define MSM7X00_GPIO_OE_2 MSM_GPIO1_SHADOW_REG(0x14)
58#define MSM7X00_GPIO_OE_3 MSM_GPIO1_SHADOW_REG(0x18)
59#define MSM7X00_GPIO_OE_4 MSM_GPIO1_SHADOW_REG(0x1C)
60#define MSM7X00_GPIO_OE_5 MSM_GPIO1_SHADOW_REG(0x54)
61
62/* same pin map as above, input read */
63#define MSM7X00_GPIO_IN_0 MSM_GPIO1_SHADOW_REG(0x34)
64#define MSM7X00_GPIO_IN_1 MSM_GPIO2_SHADOW_REG(0x20)
65#define MSM7X00_GPIO_IN_2 MSM_GPIO1_SHADOW_REG(0x38)
66#define MSM7X00_GPIO_IN_3 MSM_GPIO1_SHADOW_REG(0x3C)
67#define MSM7X00_GPIO_IN_4 MSM_GPIO1_SHADOW_REG(0x40)
68#define MSM7X00_GPIO_IN_5 MSM_GPIO1_SHADOW_REG(0x44)
69
70/* same pin map as above, 1=edge 0=level interrup */
71#define MSM7X00_GPIO_INT_EDGE_0 MSM_GPIO1_SHADOW_REG(0x60)
72#define MSM7X00_GPIO_INT_EDGE_1 MSM_GPIO2_SHADOW_REG(0x50)
73#define MSM7X00_GPIO_INT_EDGE_2 MSM_GPIO1_SHADOW_REG(0x64)
74#define MSM7X00_GPIO_INT_EDGE_3 MSM_GPIO1_SHADOW_REG(0x68)
75#define MSM7X00_GPIO_INT_EDGE_4 MSM_GPIO1_SHADOW_REG(0x6C)
76#define MSM7X00_GPIO_INT_EDGE_5 MSM_GPIO1_SHADOW_REG(0xC0)
77
78/* same pin map as above, 1=positive 0=negative */
79#define MSM7X00_GPIO_INT_POS_0 MSM_GPIO1_SHADOW_REG(0x70)
80#define MSM7X00_GPIO_INT_POS_1 MSM_GPIO2_SHADOW_REG(0x58)
81#define MSM7X00_GPIO_INT_POS_2 MSM_GPIO1_SHADOW_REG(0x74)
82#define MSM7X00_GPIO_INT_POS_3 MSM_GPIO1_SHADOW_REG(0x78)
83#define MSM7X00_GPIO_INT_POS_4 MSM_GPIO1_SHADOW_REG(0x7C)
84#define MSM7X00_GPIO_INT_POS_5 MSM_GPIO1_SHADOW_REG(0xBC)
85
86/* same pin map as above, interrupt enable */
87#define MSM7X00_GPIO_INT_EN_0 MSM_GPIO1_SHADOW_REG(0x80)
88#define MSM7X00_GPIO_INT_EN_1 MSM_GPIO2_SHADOW_REG(0x60)
89#define MSM7X00_GPIO_INT_EN_2 MSM_GPIO1_SHADOW_REG(0x84)
90#define MSM7X00_GPIO_INT_EN_3 MSM_GPIO1_SHADOW_REG(0x88)
91#define MSM7X00_GPIO_INT_EN_4 MSM_GPIO1_SHADOW_REG(0x8C)
92#define MSM7X00_GPIO_INT_EN_5 MSM_GPIO1_SHADOW_REG(0xB8)
93
94/* same pin map as above, write 1 to clear interrupt */
95#define MSM7X00_GPIO_INT_CLEAR_0 MSM_GPIO1_SHADOW_REG(0x90)
96#define MSM7X00_GPIO_INT_CLEAR_1 MSM_GPIO2_SHADOW_REG(0x68)
97#define MSM7X00_GPIO_INT_CLEAR_2 MSM_GPIO1_SHADOW_REG(0x94)
98#define MSM7X00_GPIO_INT_CLEAR_3 MSM_GPIO1_SHADOW_REG(0x98)
99#define MSM7X00_GPIO_INT_CLEAR_4 MSM_GPIO1_SHADOW_REG(0x9C)
100#define MSM7X00_GPIO_INT_CLEAR_5 MSM_GPIO1_SHADOW_REG(0xB4)
101
102/* same pin map as above, 1=interrupt pending */
103#define MSM7X00_GPIO_INT_STATUS_0 MSM_GPIO1_SHADOW_REG(0xA0)
104#define MSM7X00_GPIO_INT_STATUS_1 MSM_GPIO2_SHADOW_REG(0x70)
105#define MSM7X00_GPIO_INT_STATUS_2 MSM_GPIO1_SHADOW_REG(0xA4)
106#define MSM7X00_GPIO_INT_STATUS_3 MSM_GPIO1_SHADOW_REG(0xA8)
107#define MSM7X00_GPIO_INT_STATUS_4 MSM_GPIO1_SHADOW_REG(0xAC)
108#define MSM7X00_GPIO_INT_STATUS_5 MSM_GPIO1_SHADOW_REG(0xB0)
109
110/*
111 * QSD8X50 registers
112 */
113/* output value */
114#define QSD8X50_GPIO_OUT_0 MSM_GPIO1_SHADOW_REG(0x00) /* gpio 15-0 */
115#define QSD8X50_GPIO_OUT_1 MSM_GPIO2_SHADOW_REG(0x00) /* gpio 42-16 */
116#define QSD8X50_GPIO_OUT_2 MSM_GPIO1_SHADOW_REG(0x04) /* gpio 67-43 */
117#define QSD8X50_GPIO_OUT_3 MSM_GPIO1_SHADOW_REG(0x08) /* gpio 94-68 */
118#define QSD8X50_GPIO_OUT_4 MSM_GPIO1_SHADOW_REG(0x0C) /* gpio 103-95 */
119#define QSD8X50_GPIO_OUT_5 MSM_GPIO1_SHADOW_REG(0x10) /* gpio 121-104 */
120#define QSD8X50_GPIO_OUT_6 MSM_GPIO1_SHADOW_REG(0x14) /* gpio 152-122 */
121#define QSD8X50_GPIO_OUT_7 MSM_GPIO1_SHADOW_REG(0x18) /* gpio 164-153 */
122
123/* same pin map as above, output enable */
124#define QSD8X50_GPIO_OE_0 MSM_GPIO1_SHADOW_REG(0x20)
125#define QSD8X50_GPIO_OE_1 MSM_GPIO2_SHADOW_REG(0x08)
126#define QSD8X50_GPIO_OE_2 MSM_GPIO1_SHADOW_REG(0x24)
127#define QSD8X50_GPIO_OE_3 MSM_GPIO1_SHADOW_REG(0x28)
128#define QSD8X50_GPIO_OE_4 MSM_GPIO1_SHADOW_REG(0x2C)
129#define QSD8X50_GPIO_OE_5 MSM_GPIO1_SHADOW_REG(0x30)
130#define QSD8X50_GPIO_OE_6 MSM_GPIO1_SHADOW_REG(0x34)
131#define QSD8X50_GPIO_OE_7 MSM_GPIO1_SHADOW_REG(0x38)
132
133/* same pin map as above, input read */
134#define QSD8X50_GPIO_IN_0 MSM_GPIO1_SHADOW_REG(0x50)
135#define QSD8X50_GPIO_IN_1 MSM_GPIO2_SHADOW_REG(0x20)
136#define QSD8X50_GPIO_IN_2 MSM_GPIO1_SHADOW_REG(0x54)
137#define QSD8X50_GPIO_IN_3 MSM_GPIO1_SHADOW_REG(0x58)
138#define QSD8X50_GPIO_IN_4 MSM_GPIO1_SHADOW_REG(0x5C)
139#define QSD8X50_GPIO_IN_5 MSM_GPIO1_SHADOW_REG(0x60)
140#define QSD8X50_GPIO_IN_6 MSM_GPIO1_SHADOW_REG(0x64)
141#define QSD8X50_GPIO_IN_7 MSM_GPIO1_SHADOW_REG(0x68)
142
143/* same pin map as above, 1=edge 0=level interrup */
144#define QSD8X50_GPIO_INT_EDGE_0 MSM_GPIO1_SHADOW_REG(0x70)
145#define QSD8X50_GPIO_INT_EDGE_1 MSM_GPIO2_SHADOW_REG(0x50)
146#define QSD8X50_GPIO_INT_EDGE_2 MSM_GPIO1_SHADOW_REG(0x74)
147#define QSD8X50_GPIO_INT_EDGE_3 MSM_GPIO1_SHADOW_REG(0x78)
148#define QSD8X50_GPIO_INT_EDGE_4 MSM_GPIO1_SHADOW_REG(0x7C)
149#define QSD8X50_GPIO_INT_EDGE_5 MSM_GPIO1_SHADOW_REG(0x80)
150#define QSD8X50_GPIO_INT_EDGE_6 MSM_GPIO1_SHADOW_REG(0x84)
151#define QSD8X50_GPIO_INT_EDGE_7 MSM_GPIO1_SHADOW_REG(0x88)
152
153/* same pin map as above, 1=positive 0=negative */
154#define QSD8X50_GPIO_INT_POS_0 MSM_GPIO1_SHADOW_REG(0x90)
155#define QSD8X50_GPIO_INT_POS_1 MSM_GPIO2_SHADOW_REG(0x58)
156#define QSD8X50_GPIO_INT_POS_2 MSM_GPIO1_SHADOW_REG(0x94)
157#define QSD8X50_GPIO_INT_POS_3 MSM_GPIO1_SHADOW_REG(0x98)
158#define QSD8X50_GPIO_INT_POS_4 MSM_GPIO1_SHADOW_REG(0x9C)
159#define QSD8X50_GPIO_INT_POS_5 MSM_GPIO1_SHADOW_REG(0xA0)
160#define QSD8X50_GPIO_INT_POS_6 MSM_GPIO1_SHADOW_REG(0xA4)
161#define QSD8X50_GPIO_INT_POS_7 MSM_GPIO1_SHADOW_REG(0xA8)
162
163/* same pin map as above, interrupt enable */
164#define QSD8X50_GPIO_INT_EN_0 MSM_GPIO1_SHADOW_REG(0xB0)
165#define QSD8X50_GPIO_INT_EN_1 MSM_GPIO2_SHADOW_REG(0x60)
166#define QSD8X50_GPIO_INT_EN_2 MSM_GPIO1_SHADOW_REG(0xB4)
167#define QSD8X50_GPIO_INT_EN_3 MSM_GPIO1_SHADOW_REG(0xB8)
168#define QSD8X50_GPIO_INT_EN_4 MSM_GPIO1_SHADOW_REG(0xBC)
169#define QSD8X50_GPIO_INT_EN_5 MSM_GPIO1_SHADOW_REG(0xC0)
170#define QSD8X50_GPIO_INT_EN_6 MSM_GPIO1_SHADOW_REG(0xC4)
171#define QSD8X50_GPIO_INT_EN_7 MSM_GPIO1_SHADOW_REG(0xC8)
172
173/* same pin map as above, write 1 to clear interrupt */
174#define QSD8X50_GPIO_INT_CLEAR_0 MSM_GPIO1_SHADOW_REG(0xD0)
175#define QSD8X50_GPIO_INT_CLEAR_1 MSM_GPIO2_SHADOW_REG(0x68)
176#define QSD8X50_GPIO_INT_CLEAR_2 MSM_GPIO1_SHADOW_REG(0xD4)
177#define QSD8X50_GPIO_INT_CLEAR_3 MSM_GPIO1_SHADOW_REG(0xD8)
178#define QSD8X50_GPIO_INT_CLEAR_4 MSM_GPIO1_SHADOW_REG(0xDC)
179#define QSD8X50_GPIO_INT_CLEAR_5 MSM_GPIO1_SHADOW_REG(0xE0)
180#define QSD8X50_GPIO_INT_CLEAR_6 MSM_GPIO1_SHADOW_REG(0xE4)
181#define QSD8X50_GPIO_INT_CLEAR_7 MSM_GPIO1_SHADOW_REG(0xE8)
182
183/* same pin map as above, 1=interrupt pending */
184#define QSD8X50_GPIO_INT_STATUS_0 MSM_GPIO1_SHADOW_REG(0xF0)
185#define QSD8X50_GPIO_INT_STATUS_1 MSM_GPIO2_SHADOW_REG(0x70)
186#define QSD8X50_GPIO_INT_STATUS_2 MSM_GPIO1_SHADOW_REG(0xF4)
187#define QSD8X50_GPIO_INT_STATUS_3 MSM_GPIO1_SHADOW_REG(0xF8)
188#define QSD8X50_GPIO_INT_STATUS_4 MSM_GPIO1_SHADOW_REG(0xFC)
189#define QSD8X50_GPIO_INT_STATUS_5 MSM_GPIO1_SHADOW_REG(0x100)
190#define QSD8X50_GPIO_INT_STATUS_6 MSM_GPIO1_SHADOW_REG(0x104)
191#define QSD8X50_GPIO_INT_STATUS_7 MSM_GPIO1_SHADOW_REG(0x108)
192
193/*
194 * MSM7X30 registers
195 */
196/* output value */
197#define MSM7X30_GPIO_OUT_0 MSM_GPIO1_REG(0x00) /* gpio 15-0 */
198#define MSM7X30_GPIO_OUT_1 MSM_GPIO2_REG(0x00) /* gpio 43-16 */
199#define MSM7X30_GPIO_OUT_2 MSM_GPIO1_REG(0x04) /* gpio 67-44 */
200#define MSM7X30_GPIO_OUT_3 MSM_GPIO1_REG(0x08) /* gpio 94-68 */
201#define MSM7X30_GPIO_OUT_4 MSM_GPIO1_REG(0x0C) /* gpio 106-95 */
202#define MSM7X30_GPIO_OUT_5 MSM_GPIO1_REG(0x50) /* gpio 133-107 */
203#define MSM7X30_GPIO_OUT_6 MSM_GPIO1_REG(0xC4) /* gpio 150-134 */
204#define MSM7X30_GPIO_OUT_7 MSM_GPIO1_REG(0x214) /* gpio 181-151 */
205
206/* same pin map as above, output enable */
207#define MSM7X30_GPIO_OE_0 MSM_GPIO1_REG(0x10)
208#define MSM7X30_GPIO_OE_1 MSM_GPIO2_REG(0x08)
209#define MSM7X30_GPIO_OE_2 MSM_GPIO1_REG(0x14)
210#define MSM7X30_GPIO_OE_3 MSM_GPIO1_REG(0x18)
211#define MSM7X30_GPIO_OE_4 MSM_GPIO1_REG(0x1C)
212#define MSM7X30_GPIO_OE_5 MSM_GPIO1_REG(0x54)
213#define MSM7X30_GPIO_OE_6 MSM_GPIO1_REG(0xC8)
214#define MSM7X30_GPIO_OE_7 MSM_GPIO1_REG(0x218)
215
216/* same pin map as above, input read */
217#define MSM7X30_GPIO_IN_0 MSM_GPIO1_REG(0x34)
218#define MSM7X30_GPIO_IN_1 MSM_GPIO2_REG(0x20)
219#define MSM7X30_GPIO_IN_2 MSM_GPIO1_REG(0x38)
220#define MSM7X30_GPIO_IN_3 MSM_GPIO1_REG(0x3C)
221#define MSM7X30_GPIO_IN_4 MSM_GPIO1_REG(0x40)
222#define MSM7X30_GPIO_IN_5 MSM_GPIO1_REG(0x44)
223#define MSM7X30_GPIO_IN_6 MSM_GPIO1_REG(0xCC)
224#define MSM7X30_GPIO_IN_7 MSM_GPIO1_REG(0x21C)
225
226/* same pin map as above, 1=edge 0=level interrup */
227#define MSM7X30_GPIO_INT_EDGE_0 MSM_GPIO1_REG(0x60)
228#define MSM7X30_GPIO_INT_EDGE_1 MSM_GPIO2_REG(0x50)
229#define MSM7X30_GPIO_INT_EDGE_2 MSM_GPIO1_REG(0x64)
230#define MSM7X30_GPIO_INT_EDGE_3 MSM_GPIO1_REG(0x68)
231#define MSM7X30_GPIO_INT_EDGE_4 MSM_GPIO1_REG(0x6C)
232#define MSM7X30_GPIO_INT_EDGE_5 MSM_GPIO1_REG(0xC0)
233#define MSM7X30_GPIO_INT_EDGE_6 MSM_GPIO1_REG(0xD0)
234#define MSM7X30_GPIO_INT_EDGE_7 MSM_GPIO1_REG(0x240)
235
236/* same pin map as above, 1=positive 0=negative */
237#define MSM7X30_GPIO_INT_POS_0 MSM_GPIO1_REG(0x70)
238#define MSM7X30_GPIO_INT_POS_1 MSM_GPIO2_REG(0x58)
239#define MSM7X30_GPIO_INT_POS_2 MSM_GPIO1_REG(0x74)
240#define MSM7X30_GPIO_INT_POS_3 MSM_GPIO1_REG(0x78)
241#define MSM7X30_GPIO_INT_POS_4 MSM_GPIO1_REG(0x7C)
242#define MSM7X30_GPIO_INT_POS_5 MSM_GPIO1_REG(0xBC)
243#define MSM7X30_GPIO_INT_POS_6 MSM_GPIO1_REG(0xD4)
244#define MSM7X30_GPIO_INT_POS_7 MSM_GPIO1_REG(0x228)
245
246/* same pin map as above, interrupt enable */
247#define MSM7X30_GPIO_INT_EN_0 MSM_GPIO1_REG(0x80)
248#define MSM7X30_GPIO_INT_EN_1 MSM_GPIO2_REG(0x60)
249#define MSM7X30_GPIO_INT_EN_2 MSM_GPIO1_REG(0x84)
250#define MSM7X30_GPIO_INT_EN_3 MSM_GPIO1_REG(0x88)
251#define MSM7X30_GPIO_INT_EN_4 MSM_GPIO1_REG(0x8C)
252#define MSM7X30_GPIO_INT_EN_5 MSM_GPIO1_REG(0xB8)
253#define MSM7X30_GPIO_INT_EN_6 MSM_GPIO1_REG(0xD8)
254#define MSM7X30_GPIO_INT_EN_7 MSM_GPIO1_REG(0x22C)
255
256/* same pin map as above, write 1 to clear interrupt */
257#define MSM7X30_GPIO_INT_CLEAR_0 MSM_GPIO1_REG(0x90)
258#define MSM7X30_GPIO_INT_CLEAR_1 MSM_GPIO2_REG(0x68)
259#define MSM7X30_GPIO_INT_CLEAR_2 MSM_GPIO1_REG(0x94)
260#define MSM7X30_GPIO_INT_CLEAR_3 MSM_GPIO1_REG(0x98)
261#define MSM7X30_GPIO_INT_CLEAR_4 MSM_GPIO1_REG(0x9C)
262#define MSM7X30_GPIO_INT_CLEAR_5 MSM_GPIO1_REG(0xB4)
263#define MSM7X30_GPIO_INT_CLEAR_6 MSM_GPIO1_REG(0xDC)
264#define MSM7X30_GPIO_INT_CLEAR_7 MSM_GPIO1_REG(0x230)
265
266/* same pin map as above, 1=interrupt pending */
267#define MSM7X30_GPIO_INT_STATUS_0 MSM_GPIO1_REG(0xA0)
268#define MSM7X30_GPIO_INT_STATUS_1 MSM_GPIO2_REG(0x70)
269#define MSM7X30_GPIO_INT_STATUS_2 MSM_GPIO1_REG(0xA4)
270#define MSM7X30_GPIO_INT_STATUS_3 MSM_GPIO1_REG(0xA8)
271#define MSM7X30_GPIO_INT_STATUS_4 MSM_GPIO1_REG(0xAC)
272#define MSM7X30_GPIO_INT_STATUS_5 MSM_GPIO1_REG(0xB0)
273#define MSM7X30_GPIO_INT_STATUS_6 MSM_GPIO1_REG(0xE0)
274#define MSM7X30_GPIO_INT_STATUS_7 MSM_GPIO1_REG(0x234)
2783cc26
GB		 275
276#define FIRST_GPIO_IRQ MSM_GPIO_TO_INT(0)
277
2e01d2c5 278#define MSM_GPIO_BANK(soc, bank, first, last) \
2783cc26
GB		 279 { \
280 .regs = { \
2e01d2c5
DB		 281 .out = soc##_GPIO_OUT_##bank, \
282 .in = soc##_GPIO_IN_##bank, \
283 .int_status = soc##_GPIO_INT_STATUS_##bank, \
284 .int_clear = soc##_GPIO_INT_CLEAR_##bank, \
285 .int_en = soc##_GPIO_INT_EN_##bank, \
286 .int_edge = soc##_GPIO_INT_EDGE_##bank, \
287 .int_pos = soc##_GPIO_INT_POS_##bank, \
288 .oe = soc##_GPIO_OE_##bank, \
2783cc26
GB		 289 }, \
290 .chip = { \
291 .base = (first), \
292 .ngpio = (last) - (first) + 1, \
293 .get = msm_gpio_get, \
294 .set = msm_gpio_set, \
295 .direction_input = msm_gpio_direction_input, \
296 .direction_output = msm_gpio_direction_output, \
297 .to_irq = msm_gpio_to_irq, \
26cc6660
GB		 298 .request = msm_gpio_request, \
299 .free = msm_gpio_free, \
2783cc26
GB		 300 } \
301 }
302
303#define MSM_GPIO_BROKEN_INT_CLEAR 1
304
305struct msm_gpio_regs {
306 void __iomem *out;
307 void __iomem *in;
308 void __iomem *int_status;
309 void __iomem *int_clear;
310 void __iomem *int_en;
311 void __iomem *int_edge;
312 void __iomem *int_pos;
313 void __iomem *oe;
314};
315
316struct msm_gpio_chip {
317 spinlock_t lock;
318 struct gpio_chip chip;
319 struct msm_gpio_regs regs;
320#if MSM_GPIO_BROKEN_INT_CLEAR
321 unsigned int_status_copy;
322#endif
323 unsigned int both_edge_detect;
324 unsigned int int_enable[2]; /* 0: awake, 1: sleep */
325};
326
327static int msm_gpio_write(struct msm_gpio_chip *msm_chip,
328 unsigned offset, unsigned on)
329{
330 unsigned mask = BIT(offset);
331 unsigned val;
332
333 val = readl(msm_chip->regs.out);
334 if (on)
335 writel(val | mask, msm_chip->regs.out);
336 else
337 writel(val & ~mask, msm_chip->regs.out);
338 return 0;
339}
340
341static void msm_gpio_update_both_edge_detect(struct msm_gpio_chip *msm_chip)
342{
343 int loop_limit = 100;
344 unsigned pol, val, val2, intstat;
345 do {
346 val = readl(msm_chip->regs.in);
347 pol = readl(msm_chip->regs.int_pos);
348 pol = (pol & ~msm_chip->both_edge_detect) |
349 (~val & msm_chip->both_edge_detect);
350 writel(pol, msm_chip->regs.int_pos);
351 intstat = readl(msm_chip->regs.int_status);
352 val2 = readl(msm_chip->regs.in);
353 if (((val ^ val2) & msm_chip->both_edge_detect & ~intstat) == 0)
354 return;
355 } while (loop_limit-- > 0);
356 printk(KERN_ERR "msm_gpio_update_both_edge_detect, "
357 "failed to reach stable state %x != %x\n", val, val2);
358}
359
360static int msm_gpio_clear_detect_status(struct msm_gpio_chip *msm_chip,
361 unsigned offset)
362{
363 unsigned bit = BIT(offset);
364
365#if MSM_GPIO_BROKEN_INT_CLEAR
366 /* Save interrupts that already triggered before we loose them. */
367 /* Any interrupt that triggers between the read of int_status */
368 /* and the write to int_clear will still be lost though. */
369 msm_chip->int_status_copy |= readl(msm_chip->regs.int_status);
370 msm_chip->int_status_copy &= ~bit;
371#endif
372 writel(bit, msm_chip->regs.int_clear);
373 msm_gpio_update_both_edge_detect(msm_chip);
374 return 0;
375}
376
377static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
378{
379 struct msm_gpio_chip *msm_chip;
380 unsigned long irq_flags;
381
382 msm_chip = container_of(chip, struct msm_gpio_chip, chip);
383 spin_lock_irqsave(&msm_chip->lock, irq_flags);
384 writel(readl(msm_chip->regs.oe) & ~BIT(offset), msm_chip->regs.oe);
385 spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
386 return 0;
387}
388
389static int
390msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value)
391{
392 struct msm_gpio_chip *msm_chip;
393 unsigned long irq_flags;
394
395 msm_chip = container_of(chip, struct msm_gpio_chip, chip);
396 spin_lock_irqsave(&msm_chip->lock, irq_flags);
397 msm_gpio_write(msm_chip, offset, value);
398 writel(readl(msm_chip->regs.oe) | BIT(offset), msm_chip->regs.oe);
399 spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
400 return 0;
401}
402
403static int msm_gpio_get(struct gpio_chip *chip, unsigned offset)
404{
405 struct msm_gpio_chip *msm_chip;
406
407 msm_chip = container_of(chip, struct msm_gpio_chip, chip);
408 return (readl(msm_chip->regs.in) & (1U << offset)) ? 1 : 0;
409}
410
411static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
412{
413 struct msm_gpio_chip *msm_chip;
414 unsigned long irq_flags;
415
416 msm_chip = container_of(chip, struct msm_gpio_chip, chip);
417 spin_lock_irqsave(&msm_chip->lock, irq_flags);
418 msm_gpio_write(msm_chip, offset, value);
419 spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
420}
421
422static int msm_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
423{
424 return MSM_GPIO_TO_INT(chip->base + offset);
425}
426
26cc6660
GB		 427#ifdef CONFIG_MSM_GPIOMUX
428static int msm_gpio_request(struct gpio_chip *chip, unsigned offset)
429{
430 return msm_gpiomux_get(chip->base + offset);
431}
432
433static void msm_gpio_free(struct gpio_chip *chip, unsigned offset)
434{
435 msm_gpiomux_put(chip->base + offset);
436}
437#else
438#define msm_gpio_request NULL
439#define msm_gpio_free NULL
440#endif
441
10eb5f6b
DB		 442static struct msm_gpio_chip *msm_gpio_chips;
443static int msm_gpio_count;
444
445static struct msm_gpio_chip msm_gpio_chips_msm7x01[] = {
2e01d2c5
DB		 446 MSM_GPIO_BANK(MSM7X00, 0, 0, 15),
447 MSM_GPIO_BANK(MSM7X00, 1, 16, 42),
448 MSM_GPIO_BANK(MSM7X00, 2, 43, 67),
449 MSM_GPIO_BANK(MSM7X00, 3, 68, 94),
450 MSM_GPIO_BANK(MSM7X00, 4, 95, 106),
451 MSM_GPIO_BANK(MSM7X00, 5, 107, 121),
10eb5f6b
DB		 452};
453
454static struct msm_gpio_chip msm_gpio_chips_msm7x30[] = {
2e01d2c5
DB		 455 MSM_GPIO_BANK(MSM7X30, 0, 0, 15),
456 MSM_GPIO_BANK(MSM7X30, 1, 16, 43),
457 MSM_GPIO_BANK(MSM7X30, 2, 44, 67),
458 MSM_GPIO_BANK(MSM7X30, 3, 68, 94),
459 MSM_GPIO_BANK(MSM7X30, 4, 95, 106),
460 MSM_GPIO_BANK(MSM7X30, 5, 107, 133),
461 MSM_GPIO_BANK(MSM7X30, 6, 134, 150),
462 MSM_GPIO_BANK(MSM7X30, 7, 151, 181),
10eb5f6b
DB		 463};
464
465static struct msm_gpio_chip msm_gpio_chips_qsd8x50[] = {
2e01d2c5
DB		 466 MSM_GPIO_BANK(QSD8X50, 0, 0, 15),
467 MSM_GPIO_BANK(QSD8X50, 1, 16, 42),
468 MSM_GPIO_BANK(QSD8X50, 2, 43, 67),
469 MSM_GPIO_BANK(QSD8X50, 3, 68, 94),
470 MSM_GPIO_BANK(QSD8X50, 4, 95, 103),
471 MSM_GPIO_BANK(QSD8X50, 5, 104, 121),
472 MSM_GPIO_BANK(QSD8X50, 6, 122, 152),
473 MSM_GPIO_BANK(QSD8X50, 7, 153, 164),
2783cc26
GB		 474};
475
0f86ee08 476static void msm_gpio_irq_ack(struct irq_data *d)
2783cc26
GB		 477{
478 unsigned long irq_flags;
0f86ee08 479 struct msm_gpio_chip *msm_chip = irq_data_get_irq_chip_data(d);
2783cc26
GB		 480 spin_lock_irqsave(&msm_chip->lock, irq_flags);
481 msm_gpio_clear_detect_status(msm_chip,
0f86ee08 482 d->irq - gpio_to_irq(msm_chip->chip.base));
2783cc26
GB		 483 spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
484}
485
0f86ee08 486static void msm_gpio_irq_mask(struct irq_data *d)
2783cc26
GB		 487{
488 unsigned long irq_flags;
0f86ee08
LB		 489 struct msm_gpio_chip *msm_chip = irq_data_get_irq_chip_data(d);
490 unsigned offset = d->irq - gpio_to_irq(msm_chip->chip.base);
2783cc26
GB		 491
492 spin_lock_irqsave(&msm_chip->lock, irq_flags);
493 /* level triggered interrupts are also latched */
494 if (!(readl(msm_chip->regs.int_edge) & BIT(offset)))
495 msm_gpio_clear_detect_status(msm_chip, offset);
496 msm_chip->int_enable[0] &= ~BIT(offset);
497 writel(msm_chip->int_enable[0], msm_chip->regs.int_en);
498 spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
499}
500
0f86ee08 501static void msm_gpio_irq_unmask(struct irq_data *d)
2783cc26
GB		 502{
503 unsigned long irq_flags;
0f86ee08
LB		 504 struct msm_gpio_chip *msm_chip = irq_data_get_irq_chip_data(d);
505 unsigned offset = d->irq - gpio_to_irq(msm_chip->chip.base);
2783cc26
GB		 506
507 spin_lock_irqsave(&msm_chip->lock, irq_flags);
508 /* level triggered interrupts are also latched */
509 if (!(readl(msm_chip->regs.int_edge) & BIT(offset)))
510 msm_gpio_clear_detect_status(msm_chip, offset);
511 msm_chip->int_enable[0] |= BIT(offset);
512 writel(msm_chip->int_enable[0], msm_chip->regs.int_en);
513 spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
514}
515
0f86ee08 516static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
2783cc26
GB		 517{
518 unsigned long irq_flags;
0f86ee08
LB		 519 struct msm_gpio_chip *msm_chip = irq_data_get_irq_chip_data(d);
520 unsigned offset = d->irq - gpio_to_irq(msm_chip->chip.base);
2783cc26
GB		 521
522 spin_lock_irqsave(&msm_chip->lock, irq_flags);
523
524 if (on)
525 msm_chip->int_enable[1] |= BIT(offset);
526 else
527 msm_chip->int_enable[1] &= ~BIT(offset);
528
529 spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
530 return 0;
531}
532
0f86ee08 533static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int flow_type)
2783cc26
GB		 534{
535 unsigned long irq_flags;
0f86ee08
LB		 536 struct msm_gpio_chip *msm_chip = irq_data_get_irq_chip_data(d);
537 unsigned offset = d->irq - gpio_to_irq(msm_chip->chip.base);
2783cc26
GB		 538 unsigned val, mask = BIT(offset);
539
540 spin_lock_irqsave(&msm_chip->lock, irq_flags);
541 val = readl(msm_chip->regs.int_edge);
542 if (flow_type & IRQ_TYPE_EDGE_BOTH) {
543 writel(val | mask, msm_chip->regs.int_edge);
70c4fa22 544 __irq_set_handler_locked(d->irq, handle_edge_irq);
2783cc26
GB		 545 } else {
546 writel(val & ~mask, msm_chip->regs.int_edge);
70c4fa22 547 __irq_set_handler_locked(d->irq, handle_level_irq);
2783cc26
GB		 548 }
549 if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
550 msm_chip->both_edge_detect |= mask;
551 msm_gpio_update_both_edge_detect(msm_chip);
552 } else {
553 msm_chip->both_edge_detect &= ~mask;
554 val = readl(msm_chip->regs.int_pos);
555 if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_HIGH))
556 writel(val | mask, msm_chip->regs.int_pos);
557 else
558 writel(val & ~mask, msm_chip->regs.int_pos);
559 }
560 spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
561 return 0;
562}
563
564static void msm_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
565{
566 int i, j, mask;
567 unsigned val;
568
10eb5f6b 569 for (i = 0; i < msm_gpio_count; i++) {
2783cc26
GB		 570 struct msm_gpio_chip *msm_chip = &msm_gpio_chips[i];
571 val = readl(msm_chip->regs.int_status);
572 val &= msm_chip->int_enable[0];
573 while (val) {
574 mask = val & -val;
575 j = fls(mask) - 1;
576 /* printk("%s %08x %08x bit %d gpio %d irq %d\n",
577 __func__, v, m, j, msm_chip->chip.start + j,
578 FIRST_GPIO_IRQ + msm_chip->chip.start + j); */
579 val &= ~mask;
580 generic_handle_irq(FIRST_GPIO_IRQ +
581 msm_chip->chip.base + j);
582 }
583 }
0f86ee08 584 desc->irq_data.chip->irq_ack(&desc->irq_data);
2783cc26
GB		 585}
586
587static struct irq_chip msm_gpio_irq_chip = {
0f86ee08
LB		 588 .name = "msmgpio",
589 .irq_ack = msm_gpio_irq_ack,
590 .irq_mask = msm_gpio_irq_mask,
591 .irq_unmask = msm_gpio_irq_unmask,
592 .irq_set_wake = msm_gpio_irq_set_wake,
593 .irq_set_type = msm_gpio_irq_set_type,
2783cc26
GB		 594};
595
596static int __init msm_init_gpio(void)
597{
598 int i, j = 0;
599
10eb5f6b
DB		 600 if (cpu_is_msm7x01()) {
601 msm_gpio_chips = msm_gpio_chips_msm7x01;
602 msm_gpio_count = ARRAY_SIZE(msm_gpio_chips_msm7x01);
603 } else if (cpu_is_msm7x30()) {
604 msm_gpio_chips = msm_gpio_chips_msm7x30;
605 msm_gpio_count = ARRAY_SIZE(msm_gpio_chips_msm7x30);
606 } else if (cpu_is_qsd8x50()) {
607 msm_gpio_chips = msm_gpio_chips_qsd8x50;
608 msm_gpio_count = ARRAY_SIZE(msm_gpio_chips_qsd8x50);
609 } else {
610 return 0;
611 }
612
2783cc26
GB		 613 for (i = FIRST_GPIO_IRQ; i < FIRST_GPIO_IRQ + NR_GPIO_IRQS; i++) {
614 if (i - FIRST_GPIO_IRQ >=
615 msm_gpio_chips[j].chip.base +
616 msm_gpio_chips[j].chip.ngpio)
617 j++;
6845664a 618 irq_set_chip_data(i, &msm_gpio_chips[j]);
f38c02f3
TG		 619 irq_set_chip_and_handler(i, &msm_gpio_irq_chip,
620 handle_edge_irq);
2783cc26
GB		 621 set_irq_flags(i, IRQF_VALID);
622 }
623
10eb5f6b 624 for (i = 0; i < msm_gpio_count; i++) {
2783cc26
GB		 625 spin_lock_init(&msm_gpio_chips[i].lock);
626 writel(0, msm_gpio_chips[i].regs.int_en);
627 gpiochip_add(&msm_gpio_chips[i].chip);
628 }
629
6845664a
TG		 630 irq_set_chained_handler(INT_GPIO_GROUP1, msm_gpio_irq_handler);
631 irq_set_chained_handler(INT_GPIO_GROUP2, msm_gpio_irq_handler);
632 irq_set_irq_wake(INT_GPIO_GROUP1, 1);
633 irq_set_irq_wake(INT_GPIO_GROUP2, 2);
2783cc26
GB		 634 return 0;
635}
636
637postcore_initcall(msm_init_gpio);
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