]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blame - arch/arm/mach-msm/io.c
arm: Add export.h to ARM specific files as required.
[mirror_ubuntu-artful-kernel.git] / arch / arm / mach-msm / io.c
CommitLineData
3042102a
BS
1/* arch/arm/mach-msm/io.c
2 *
cf62ffae 3 * MSM7K, QSD io support
3042102a
BS
4 *
5 * Copyright (C) 2007 Google, Inc.
8c27e6f3 6 * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
3042102a
BS
7 * Author: Brian Swetland <swetland@google.com>
8 *
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 */
19
20#include <linux/kernel.h>
21#include <linux/init.h>
fced80c7 22#include <linux/io.h>
dc28094b 23#include <linux/export.h>
3042102a 24
a09e64fb 25#include <mach/hardware.h>
3042102a 26#include <asm/page.h>
a09e64fb 27#include <mach/msm_iomap.h>
3042102a
BS
28#include <asm/mach/map.h>
29
a09e64fb 30#include <mach/board.h>
3042102a 31
8c27e6f3 32#define MSM_CHIP_DEVICE(name, chip) { \
bcc0f6af 33 .virtual = (unsigned long) MSM_##name##_BASE, \
8c27e6f3
DB
34 .pfn = __phys_to_pfn(chip##_##name##_PHYS), \
35 .length = chip##_##name##_SIZE, \
3042102a
BS
36 .type = MT_DEVICE_NONSHARED, \
37 }
38
8c27e6f3
DB
39#define MSM_DEVICE(name) MSM_CHIP_DEVICE(name, MSM)
40
cf62ffae
DW
41#if defined(CONFIG_ARCH_MSM7X00A) || defined(CONFIG_ARCH_MSM7X27) \
42 || defined(CONFIG_ARCH_MSM7X25)
3042102a
BS
43static struct map_desc msm_io_desc[] __initdata = {
44 MSM_DEVICE(VIC),
8c27e6f3 45 MSM_CHIP_DEVICE(CSR, MSM7X00),
3042102a 46 MSM_DEVICE(DMOV),
03db0729
DB
47 MSM_CHIP_DEVICE(GPIO1, MSM7X00),
48 MSM_CHIP_DEVICE(GPIO2, MSM7X00),
3042102a 49 MSM_DEVICE(CLK_CTL),
6339f669
PM
50#ifdef CONFIG_MSM_DEBUG_UART
51 MSM_DEVICE(DEBUG_UART),
b42dc44a
DZ
52#endif
53#ifdef CONFIG_ARCH_MSM7X30
54 MSM_DEVICE(GCC),
6339f669 55#endif
3042102a 56 {
bcc0f6af 57 .virtual = (unsigned long) MSM_SHARED_RAM_BASE,
cf62ffae 58 .pfn = __phys_to_pfn(MSM_SHARED_RAM_PHYS),
3042102a
BS
59 .length = MSM_SHARED_RAM_SIZE,
60 .type = MT_DEVICE,
61 },
62};
63
64void __init msm_map_common_io(void)
65{
66 /* Make sure the peripheral register window is closed, since
67 * we will use PTE flags (TEX[1]=1,B=0,C=1) to determine which
68 * pages are peripheral interface or not.
69 */
70 asm("mcr p15, 0, %0, c15, c2, 4" : : "r" (0));
3042102a
BS
71 iotable_init(msm_io_desc, ARRAY_SIZE(msm_io_desc));
72}
cf62ffae
DW
73#endif
74
75#ifdef CONFIG_ARCH_QSD8X50
76static struct map_desc qsd8x50_io_desc[] __initdata = {
77 MSM_DEVICE(VIC),
8c27e6f3 78 MSM_CHIP_DEVICE(CSR, QSD8X50),
cf62ffae 79 MSM_DEVICE(DMOV),
03db0729
DB
80 MSM_CHIP_DEVICE(GPIO1, QSD8X50),
81 MSM_CHIP_DEVICE(GPIO2, QSD8X50),
cf62ffae
DW
82 MSM_DEVICE(CLK_CTL),
83 MSM_DEVICE(SIRC),
84 MSM_DEVICE(SCPLL),
85 MSM_DEVICE(AD5),
86 MSM_DEVICE(MDC),
87#ifdef CONFIG_MSM_DEBUG_UART
88 MSM_DEVICE(DEBUG_UART),
89#endif
90 {
91 .virtual = (unsigned long) MSM_SHARED_RAM_BASE,
92 .pfn = __phys_to_pfn(MSM_SHARED_RAM_PHYS),
93 .length = MSM_SHARED_RAM_SIZE,
94 .type = MT_DEVICE,
95 },
96};
97
98void __init msm_map_qsd8x50_io(void)
99{
100 iotable_init(qsd8x50_io_desc, ARRAY_SIZE(qsd8x50_io_desc));
101}
102#endif /* CONFIG_ARCH_QSD8X50 */
3042102a 103
6cf6dfef
SM
104#ifdef CONFIG_ARCH_MSM8X60
105static struct map_desc msm8x60_io_desc[] __initdata = {
8bb06444
DB
106 MSM_CHIP_DEVICE(QGIC_DIST, MSM8X60),
107 MSM_CHIP_DEVICE(QGIC_CPU, MSM8X60),
8c27e6f3
DB
108 MSM_CHIP_DEVICE(TMR, MSM8X60),
109 MSM_CHIP_DEVICE(TMR0, MSM8X60),
6cf6dfef
SM
110 MSM_DEVICE(ACC),
111 MSM_DEVICE(GCC),
112};
113
114void __init msm_map_msm8x60_io(void)
115{
116 iotable_init(msm8x60_io_desc, ARRAY_SIZE(msm8x60_io_desc));
117}
118#endif /* CONFIG_ARCH_MSM8X60 */
119
5d0afd74
SM
120#ifdef CONFIG_ARCH_MSM8960
121static struct map_desc msm8960_io_desc[] __initdata = {
122 MSM_CHIP_DEVICE(QGIC_DIST, MSM8960),
123 MSM_CHIP_DEVICE(QGIC_CPU, MSM8960),
124 MSM_CHIP_DEVICE(TMR, MSM8960),
125 MSM_CHIP_DEVICE(TMR0, MSM8960),
126};
127
128void __init msm_map_msm8960_io(void)
129{
130 iotable_init(msm8960_io_desc, ARRAY_SIZE(msm8960_io_desc));
131}
132#endif /* CONFIG_ARCH_MSM8960 */
133
c83b2bf6
DW
134#ifdef CONFIG_ARCH_MSM7X30
135static struct map_desc msm7x30_io_desc[] __initdata = {
136 MSM_DEVICE(VIC),
8c27e6f3 137 MSM_CHIP_DEVICE(CSR, MSM7X30),
c83b2bf6 138 MSM_DEVICE(DMOV),
03db0729
DB
139 MSM_CHIP_DEVICE(GPIO1, MSM7X30),
140 MSM_CHIP_DEVICE(GPIO2, MSM7X30),
c83b2bf6
DW
141 MSM_DEVICE(CLK_CTL),
142 MSM_DEVICE(CLK_CTL_SH2),
143 MSM_DEVICE(AD5),
144 MSM_DEVICE(MDC),
145 MSM_DEVICE(ACC),
146 MSM_DEVICE(SAW),
147 MSM_DEVICE(GCC),
148 MSM_DEVICE(TCSR),
149#ifdef CONFIG_MSM_DEBUG_UART
150 MSM_DEVICE(DEBUG_UART),
151#endif
152 {
153 .virtual = (unsigned long) MSM_SHARED_RAM_BASE,
154 .pfn = __phys_to_pfn(MSM_SHARED_RAM_PHYS),
155 .length = MSM_SHARED_RAM_SIZE,
156 .type = MT_DEVICE,
157 },
158};
159
160void __init msm_map_msm7x30_io(void)
161{
162 iotable_init(msm7x30_io_desc, ARRAY_SIZE(msm7x30_io_desc));
163}
164#endif /* CONFIG_ARCH_MSM7X30 */
165
3042102a
BS
166void __iomem *
167__msm_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype)
168{
169 if (mtype == MT_DEVICE) {
170 /* The peripherals in the 88000000 - D0000000 range
b595076a 171 * are only accessible by type MT_DEVICE_NONSHARED.
3042102a
BS
172 * Adjust mtype as necessary to make this "just work."
173 */
174 if ((phys_addr >= 0x88000000) && (phys_addr < 0xD0000000))
175 mtype = MT_DEVICE_NONSHARED;
176 }
177
31aa8fd6
RK
178 return __arm_ioremap_caller(phys_addr, size, mtype,
179 __builtin_return_address(0));
3042102a 180}
4916a108 181EXPORT_SYMBOL(__msm_ioremap);