[mirror_ubuntu-artful-kernel.git] / arch / arm / mach-msm / timer.c

/* linux/arch/arm/mach-msm/timer.c
 *
 * Copyright (C) 2007 Google, Inc.
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#include <linux/init.h>
#include <linux/time.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/clk.h>
#include <linux/clockchips.h>
#include <linux/delay.h>
#include <linux/io.h>

#include <asm/mach/time.h>
#include <asm/hardware/gic.h>

#include <mach/msm_iomap.h>
#include <mach/cpu.h>

#define TIMER_MATCH_VAL         0x0000
#define TIMER_COUNT_VAL         0x0004
#define TIMER_ENABLE            0x0008
#define TIMER_ENABLE_CLR_ON_MATCH_EN    2
#define TIMER_ENABLE_EN                 1
#define TIMER_CLEAR             0x000C
#define DGT_CLK_CTL             0x0034
enum {
	DGT_CLK_CTL_DIV_1 = 0,
	DGT_CLK_CTL_DIV_2 = 1,
	DGT_CLK_CTL_DIV_3 = 2,
	DGT_CLK_CTL_DIV_4 = 3,
};
#define CSR_PROTECTION          0x0020
#define CSR_PROTECTION_EN               1

#define GPT_HZ 32768

enum timer_location {
	LOCAL_TIMER = 0,
	GLOBAL_TIMER = 1,
};

#define MSM_GLOBAL_TIMER MSM_CLOCK_DGT

/* TODO: Remove these ifdefs */
#if defined(CONFIG_ARCH_QSD8X50)
#define DGT_HZ (19200000 / 4) /* 19.2 MHz / 4 by default */
#define MSM_DGT_SHIFT (0)
#elif defined(CONFIG_ARCH_MSM7X30)
#define DGT_HZ (24576000 / 4) /* 24.576 MHz (LPXO) / 4 by default */
#define MSM_DGT_SHIFT (0)
#elif defined(CONFIG_ARCH_MSM8X60) || defined(CONFIG_ARCH_MSM8960)
#define DGT_HZ (27000000 / 4) /* 27 MHz (PXO) / 4 by default */
#define MSM_DGT_SHIFT (0)
#else
#define DGT_HZ 19200000 /* 19.2 MHz or 600 KHz after shift */
#define MSM_DGT_SHIFT (5)
#endif

struct msm_clock {
	struct clock_event_device   clockevent;
	struct clocksource          clocksource;
	struct irqaction            irq;
	void __iomem                *regbase;
	uint32_t                    freq;
	uint32_t                    shift;
	void __iomem                *global_counter;
	void __iomem                *local_counter;
};

enum {
	MSM_CLOCK_GPT,
	MSM_CLOCK_DGT,
	NR_TIMERS,
};


static struct msm_clock msm_clocks[];
static struct clock_event_device *local_clock_event;

static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evt = dev_id;
	if (smp_processor_id() != 0)
		evt = local_clock_event;
	if (evt->event_handler == NULL)
		return IRQ_HANDLED;
	evt->event_handler(evt);
	return IRQ_HANDLED;
}

static cycle_t msm_read_timer_count(struct clocksource *cs)
{
	struct msm_clock *clk = container_of(cs, struct msm_clock, clocksource);

	/*
	 * Shift timer count down by a constant due to unreliable lower bits
	 * on some targets.
	 */
	return readl(clk->global_counter) >> clk->shift;
}

static struct msm_clock *clockevent_to_clock(struct clock_event_device *evt)
{
#ifdef CONFIG_SMP
	int i;
	for (i = 0; i < NR_TIMERS; i++)
		if (evt == &(msm_clocks[i].clockevent))
			return &msm_clocks[i];
	return &msm_clocks[MSM_GLOBAL_TIMER];
#else
	return container_of(evt, struct msm_clock, clockevent);
#endif
}

static int msm_timer_set_next_event(unsigned long cycles,
				    struct clock_event_device *evt)
{
	struct msm_clock *clock = clockevent_to_clock(evt);
	uint32_t now = readl(clock->local_counter);
	uint32_t alarm = now + (cycles << clock->shift);

	writel(alarm, clock->regbase + TIMER_MATCH_VAL);
	return 0;
}

static void msm_timer_set_mode(enum clock_event_mode mode,
			      struct clock_event_device *evt)
{
	struct msm_clock *clock = clockevent_to_clock(evt);

	switch (mode) {
	case CLOCK_EVT_MODE_RESUME:
	case CLOCK_EVT_MODE_PERIODIC:
		break;
	case CLOCK_EVT_MODE_ONESHOT:
		writel(TIMER_ENABLE_EN, clock->regbase + TIMER_ENABLE);
		break;
	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
		writel(0, clock->regbase + TIMER_ENABLE);
		break;
	}
}

static struct msm_clock msm_clocks[] = {
	[MSM_CLOCK_GPT] = {
		.clockevent = {
			.name           = "gp_timer",
			.features       = CLOCK_EVT_FEAT_ONESHOT,
			.shift          = 32,
			.rating         = 200,
			.set_next_event = msm_timer_set_next_event,
			.set_mode       = msm_timer_set_mode,
		},
		.clocksource = {
			.name           = "gp_timer",
			.rating         = 200,
			.read           = msm_read_timer_count,
			.mask           = CLOCKSOURCE_MASK(32),
			.flags          = CLOCK_SOURCE_IS_CONTINUOUS,
		},
		.irq = {
			.name    = "gp_timer",
			.flags   = IRQF_DISABLED | IRQF_TIMER | IRQF_TRIGGER_RISING,
			.handler = msm_timer_interrupt,
			.dev_id  = &msm_clocks[0].clockevent,
			.irq     = INT_GP_TIMER_EXP
		},
		.freq = GPT_HZ,
	},
	[MSM_CLOCK_DGT] = {
		.clockevent = {
			.name           = "dg_timer",
			.features       = CLOCK_EVT_FEAT_ONESHOT,
			.shift          = 32 + MSM_DGT_SHIFT,
			.rating         = 300,
			.set_next_event = msm_timer_set_next_event,
			.set_mode       = msm_timer_set_mode,
		},
		.clocksource = {
			.name           = "dg_timer",
			.rating         = 300,
			.read           = msm_read_timer_count,
			.mask           = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT)),
			.flags          = CLOCK_SOURCE_IS_CONTINUOUS,
		},
		.irq = {
			.name    = "dg_timer",
			.flags   = IRQF_DISABLED | IRQF_TIMER | IRQF_TRIGGER_RISING,
			.handler = msm_timer_interrupt,
			.dev_id  = &msm_clocks[1].clockevent,
			.irq     = INT_DEBUG_TIMER_EXP
		},
		.freq = DGT_HZ >> MSM_DGT_SHIFT,
		.shift = MSM_DGT_SHIFT,
	}
};

static void __init msm_timer_init(void)
{
	int i;
	int res;
	int global_offset = 0;

	if (cpu_is_msm7x01()) {
		msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE;
		msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x10;
	} else if (cpu_is_msm7x30()) {
		msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE + 0x04;
		msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x24;
	} else if (cpu_is_qsd8x50()) {
		msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE;
		msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x10;
	} else if (cpu_is_msm8x60() || cpu_is_msm8960()) {
		msm_clocks[MSM_CLOCK_GPT].regbase = MSM_TMR_BASE + 0x04;
		msm_clocks[MSM_CLOCK_DGT].regbase = MSM_TMR_BASE + 0x24;

		/* Use CPU0's timer as the global timer. */
		global_offset = MSM_TMR0_BASE - MSM_TMR_BASE;
	} else
		BUG();

#ifdef CONFIG_ARCH_MSM_SCORPIONMP
	writel(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL);
#endif

	for (i = 0; i < ARRAY_SIZE(msm_clocks); i++) {
		struct msm_clock *clock = &msm_clocks[i];
		struct clock_event_device *ce = &clock->clockevent;
		struct clocksource *cs = &clock->clocksource;

		clock->local_counter = clock->regbase + TIMER_COUNT_VAL;
		clock->global_counter = clock->local_counter + global_offset;

		writel(0, clock->regbase + TIMER_ENABLE);
		writel(0, clock->regbase + TIMER_CLEAR);
		writel(~0, clock->regbase + TIMER_MATCH_VAL);

		ce->mult = div_sc(clock->freq, NSEC_PER_SEC, ce->shift);
		/* allow at least 10 seconds to notice that the timer wrapped */
		ce->max_delta_ns =
			clockevent_delta2ns(0xf0000000 >> clock->shift, ce);
		/* 4 gets rounded down to 3 */
		ce->min_delta_ns = clockevent_delta2ns(4, ce);
		ce->cpumask = cpumask_of(0);

		res = clocksource_register_hz(cs, clock->freq);
		if (res)
			printk(KERN_ERR "msm_timer_init: clocksource_register "
			       "failed for %s\n", cs->name);

		res = setup_irq(clock->irq.irq, &clock->irq);
		if (res)
			printk(KERN_ERR "msm_timer_init: setup_irq "
			       "failed for %s\n", cs->name);

		clockevents_register_device(ce);
	}
}

#ifdef CONFIG_SMP
int __cpuinit local_timer_setup(struct clock_event_device *evt)
{
	struct msm_clock *clock = &msm_clocks[MSM_GLOBAL_TIMER];

	/* Use existing clock_event for cpu 0 */
	if (!smp_processor_id())
		return 0;

	writel(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL);

	if (!local_clock_event) {
		writel(0, clock->regbase  + TIMER_ENABLE);
		writel(0, clock->regbase + TIMER_CLEAR);
		writel(~0, clock->regbase + TIMER_MATCH_VAL);
	}
	evt->irq = clock->irq.irq;
	evt->name = "local_timer";
	evt->features = CLOCK_EVT_FEAT_ONESHOT;
	evt->rating = clock->clockevent.rating;
	evt->set_mode = msm_timer_set_mode;
	evt->set_next_event = msm_timer_set_next_event;
	evt->shift = clock->clockevent.shift;
	evt->mult = div_sc(clock->freq, NSEC_PER_SEC, evt->shift);
	evt->max_delta_ns =
		clockevent_delta2ns(0xf0000000 >> clock->shift, evt);
	evt->min_delta_ns = clockevent_delta2ns(4, evt);

	local_clock_event = evt;

	gic_enable_ppi(clock->irq.irq);

	clockevents_register_device(evt);
	return 0;
}

inline int local_timer_ack(void)
{
	return 1;
}

#endif

struct sys_timer msm_timer = {
	.init = msm_timer_init
};
Commit	Line	Data
3e4ea372 AH	1	/* linux/arch/arm/mach-msm/timer.c
	2	*
	3	* Copyright (C) 2007 Google, Inc.
	4	*
	5	* This software is licensed under the terms of the GNU General Public
	6	* License version 2, as published by the Free Software Foundation, and
	7	* may be copied, distributed, and modified under those terms.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	*/
	15
	16	#include <linux/init.h>
	17	#include <linux/time.h>
	18	#include <linux/interrupt.h>
	19	#include <linux/irq.h>
	20	#include <linux/clk.h>
	21	#include <linux/clockchips.h>
	22	#include <linux/delay.h>
fced80c7	23	#include <linux/io.h>
3e4ea372 AH	24
3e4ea372 AH	25	#include <asm/mach/time.h>
ebf30dc9 SB	26	#include <asm/hardware/gic.h>
ebf30dc9 SB	27
a09e64fb	28	#include <mach/msm_iomap.h>
8c27e6f3	29	#include <mach/cpu.h>
3e4ea372 AH	30
	31	#define TIMER_MATCH_VAL 0x0000
	32	#define TIMER_COUNT_VAL 0x0004
	33	#define TIMER_ENABLE 0x0008
	34	#define TIMER_ENABLE_CLR_ON_MATCH_EN 2
	35	#define TIMER_ENABLE_EN 1
	36	#define TIMER_CLEAR 0x000C
672039f0 JO	37	#define DGT_CLK_CTL 0x0034
	38	enum {
	39	DGT_CLK_CTL_DIV_1 = 0,
	40	DGT_CLK_CTL_DIV_2 = 1,
	41	DGT_CLK_CTL_DIV_3 = 2,
	42	DGT_CLK_CTL_DIV_4 = 3,
	43	};
3e4ea372 AH	44	#define CSR_PROTECTION 0x0020
	45	#define CSR_PROTECTION_EN 1
	46
	47	#define GPT_HZ 32768
672039f0	48
94790ec2 JO	49	enum timer_location {
	50	LOCAL_TIMER = 0,
	51	GLOBAL_TIMER = 1,
	52	};
	53
94790ec2 JO	54	#define MSM_GLOBAL_TIMER MSM_CLOCK_DGT
94790ec2 JO	55
8c27e6f3	56	/* TODO: Remove these ifdefs */
672039f0 JO	57	#if defined(CONFIG_ARCH_QSD8X50)
	58	#define DGT_HZ (19200000 / 4) /* 19.2 MHz / 4 by default */
	59	#define MSM_DGT_SHIFT (0)
fdb9c3cd	60	#elif defined(CONFIG_ARCH_MSM7X30)
672039f0 JO	61	#define DGT_HZ (24576000 / 4) /* 24.576 MHz (LPXO) / 4 by default */
672039f0 JO	62	#define MSM_DGT_SHIFT (0)
fdb9c3cd SB	63	#elif defined(CONFIG_ARCH_MSM8X60) \|\| defined(CONFIG_ARCH_MSM8960)
	64	#define DGT_HZ (27000000 / 4) /* 27 MHz (PXO) / 4 by default */
	65	#define MSM_DGT_SHIFT (0)
672039f0	66	#else
3e4ea372	67	#define DGT_HZ 19200000 /* 19.2 MHz or 600 KHz after shift */
672039f0 JO	68	#define MSM_DGT_SHIFT (5)
672039f0 JO	69	#endif
3e4ea372 AH	70
	71	struct msm_clock {
	72	struct clock_event_device clockevent;
	73	struct clocksource clocksource;
	74	struct irqaction irq;
bcc0f6af	75	void __iomem *regbase;
3e4ea372 AH	76	uint32_t freq;
3e4ea372 AH	77	uint32_t shift;
94790ec2 JO	78	void __iomem *global_counter;
	79	void __iomem *local_counter;
	80	};
	81
	82	enum {
	83	MSM_CLOCK_GPT,
	84	MSM_CLOCK_DGT,
	85	NR_TIMERS,
3e4ea372 AH	86	};
3e4ea372 AH	87
94790ec2 JO	88
	89	static struct msm_clock msm_clocks[];
	90	static struct clock_event_device *local_clock_event;
	91
3e4ea372 AH	92	static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
	93	{
	94	struct clock_event_device *evt = dev_id;
94790ec2 JO	95	if (smp_processor_id() != 0)
	96	evt = local_clock_event;
	97	if (evt->event_handler == NULL)
	98	return IRQ_HANDLED;
3e4ea372 AH	99	evt->event_handler(evt);
	100	return IRQ_HANDLED;
	101	}
	102
94790ec2	103	static cycle_t msm_read_timer_count(struct clocksource *cs)
3e4ea372	104	{
94790ec2 JO	105	struct msm_clock *clk = container_of(cs, struct msm_clock, clocksource);
94790ec2 JO	106
650f1567 JO	107	/*
	108	* Shift timer count down by a constant due to unreliable lower bits
	109	* on some targets.
	110	*/
	111	return readl(clk->global_counter) >> clk->shift;
3e4ea372 AH	112	}
3e4ea372 AH	113
94790ec2	114	static struct msm_clock clockevent_to_clock(struct clock_event_device evt)
3e4ea372	115	{
94790ec2 JO	116	#ifdef CONFIG_SMP
	117	int i;
	118	for (i = 0; i < NR_TIMERS; i++)
	119	if (evt == &(msm_clocks[i].clockevent))
	120	return &msm_clocks[i];
	121	return &msm_clocks[MSM_GLOBAL_TIMER];
	122	#else
	123	return container_of(evt, struct msm_clock, clockevent);
	124	#endif
3e4ea372 AH	125	}
	126
	127	static int msm_timer_set_next_event(unsigned long cycles,
	128	struct clock_event_device *evt)
	129	{
94790ec2 JO	130	struct msm_clock *clock = clockevent_to_clock(evt);
94790ec2 JO	131	uint32_t now = readl(clock->local_counter);
3e4ea372	132	uint32_t alarm = now + (cycles << clock->shift);
3e4ea372 AH	133
3e4ea372 AH	134	writel(alarm, clock->regbase + TIMER_MATCH_VAL);
3e4ea372 AH	135	return 0;
	136	}
	137
	138	static void msm_timer_set_mode(enum clock_event_mode mode,
	139	struct clock_event_device *evt)
	140	{
94790ec2 JO	141	struct msm_clock *clock = clockevent_to_clock(evt);
94790ec2 JO	142
3e4ea372 AH	143	switch (mode) {
	144	case CLOCK_EVT_MODE_RESUME:
	145	case CLOCK_EVT_MODE_PERIODIC:
	146	break;
	147	case CLOCK_EVT_MODE_ONESHOT:
	148	writel(TIMER_ENABLE_EN, clock->regbase + TIMER_ENABLE);
	149	break;
	150	case CLOCK_EVT_MODE_UNUSED:
	151	case CLOCK_EVT_MODE_SHUTDOWN:
	152	writel(0, clock->regbase + TIMER_ENABLE);
	153	break;
	154	}
	155	}
	156
	157	static struct msm_clock msm_clocks[] = {
94790ec2	158	[MSM_CLOCK_GPT] = {
3e4ea372 AH	159	.clockevent = {
	160	.name = "gp_timer",
	161	.features = CLOCK_EVT_FEAT_ONESHOT,
	162	.shift = 32,
	163	.rating = 200,
	164	.set_next_event = msm_timer_set_next_event,
	165	.set_mode = msm_timer_set_mode,
	166	},
	167	.clocksource = {
	168	.name = "gp_timer",
	169	.rating = 200,
94790ec2	170	.read = msm_read_timer_count,
3e4ea372	171	.mask = CLOCKSOURCE_MASK(32),
3e4ea372 AH	172	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	173	},
	174	.irq = {
	175	.name = "gp_timer",
	176	.flags = IRQF_DISABLED \| IRQF_TIMER \| IRQF_TRIGGER_RISING,
	177	.handler = msm_timer_interrupt,
	178	.dev_id = &msm_clocks[0].clockevent,
	179	.irq = INT_GP_TIMER_EXP
	180	},
94790ec2	181	.freq = GPT_HZ,
3e4ea372	182	},
94790ec2	183	[MSM_CLOCK_DGT] = {
3e4ea372 AH	184	.clockevent = {
	185	.name = "dg_timer",
	186	.features = CLOCK_EVT_FEAT_ONESHOT,
	187	.shift = 32 + MSM_DGT_SHIFT,
	188	.rating = 300,
	189	.set_next_event = msm_timer_set_next_event,
	190	.set_mode = msm_timer_set_mode,
	191	},
	192	.clocksource = {
	193	.name = "dg_timer",
	194	.rating = 300,
94790ec2	195	.read = msm_read_timer_count,
3e4ea372	196	.mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT)),
3e4ea372 AH	197	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	198	},
	199	.irq = {
	200	.name = "dg_timer",
	201	.flags = IRQF_DISABLED \| IRQF_TIMER \| IRQF_TRIGGER_RISING,
	202	.handler = msm_timer_interrupt,
	203	.dev_id = &msm_clocks[1].clockevent,
	204	.irq = INT_DEBUG_TIMER_EXP
	205	},
3e4ea372	206	.freq = DGT_HZ >> MSM_DGT_SHIFT,
94790ec2	207	.shift = MSM_DGT_SHIFT,
3e4ea372 AH	208	}
	209	};
	210
	211	static void __init msm_timer_init(void)
	212	{
	213	int i;
	214	int res;
8c27e6f3 DB	215	int global_offset = 0;
	216
	217	if (cpu_is_msm7x01()) {
	218	msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE;
	219	msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x10;
	220	} else if (cpu_is_msm7x30()) {
	221	msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE + 0x04;
	222	msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x24;
	223	} else if (cpu_is_qsd8x50()) {
	224	msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE;
	225	msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x10;
a81c8c38	226	} else if (cpu_is_msm8x60() \|\| cpu_is_msm8960()) {
8c27e6f3 DB	227	msm_clocks[MSM_CLOCK_GPT].regbase = MSM_TMR_BASE + 0x04;
	228	msm_clocks[MSM_CLOCK_DGT].regbase = MSM_TMR_BASE + 0x24;
	229
	230	/* Use CPU0's timer as the global timer. */
	231	global_offset = MSM_TMR0_BASE - MSM_TMR_BASE;
	232	} else
	233	BUG();
3e4ea372	234
94790ec2	235	#ifdef CONFIG_ARCH_MSM_SCORPIONMP
672039f0 JO	236	writel(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL);
	237	#endif
	238
3e4ea372 AH	239	for (i = 0; i < ARRAY_SIZE(msm_clocks); i++) {
	240	struct msm_clock *clock = &msm_clocks[i];
	241	struct clock_event_device *ce = &clock->clockevent;
	242	struct clocksource *cs = &clock->clocksource;
8c27e6f3 DB	243
	244	clock->local_counter = clock->regbase + TIMER_COUNT_VAL;
	245	clock->global_counter = clock->local_counter + global_offset;
	246
3e4ea372 AH	247	writel(0, clock->regbase + TIMER_ENABLE);
	248	writel(0, clock->regbase + TIMER_CLEAR);
	249	writel(~0, clock->regbase + TIMER_MATCH_VAL);
	250
	251	ce->mult = div_sc(clock->freq, NSEC_PER_SEC, ce->shift);
	252	/* allow at least 10 seconds to notice that the timer wrapped */
	253	ce->max_delta_ns =
	254	clockevent_delta2ns(0xf0000000 >> clock->shift, ce);
	255	/* 4 gets rounded down to 3 */
	256	ce->min_delta_ns = clockevent_delta2ns(4, ce);
320ab2b0	257	ce->cpumask = cpumask_of(0);
3e4ea372	258
ff9c9772	259	res = clocksource_register_hz(cs, clock->freq);
3e4ea372 AH	260	if (res)
	261	printk(KERN_ERR "msm_timer_init: clocksource_register "
	262	"failed for %s\n", cs->name);
	263
	264	res = setup_irq(clock->irq.irq, &clock->irq);
	265	if (res)
	266	printk(KERN_ERR "msm_timer_init: setup_irq "
	267	"failed for %s\n", cs->name);
	268
	269	clockevents_register_device(ce);
	270	}
	271	}
	272
94790ec2	273	#ifdef CONFIG_SMP
af90f10d	274	int __cpuinit local_timer_setup(struct clock_event_device *evt)
94790ec2 JO	275	{
	276	struct msm_clock *clock = &msm_clocks[MSM_GLOBAL_TIMER];
	277
	278	/* Use existing clock_event for cpu 0 */
	279	if (!smp_processor_id())
893b66c3	280	return 0;
94790ec2 JO	281
	282	writel(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL);
	283
	284	if (!local_clock_event) {
	285	writel(0, clock->regbase + TIMER_ENABLE);
	286	writel(0, clock->regbase + TIMER_CLEAR);
	287	writel(~0, clock->regbase + TIMER_MATCH_VAL);
	288	}
	289	evt->irq = clock->irq.irq;
	290	evt->name = "local_timer";
	291	evt->features = CLOCK_EVT_FEAT_ONESHOT;
	292	evt->rating = clock->clockevent.rating;
	293	evt->set_mode = msm_timer_set_mode;
	294	evt->set_next_event = msm_timer_set_next_event;
	295	evt->shift = clock->clockevent.shift;
	296	evt->mult = div_sc(clock->freq, NSEC_PER_SEC, evt->shift);
	297	evt->max_delta_ns =
	298	clockevent_delta2ns(0xf0000000 >> clock->shift, evt);
	299	evt->min_delta_ns = clockevent_delta2ns(4, evt);
	300
	301	local_clock_event = evt;
	302
	303	gic_enable_ppi(clock->irq.irq);
	304
	305	clockevents_register_device(evt);
af90f10d	306	return 0;
94790ec2 JO	307	}
	308
	309	inline int local_timer_ack(void)
	310	{
	311	return 1;
	312	}
	313
	314	#endif
	315
3e4ea372 AH	316	struct sys_timer msm_timer = {
	317	.init = msm_timer_init
	318	};