[mirror_ubuntu-bionic-kernel.git] / arch / arm / mach-msm / timer.c

/* linux/arch/arm/mach-msm/timer.c
 *
 * Copyright (C) 2007 Google, Inc.
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#include <linux/init.h>
#include <linux/time.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/clk.h>
#include <linux/clockchips.h>
#include <linux/delay.h>
#include <linux/io.h>

#include <asm/mach/time.h>
#include <asm/hardware/gic.h>

#include <mach/msm_iomap.h>
#include <mach/cpu.h>

#define TIMER_MATCH_VAL         0x0000
#define TIMER_COUNT_VAL         0x0004
#define TIMER_ENABLE            0x0008
#define TIMER_ENABLE_CLR_ON_MATCH_EN    2
#define TIMER_ENABLE_EN                 1
#define TIMER_CLEAR             0x000C
#define DGT_CLK_CTL             0x0034
enum {
	DGT_CLK_CTL_DIV_1 = 0,
	DGT_CLK_CTL_DIV_2 = 1,
	DGT_CLK_CTL_DIV_3 = 2,
	DGT_CLK_CTL_DIV_4 = 3,
};
#define CSR_PROTECTION          0x0020
#define CSR_PROTECTION_EN               1

#define GPT_HZ 32768

enum timer_location {
	LOCAL_TIMER = 0,
	GLOBAL_TIMER = 1,
};

#define MSM_GLOBAL_TIMER MSM_CLOCK_DGT

/* TODO: Remove these ifdefs */
#if defined(CONFIG_ARCH_QSD8X50)
#define DGT_HZ (19200000 / 4) /* 19.2 MHz / 4 by default */
#define MSM_DGT_SHIFT (0)
#elif defined(CONFIG_ARCH_MSM7X30)
#define DGT_HZ (24576000 / 4) /* 24.576 MHz (LPXO) / 4 by default */
#define MSM_DGT_SHIFT (0)
#elif defined(CONFIG_ARCH_MSM8X60) || defined(CONFIG_ARCH_MSM8960)
#define DGT_HZ (27000000 / 4) /* 27 MHz (PXO) / 4 by default */
#define MSM_DGT_SHIFT (0)
#else
#define DGT_HZ 19200000 /* 19.2 MHz or 600 KHz after shift */
#define MSM_DGT_SHIFT (5)
#endif

struct msm_clock {
	struct clock_event_device   clockevent;
	struct clocksource          clocksource;
	unsigned int		    irq;
	void __iomem                *regbase;
	uint32_t                    freq;
	uint32_t                    shift;
	void __iomem                *global_counter;
	void __iomem                *local_counter;
	union {
		struct clock_event_device		*evt;
		struct clock_event_device __percpu	**percpu_evt;
	};		
};

enum {
	MSM_CLOCK_GPT,
	MSM_CLOCK_DGT,
	NR_TIMERS,
};


static struct msm_clock msm_clocks[];

static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evt = *(struct clock_event_device **)dev_id;
	if (evt->event_handler == NULL)
		return IRQ_HANDLED;
	evt->event_handler(evt);
	return IRQ_HANDLED;
}

static cycle_t msm_read_timer_count(struct clocksource *cs)
{
	struct msm_clock *clk = container_of(cs, struct msm_clock, clocksource);

	/*
	 * Shift timer count down by a constant due to unreliable lower bits
	 * on some targets.
	 */
	return readl(clk->global_counter) >> clk->shift;
}

static struct msm_clock *clockevent_to_clock(struct clock_event_device *evt)
{
#ifdef CONFIG_SMP
	int i;
	for (i = 0; i < NR_TIMERS; i++)
		if (evt == &(msm_clocks[i].clockevent))
			return &msm_clocks[i];
	return &msm_clocks[MSM_GLOBAL_TIMER];
#else
	return container_of(evt, struct msm_clock, clockevent);
#endif
}

static int msm_timer_set_next_event(unsigned long cycles,
				    struct clock_event_device *evt)
{
	struct msm_clock *clock = clockevent_to_clock(evt);
	uint32_t now = readl(clock->local_counter);
	uint32_t alarm = now + (cycles << clock->shift);

	writel(alarm, clock->regbase + TIMER_MATCH_VAL);
	return 0;
}

static void msm_timer_set_mode(enum clock_event_mode mode,
			      struct clock_event_device *evt)
{
	struct msm_clock *clock = clockevent_to_clock(evt);

	switch (mode) {
	case CLOCK_EVT_MODE_RESUME:
	case CLOCK_EVT_MODE_PERIODIC:
		break;
	case CLOCK_EVT_MODE_ONESHOT:
		writel(TIMER_ENABLE_EN, clock->regbase + TIMER_ENABLE);
		break;
	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
		writel(0, clock->regbase + TIMER_ENABLE);
		break;
	}
}

static struct msm_clock msm_clocks[] = {
	[MSM_CLOCK_GPT] = {
		.clockevent = {
			.name           = "gp_timer",
			.features       = CLOCK_EVT_FEAT_ONESHOT,
			.shift          = 32,
			.rating         = 200,
			.set_next_event = msm_timer_set_next_event,
			.set_mode       = msm_timer_set_mode,
		},
		.clocksource = {
			.name           = "gp_timer",
			.rating         = 200,
			.read           = msm_read_timer_count,
			.mask           = CLOCKSOURCE_MASK(32),
			.flags          = CLOCK_SOURCE_IS_CONTINUOUS,
		},
		.irq = INT_GP_TIMER_EXP,
		.freq = GPT_HZ,
	},
	[MSM_CLOCK_DGT] = {
		.clockevent = {
			.name           = "dg_timer",
			.features       = CLOCK_EVT_FEAT_ONESHOT,
			.shift          = 32 + MSM_DGT_SHIFT,
			.rating         = 300,
			.set_next_event = msm_timer_set_next_event,
			.set_mode       = msm_timer_set_mode,
		},
		.clocksource = {
			.name           = "dg_timer",
			.rating         = 300,
			.read           = msm_read_timer_count,
			.mask           = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT)),
			.flags          = CLOCK_SOURCE_IS_CONTINUOUS,
		},
		.irq = INT_DEBUG_TIMER_EXP,
		.freq = DGT_HZ >> MSM_DGT_SHIFT,
		.shift = MSM_DGT_SHIFT,
	}
};

static void __init msm_timer_init(void)
{
	int i;
	int res;
	int global_offset = 0;

	if (cpu_is_msm7x01()) {
		msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE;
		msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x10;
	} else if (cpu_is_msm7x30()) {
		msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE + 0x04;
		msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x24;
	} else if (cpu_is_qsd8x50()) {
		msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE;
		msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x10;
	} else if (cpu_is_msm8x60() || cpu_is_msm8960()) {
		msm_clocks[MSM_CLOCK_GPT].regbase = MSM_TMR_BASE + 0x04;
		msm_clocks[MSM_CLOCK_DGT].regbase = MSM_TMR_BASE + 0x24;

		/* Use CPU0's timer as the global timer. */
		global_offset = MSM_TMR0_BASE - MSM_TMR_BASE;
	} else
		BUG();

#ifdef CONFIG_ARCH_MSM_SCORPIONMP
	writel(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL);
#endif

	for (i = 0; i < ARRAY_SIZE(msm_clocks); i++) {
		struct msm_clock *clock = &msm_clocks[i];
		struct clock_event_device *ce = &clock->clockevent;
		struct clocksource *cs = &clock->clocksource;

		clock->local_counter = clock->regbase + TIMER_COUNT_VAL;
		clock->global_counter = clock->local_counter + global_offset;

		writel(0, clock->regbase + TIMER_ENABLE);
		writel(0, clock->regbase + TIMER_CLEAR);
		writel(~0, clock->regbase + TIMER_MATCH_VAL);

		ce->mult = div_sc(clock->freq, NSEC_PER_SEC, ce->shift);
		/* allow at least 10 seconds to notice that the timer wrapped */
		ce->max_delta_ns =
			clockevent_delta2ns(0xf0000000 >> clock->shift, ce);
		/* 4 gets rounded down to 3 */
		ce->min_delta_ns = clockevent_delta2ns(4, ce);
		ce->cpumask = cpumask_of(0);

		res = clocksource_register_hz(cs, clock->freq);
		if (res)
			printk(KERN_ERR "msm_timer_init: clocksource_register "
			       "failed for %s\n", cs->name);

		ce->irq = clock->irq;
		if (cpu_is_msm8x60() || cpu_is_msm8960()) {
			clock->percpu_evt = alloc_percpu(struct clock_event_device *);
			if (!clock->percpu_evt) {
				pr_err("msm_timer_init: memory allocation "
				       "failed for %s\n", ce->name);
				continue;
			}

			*__this_cpu_ptr(clock->percpu_evt) = ce;
			res = request_percpu_irq(ce->irq, msm_timer_interrupt,
						 ce->name, clock->percpu_evt);
			if (!res)
				enable_percpu_irq(ce->irq, 0);
		} else {
			clock->evt = ce;
			res = request_irq(ce->irq, msm_timer_interrupt,
					  IRQF_TIMER | IRQF_NOBALANCING | IRQF_TRIGGER_RISING,
					  ce->name, &clock->evt);
		}

		if (res)
			pr_err("msm_timer_init: request_irq failed for %s\n",
			       ce->name);

		clockevents_register_device(ce);
	}
}

#ifdef CONFIG_LOCAL_TIMERS
int __cpuinit local_timer_setup(struct clock_event_device *evt)
{
	static bool local_timer_inited;
	struct msm_clock *clock = &msm_clocks[MSM_GLOBAL_TIMER];

	/* Use existing clock_event for cpu 0 */
	if (!smp_processor_id())
		return 0;

	writel(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL);

	if (!local_timer_inited) {
		writel(0, clock->regbase  + TIMER_ENABLE);
		writel(0, clock->regbase + TIMER_CLEAR);
		writel(~0, clock->regbase + TIMER_MATCH_VAL);
		local_timer_inited = true;
	}
	evt->irq = clock->irq;
	evt->name = "local_timer";
	evt->features = CLOCK_EVT_FEAT_ONESHOT;
	evt->rating = clock->clockevent.rating;
	evt->set_mode = msm_timer_set_mode;
	evt->set_next_event = msm_timer_set_next_event;
	evt->shift = clock->clockevent.shift;
	evt->mult = div_sc(clock->freq, NSEC_PER_SEC, evt->shift);
	evt->max_delta_ns =
		clockevent_delta2ns(0xf0000000 >> clock->shift, evt);
	evt->min_delta_ns = clockevent_delta2ns(4, evt);

	*__this_cpu_ptr(clock->percpu_evt) = evt;
	enable_percpu_irq(evt->irq, 0);

	clockevents_register_device(evt);
	return 0;
}

void local_timer_stop(struct clock_event_device *evt)
{
	evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
	disable_percpu_irq(evt->irq);
}
#endif /* CONFIG_LOCAL_TIMERS */

struct sys_timer msm_timer = {
	.init = msm_timer_init
};
Commit	Line	Data
3e4ea372 AH	1	/* linux/arch/arm/mach-msm/timer.c
	2	*
	3	* Copyright (C) 2007 Google, Inc.
	4	*
	5	* This software is licensed under the terms of the GNU General Public
	6	* License version 2, as published by the Free Software Foundation, and
	7	* may be copied, distributed, and modified under those terms.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	*/
	15
	16	#include <linux/init.h>
	17	#include <linux/time.h>
	18	#include <linux/interrupt.h>
	19	#include <linux/irq.h>
	20	#include <linux/clk.h>
	21	#include <linux/clockchips.h>
	22	#include <linux/delay.h>
fced80c7	23	#include <linux/io.h>
3e4ea372 AH	24
3e4ea372 AH	25	#include <asm/mach/time.h>
ebf30dc9 SB	26	#include <asm/hardware/gic.h>
ebf30dc9 SB	27
a09e64fb	28	#include <mach/msm_iomap.h>
8c27e6f3	29	#include <mach/cpu.h>
3e4ea372 AH	30
	31	#define TIMER_MATCH_VAL 0x0000
	32	#define TIMER_COUNT_VAL 0x0004
	33	#define TIMER_ENABLE 0x0008
	34	#define TIMER_ENABLE_CLR_ON_MATCH_EN 2
	35	#define TIMER_ENABLE_EN 1
	36	#define TIMER_CLEAR 0x000C
672039f0 JO	37	#define DGT_CLK_CTL 0x0034
	38	enum {
	39	DGT_CLK_CTL_DIV_1 = 0,
	40	DGT_CLK_CTL_DIV_2 = 1,
	41	DGT_CLK_CTL_DIV_3 = 2,
	42	DGT_CLK_CTL_DIV_4 = 3,
	43	};
3e4ea372 AH	44	#define CSR_PROTECTION 0x0020
	45	#define CSR_PROTECTION_EN 1
	46
	47	#define GPT_HZ 32768
672039f0	48
94790ec2 JO	49	enum timer_location {
	50	LOCAL_TIMER = 0,
	51	GLOBAL_TIMER = 1,
	52	};
	53
94790ec2 JO	54	#define MSM_GLOBAL_TIMER MSM_CLOCK_DGT
94790ec2 JO	55
8c27e6f3	56	/* TODO: Remove these ifdefs */
672039f0 JO	57	#if defined(CONFIG_ARCH_QSD8X50)
	58	#define DGT_HZ (19200000 / 4) /* 19.2 MHz / 4 by default */
	59	#define MSM_DGT_SHIFT (0)
fdb9c3cd	60	#elif defined(CONFIG_ARCH_MSM7X30)
672039f0 JO	61	#define DGT_HZ (24576000 / 4) /* 24.576 MHz (LPXO) / 4 by default */
672039f0 JO	62	#define MSM_DGT_SHIFT (0)
fdb9c3cd SB	63	#elif defined(CONFIG_ARCH_MSM8X60) \|\| defined(CONFIG_ARCH_MSM8960)
	64	#define DGT_HZ (27000000 / 4) /* 27 MHz (PXO) / 4 by default */
	65	#define MSM_DGT_SHIFT (0)
672039f0	66	#else
3e4ea372	67	#define DGT_HZ 19200000 /* 19.2 MHz or 600 KHz after shift */
672039f0 JO	68	#define MSM_DGT_SHIFT (5)
672039f0 JO	69	#endif
3e4ea372 AH	70
	71	struct msm_clock {
	72	struct clock_event_device clockevent;
	73	struct clocksource clocksource;
28af690a	74	unsigned int irq;
bcc0f6af	75	void __iomem *regbase;
3e4ea372 AH	76	uint32_t freq;
3e4ea372 AH	77	uint32_t shift;
94790ec2 JO	78	void __iomem *global_counter;
94790ec2 JO	79	void __iomem *local_counter;
28af690a MZ	80	union {
	81	struct clock_event_device *evt;
	82	struct clock_event_device __percpu **percpu_evt;
	83	};
94790ec2 JO	84	};
	85
	86	enum {
	87	MSM_CLOCK_GPT,
	88	MSM_CLOCK_DGT,
	89	NR_TIMERS,
3e4ea372 AH	90	};
3e4ea372 AH	91
94790ec2 JO	92
94790ec2 JO	93	static struct msm_clock msm_clocks[];
94790ec2	94
3e4ea372 AH	95	static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
3e4ea372 AH	96	{
28af690a	97	struct clock_event_device evt = (struct clock_event_device **)dev_id;
94790ec2 JO	98	if (evt->event_handler == NULL)
94790ec2 JO	99	return IRQ_HANDLED;
3e4ea372 AH	100	evt->event_handler(evt);
	101	return IRQ_HANDLED;
	102	}
	103
94790ec2	104	static cycle_t msm_read_timer_count(struct clocksource *cs)
3e4ea372	105	{
94790ec2 JO	106	struct msm_clock *clk = container_of(cs, struct msm_clock, clocksource);
94790ec2 JO	107
650f1567 JO	108	/*
	109	* Shift timer count down by a constant due to unreliable lower bits
	110	* on some targets.
	111	*/
	112	return readl(clk->global_counter) >> clk->shift;
3e4ea372 AH	113	}
3e4ea372 AH	114
94790ec2	115	static struct msm_clock clockevent_to_clock(struct clock_event_device evt)
3e4ea372	116	{
94790ec2 JO	117	#ifdef CONFIG_SMP
	118	int i;
	119	for (i = 0; i < NR_TIMERS; i++)
	120	if (evt == &(msm_clocks[i].clockevent))
	121	return &msm_clocks[i];
	122	return &msm_clocks[MSM_GLOBAL_TIMER];
	123	#else
	124	return container_of(evt, struct msm_clock, clockevent);
	125	#endif
3e4ea372 AH	126	}
	127
	128	static int msm_timer_set_next_event(unsigned long cycles,
	129	struct clock_event_device *evt)
	130	{
94790ec2 JO	131	struct msm_clock *clock = clockevent_to_clock(evt);
94790ec2 JO	132	uint32_t now = readl(clock->local_counter);
3e4ea372	133	uint32_t alarm = now + (cycles << clock->shift);
3e4ea372 AH	134
3e4ea372 AH	135	writel(alarm, clock->regbase + TIMER_MATCH_VAL);
3e4ea372 AH	136	return 0;
	137	}
	138
	139	static void msm_timer_set_mode(enum clock_event_mode mode,
	140	struct clock_event_device *evt)
	141	{
94790ec2 JO	142	struct msm_clock *clock = clockevent_to_clock(evt);
94790ec2 JO	143
3e4ea372 AH	144	switch (mode) {
	145	case CLOCK_EVT_MODE_RESUME:
	146	case CLOCK_EVT_MODE_PERIODIC:
	147	break;
	148	case CLOCK_EVT_MODE_ONESHOT:
	149	writel(TIMER_ENABLE_EN, clock->regbase + TIMER_ENABLE);
	150	break;
	151	case CLOCK_EVT_MODE_UNUSED:
	152	case CLOCK_EVT_MODE_SHUTDOWN:
	153	writel(0, clock->regbase + TIMER_ENABLE);
	154	break;
	155	}
	156	}
	157
	158	static struct msm_clock msm_clocks[] = {
94790ec2	159	[MSM_CLOCK_GPT] = {
3e4ea372 AH	160	.clockevent = {
	161	.name = "gp_timer",
	162	.features = CLOCK_EVT_FEAT_ONESHOT,
	163	.shift = 32,
	164	.rating = 200,
	165	.set_next_event = msm_timer_set_next_event,
	166	.set_mode = msm_timer_set_mode,
	167	},
	168	.clocksource = {
	169	.name = "gp_timer",
	170	.rating = 200,
94790ec2	171	.read = msm_read_timer_count,
3e4ea372	172	.mask = CLOCKSOURCE_MASK(32),
3e4ea372 AH	173	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
3e4ea372 AH	174	},
28af690a	175	.irq = INT_GP_TIMER_EXP,
94790ec2	176	.freq = GPT_HZ,
3e4ea372	177	},
94790ec2	178	[MSM_CLOCK_DGT] = {
3e4ea372 AH	179	.clockevent = {
	180	.name = "dg_timer",
	181	.features = CLOCK_EVT_FEAT_ONESHOT,
	182	.shift = 32 + MSM_DGT_SHIFT,
	183	.rating = 300,
	184	.set_next_event = msm_timer_set_next_event,
	185	.set_mode = msm_timer_set_mode,
	186	},
	187	.clocksource = {
	188	.name = "dg_timer",
	189	.rating = 300,
94790ec2	190	.read = msm_read_timer_count,
3e4ea372	191	.mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT)),
3e4ea372 AH	192	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
3e4ea372 AH	193	},
28af690a	194	.irq = INT_DEBUG_TIMER_EXP,
3e4ea372	195	.freq = DGT_HZ >> MSM_DGT_SHIFT,
94790ec2	196	.shift = MSM_DGT_SHIFT,
3e4ea372 AH	197	}
	198	};
	199
	200	static void __init msm_timer_init(void)
	201	{
	202	int i;
	203	int res;
8c27e6f3 DB	204	int global_offset = 0;
	205
	206	if (cpu_is_msm7x01()) {
	207	msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE;
	208	msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x10;
	209	} else if (cpu_is_msm7x30()) {
	210	msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE + 0x04;
	211	msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x24;
	212	} else if (cpu_is_qsd8x50()) {
	213	msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE;
	214	msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x10;
a81c8c38	215	} else if (cpu_is_msm8x60() \|\| cpu_is_msm8960()) {
8c27e6f3 DB	216	msm_clocks[MSM_CLOCK_GPT].regbase = MSM_TMR_BASE + 0x04;
	217	msm_clocks[MSM_CLOCK_DGT].regbase = MSM_TMR_BASE + 0x24;
	218
	219	/* Use CPU0's timer as the global timer. */
	220	global_offset = MSM_TMR0_BASE - MSM_TMR_BASE;
	221	} else
	222	BUG();
3e4ea372	223
94790ec2	224	#ifdef CONFIG_ARCH_MSM_SCORPIONMP
672039f0 JO	225	writel(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL);
	226	#endif
	227
3e4ea372 AH	228	for (i = 0; i < ARRAY_SIZE(msm_clocks); i++) {
	229	struct msm_clock *clock = &msm_clocks[i];
	230	struct clock_event_device *ce = &clock->clockevent;
	231	struct clocksource *cs = &clock->clocksource;
8c27e6f3 DB	232
	233	clock->local_counter = clock->regbase + TIMER_COUNT_VAL;
	234	clock->global_counter = clock->local_counter + global_offset;
	235
3e4ea372 AH	236	writel(0, clock->regbase + TIMER_ENABLE);
	237	writel(0, clock->regbase + TIMER_CLEAR);
	238	writel(~0, clock->regbase + TIMER_MATCH_VAL);
	239
	240	ce->mult = div_sc(clock->freq, NSEC_PER_SEC, ce->shift);
	241	/* allow at least 10 seconds to notice that the timer wrapped */
	242	ce->max_delta_ns =
	243	clockevent_delta2ns(0xf0000000 >> clock->shift, ce);
	244	/* 4 gets rounded down to 3 */
	245	ce->min_delta_ns = clockevent_delta2ns(4, ce);
320ab2b0	246	ce->cpumask = cpumask_of(0);
3e4ea372	247
ff9c9772	248	res = clocksource_register_hz(cs, clock->freq);
3e4ea372 AH	249	if (res)
	250	printk(KERN_ERR "msm_timer_init: clocksource_register "
	251	"failed for %s\n", cs->name);
	252
28af690a MZ	253	ce->irq = clock->irq;
	254	if (cpu_is_msm8x60() \|\| cpu_is_msm8960()) {
	255	clock->percpu_evt = alloc_percpu(struct clock_event_device *);
	256	if (!clock->percpu_evt) {
	257	pr_err("msm_timer_init: memory allocation "
	258	"failed for %s\n", ce->name);
	259	continue;
	260	}
	261
	262	*__this_cpu_ptr(clock->percpu_evt) = ce;
	263	res = request_percpu_irq(ce->irq, msm_timer_interrupt,
	264	ce->name, clock->percpu_evt);
	265	if (!res)
	266	enable_percpu_irq(ce->irq, 0);
	267	} else {
	268	clock->evt = ce;
	269	res = request_irq(ce->irq, msm_timer_interrupt,
	270	IRQF_TIMER \| IRQF_NOBALANCING \| IRQF_TRIGGER_RISING,
	271	ce->name, &clock->evt);
	272	}
	273
3e4ea372	274	if (res)
28af690a MZ	275	pr_err("msm_timer_init: request_irq failed for %s\n",
28af690a MZ	276	ce->name);
3e4ea372 AH	277
	278	clockevents_register_device(ce);
	279	}
	280	}
	281
2852ccae	282	#ifdef CONFIG_LOCAL_TIMERS
af90f10d	283	int __cpuinit local_timer_setup(struct clock_event_device *evt)
94790ec2	284	{
28af690a	285	static bool local_timer_inited;
94790ec2 JO	286	struct msm_clock *clock = &msm_clocks[MSM_GLOBAL_TIMER];
	287
	288	/* Use existing clock_event for cpu 0 */
	289	if (!smp_processor_id())
893b66c3	290	return 0;
94790ec2 JO	291
	292	writel(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL);
	293
28af690a	294	if (!local_timer_inited) {
94790ec2 JO	295	writel(0, clock->regbase + TIMER_ENABLE);
	296	writel(0, clock->regbase + TIMER_CLEAR);
	297	writel(~0, clock->regbase + TIMER_MATCH_VAL);
28af690a	298	local_timer_inited = true;
94790ec2	299	}
28af690a	300	evt->irq = clock->irq;
94790ec2 JO	301	evt->name = "local_timer";
	302	evt->features = CLOCK_EVT_FEAT_ONESHOT;
	303	evt->rating = clock->clockevent.rating;
	304	evt->set_mode = msm_timer_set_mode;
	305	evt->set_next_event = msm_timer_set_next_event;
	306	evt->shift = clock->clockevent.shift;
	307	evt->mult = div_sc(clock->freq, NSEC_PER_SEC, evt->shift);
	308	evt->max_delta_ns =
	309	clockevent_delta2ns(0xf0000000 >> clock->shift, evt);
	310	evt->min_delta_ns = clockevent_delta2ns(4, evt);
	311
28af690a MZ	312	*__this_cpu_ptr(clock->percpu_evt) = evt;
28af690a MZ	313	enable_percpu_irq(evt->irq, 0);
94790ec2 JO	314
94790ec2 JO	315	clockevents_register_device(evt);
af90f10d	316	return 0;
94790ec2 JO	317	}
94790ec2 JO	318
28af690a	319	void local_timer_stop(struct clock_event_device *evt)
94790ec2	320	{
28af690a MZ	321	evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
28af690a MZ	322	disable_percpu_irq(evt->irq);
94790ec2	323	}
2852ccae	324	#endif /* CONFIG_LOCAL_TIMERS */
94790ec2	325
3e4ea372 AH	326	struct sys_timer msm_timer = {
	327	.init = msm_timer_init
	328	};