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Commit | Line | Data |
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9ae6f740 TP |
1 | /* |
2 | * Device Tree support for Armada 370 and XP platforms. | |
3 | * | |
4 | * Copyright (C) 2012 Marvell | |
5 | * | |
6 | * Lior Amsalem <alior@marvell.com> | |
7 | * Gregory CLEMENT <gregory.clement@free-electrons.com> | |
8 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | |
9 | * | |
10 | * This file is licensed under the terms of the GNU General Public | |
11 | * License version 2. This program is licensed "as is" without any | |
12 | * warranty of any kind, whether express or implied. | |
13 | */ | |
14 | ||
15 | #include <linux/kernel.h> | |
16 | #include <linux/init.h> | |
9cbbc515 | 17 | #include <linux/clk-provider.h> |
d834d26a | 18 | #include <linux/of_address.h> |
9ae6f740 TP |
19 | #include <linux/of_platform.h> |
20 | #include <linux/io.h> | |
573145f0 | 21 | #include <linux/clocksource.h> |
53d2f889 | 22 | #include <linux/dma-mapping.h> |
87e1bed4 | 23 | #include <linux/mbus.h> |
9e128041 | 24 | #include <linux/signal.h> |
85e618a1 | 25 | #include <linux/slab.h> |
e33369cb | 26 | #include <asm/hardware/cache-l2x0.h> |
9ae6f740 TP |
27 | #include <asm/mach/arch.h> |
28 | #include <asm/mach/map.h> | |
29 | #include <asm/mach/time.h> | |
8e6ac203 | 30 | #include <asm/smp_scu.h> |
6eb5be34 | 31 | #include "armada-370-xp.h" |
9ae6f740 | 32 | #include "common.h" |
45f5984a | 33 | #include "coherency.h" |
85e618a1 | 34 | #include "mvebu-soc-id.h" |
9ae6f740 | 35 | |
8e6ac203 TP |
36 | /* |
37 | * Enables the SCU when available. Obviously, this is only useful on | |
38 | * Cortex-A based SOCs, not on PJ4B based ones. | |
39 | */ | |
40 | static void __init mvebu_scu_enable(void) | |
41 | { | |
42 | void __iomem *scu_base; | |
43 | ||
44 | struct device_node *np = | |
45 | of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu"); | |
46 | if (np) { | |
47 | scu_base = of_iomap(np, 0); | |
48 | scu_enable(scu_base); | |
49 | of_node_put(np); | |
50 | } | |
51 | } | |
52 | ||
ca4a6f87 TP |
53 | /* |
54 | * Early versions of Armada 375 SoC have a bug where the BootROM | |
55 | * leaves an external data abort pending. The kernel is hit by this | |
56 | * data abort as soon as it enters userspace, because it unmasks the | |
57 | * data aborts at this moment. We register a custom abort handler | |
58 | * below to ignore the first data abort to work around this | |
59 | * problem. | |
60 | */ | |
61 | static int armada_375_external_abort_wa(unsigned long addr, unsigned int fsr, | |
62 | struct pt_regs *regs) | |
63 | { | |
64 | static int ignore_first; | |
65 | ||
66 | if (!ignore_first && fsr == 0x1406) { | |
67 | ignore_first = 1; | |
68 | return 0; | |
69 | } | |
70 | ||
71 | return 1; | |
72 | } | |
73 | ||
99b3d294 | 74 | static void __init mvebu_timer_and_clk_init(void) |
d834d26a | 75 | { |
5ae13ef4 | 76 | of_clk_init(NULL); |
573145f0 | 77 | clocksource_of_init(); |
8e6ac203 | 78 | mvebu_scu_enable(); |
d834d26a | 79 | coherency_init(); |
5686a1e5 | 80 | BUG_ON(mvebu_mbus_dt_init(coherency_available())); |
752ef800 TP |
81 | } |
82 | ||
83 | static void __init external_abort_quirk(void) | |
84 | { | |
85 | u32 dev, rev; | |
ca4a6f87 | 86 | |
752ef800 TP |
87 | if (mvebu_get_soc_id(&dev, &rev) == 0 && rev > ARMADA_375_Z1_REV) |
88 | return; | |
89 | ||
90 | hook_fault_code(16 + 6, armada_375_external_abort_wa, SIGBUS, 0, | |
91 | "imprecise external abort"); | |
53d2f889 GC |
92 | } |
93 | ||
85e618a1 GC |
94 | static void __init i2c_quirk(void) |
95 | { | |
96 | struct device_node *np; | |
97 | u32 dev, rev; | |
98 | ||
99 | /* | |
100 | * Only revisons more recent than A0 support the offload | |
101 | * mechanism. We can exit only if we are sure that we can | |
102 | * get the SoC revision and it is more recent than A0. | |
103 | */ | |
8eee0f81 | 104 | if (mvebu_get_soc_id(&dev, &rev) == 0 && rev > MV78XX0_A0_REV) |
85e618a1 GC |
105 | return; |
106 | ||
107 | for_each_compatible_node(np, NULL, "marvell,mv78230-i2c") { | |
108 | struct property *new_compat; | |
109 | ||
110 | new_compat = kzalloc(sizeof(*new_compat), GFP_KERNEL); | |
111 | ||
112 | new_compat->name = kstrdup("compatible", GFP_KERNEL); | |
113 | new_compat->length = sizeof("marvell,mv78230-a0-i2c"); | |
114 | new_compat->value = kstrdup("marvell,mv78230-a0-i2c", | |
115 | GFP_KERNEL); | |
116 | ||
117 | of_update_property(np, new_compat); | |
118 | } | |
119 | return; | |
120 | } | |
121 | ||
5fd62066 EG |
122 | #define A375_Z1_THERMAL_FIXUP_OFFSET 0xc |
123 | ||
124 | static void __init thermal_quirk(void) | |
125 | { | |
126 | struct device_node *np; | |
127 | u32 dev, rev; | |
128 | ||
c1a01a03 | 129 | if (mvebu_get_soc_id(&dev, &rev) == 0 && rev > ARMADA_375_Z1_REV) |
5fd62066 EG |
130 | return; |
131 | ||
132 | for_each_compatible_node(np, NULL, "marvell,armada375-thermal") { | |
133 | struct property *prop; | |
134 | __be32 newval, *newprop, *oldprop; | |
135 | int len; | |
136 | ||
137 | /* | |
138 | * The register offset is at a wrong location. This quirk | |
139 | * creates a new reg property as a clone of the previous | |
140 | * one and corrects the offset. | |
141 | */ | |
142 | oldprop = (__be32 *)of_get_property(np, "reg", &len); | |
143 | if (!oldprop) | |
144 | continue; | |
145 | ||
146 | /* Create a duplicate of the 'reg' property */ | |
147 | prop = kzalloc(sizeof(*prop), GFP_KERNEL); | |
148 | prop->length = len; | |
149 | prop->name = kstrdup("reg", GFP_KERNEL); | |
150 | prop->value = kzalloc(len, GFP_KERNEL); | |
151 | memcpy(prop->value, oldprop, len); | |
152 | ||
153 | /* Fixup the register offset of the second entry */ | |
154 | oldprop += 2; | |
155 | newprop = (__be32 *)prop->value + 2; | |
156 | newval = cpu_to_be32(be32_to_cpu(*oldprop) - | |
157 | A375_Z1_THERMAL_FIXUP_OFFSET); | |
158 | *newprop = newval; | |
159 | of_update_property(np, prop); | |
160 | ||
161 | /* | |
162 | * The thermal controller needs some quirk too, so let's change | |
163 | * the compatible string to reflect this. | |
164 | */ | |
165 | prop = kzalloc(sizeof(*prop), GFP_KERNEL); | |
166 | prop->name = kstrdup("compatible", GFP_KERNEL); | |
167 | prop->length = sizeof("marvell,armada375-z1-thermal"); | |
168 | prop->value = kstrdup("marvell,armada375-z1-thermal", | |
169 | GFP_KERNEL); | |
170 | of_update_property(np, prop); | |
171 | } | |
172 | return; | |
173 | } | |
174 | ||
99b3d294 | 175 | static void __init mvebu_dt_init(void) |
9ae6f740 | 176 | { |
85e618a1 GC |
177 | if (of_machine_is_compatible("plathome,openblocks-ax3-4")) |
178 | i2c_quirk(); | |
752ef800 TP |
179 | if (of_machine_is_compatible("marvell,a375-db")) { |
180 | external_abort_quirk(); | |
5fd62066 | 181 | thermal_quirk(); |
752ef800 | 182 | } |
5fd62066 | 183 | |
9ae6f740 TP |
184 | of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); |
185 | } | |
186 | ||
61505e11 TP |
187 | static const char * const armada_370_xp_dt_compat[] = { |
188 | "marvell,armada-370-xp", | |
9ae6f740 TP |
189 | NULL, |
190 | }; | |
191 | ||
a017dbb6 | 192 | DT_MACHINE_START(ARMADA_370_XP_DT, "Marvell Armada 370/XP (Device Tree)") |
9847cf04 RK |
193 | .l2c_aux_val = 0, |
194 | .l2c_aux_mask = ~0, | |
45f5984a | 195 | .smp = smp_ops(armada_xp_smp_ops), |
99b3d294 TP |
196 | .init_machine = mvebu_dt_init, |
197 | .init_time = mvebu_timer_and_clk_init, | |
9ae6f740 | 198 | .restart = mvebu_restart, |
61505e11 | 199 | .dt_compat = armada_370_xp_dt_compat, |
9ae6f740 | 200 | MACHINE_END |
d3ce7f25 GC |
201 | |
202 | static const char * const armada_375_dt_compat[] = { | |
203 | "marvell,armada375", | |
204 | NULL, | |
205 | }; | |
206 | ||
207 | DT_MACHINE_START(ARMADA_375_DT, "Marvell Armada 375 (Device Tree)") | |
9847cf04 RK |
208 | .l2c_aux_val = 0, |
209 | .l2c_aux_mask = ~0, | |
d3ce7f25 | 210 | .init_time = mvebu_timer_and_clk_init, |
5fd62066 | 211 | .init_machine = mvebu_dt_init, |
d3ce7f25 GC |
212 | .restart = mvebu_restart, |
213 | .dt_compat = armada_375_dt_compat, | |
214 | MACHINE_END | |
9aa30f1c TP |
215 | |
216 | static const char * const armada_38x_dt_compat[] = { | |
217 | "marvell,armada380", | |
218 | "marvell,armada385", | |
219 | NULL, | |
220 | }; | |
221 | ||
222 | DT_MACHINE_START(ARMADA_38X_DT, "Marvell Armada 380/385 (Device Tree)") | |
9847cf04 RK |
223 | .l2c_aux_val = 0, |
224 | .l2c_aux_mask = ~0, | |
9aa30f1c TP |
225 | .init_time = mvebu_timer_and_clk_init, |
226 | .restart = mvebu_restart, | |
227 | .dt_compat = armada_38x_dt_compat, | |
228 | MACHINE_END |