[mirror_ubuntu-artful-kernel.git] / arch / arm / mach-mvebu / coherency.c

/*
 * Coherency fabric (Aurora) support for Armada 370, 375, 38x and XP
 * platforms.
 *
 * Copyright (C) 2012 Marvell
 *
 * Yehuda Yitschak <yehuday@marvell.com>
 * Gregory Clement <gregory.clement@free-electrons.com>
 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 *
 * The Armada 370, 375, 38x and XP SOCs have a coherency fabric which is
 * responsible for ensuring hardware coherency between all CPUs and between
 * CPUs and I/O masters. This file initializes the coherency fabric and
 * supplies basic routines for configuring and controlling hardware coherency
 */

#define pr_fmt(fmt) "mvebu-coherency: " fmt

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/of_address.h>
#include <linux/io.h>
#include <linux/smp.h>
#include <linux/dma-mapping.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/mbus.h>
#include <linux/pci.h>
#include <asm/smp_plat.h>
#include <asm/cacheflush.h>
#include <asm/mach/map.h>
#include "coherency.h"
#include "mvebu-soc-id.h"

unsigned long coherency_phys_base;
void __iomem *coherency_base;
static void __iomem *coherency_cpu_base;

/* Coherency fabric registers */
#define IO_SYNC_BARRIER_CTL_OFFSET		   0x0

enum {
	COHERENCY_FABRIC_TYPE_NONE,
	COHERENCY_FABRIC_TYPE_ARMADA_370_XP,
	COHERENCY_FABRIC_TYPE_ARMADA_375,
	COHERENCY_FABRIC_TYPE_ARMADA_380,
};

static struct of_device_id of_coherency_table[] = {
	{.compatible = "marvell,coherency-fabric",
	 .data = (void *) COHERENCY_FABRIC_TYPE_ARMADA_370_XP },
	{.compatible = "marvell,armada-375-coherency-fabric",
	 .data = (void *) COHERENCY_FABRIC_TYPE_ARMADA_375 },
	{.compatible = "marvell,armada-380-coherency-fabric",
	 .data = (void *) COHERENCY_FABRIC_TYPE_ARMADA_380 },
	{ /* end of list */ },
};

/* Functions defined in coherency_ll.S */
int ll_enable_coherency(void);
void ll_add_cpu_to_smp_group(void);

int set_cpu_coherent(void)
{
	if (!coherency_base) {
		pr_warn("Can't make current CPU cache coherent.\n");
		pr_warn("Coherency fabric is not initialized\n");
		return 1;
	}

	ll_add_cpu_to_smp_group();
	return ll_enable_coherency();
}

static inline void mvebu_hwcc_sync_io_barrier(void)
{
	writel(0x1, coherency_cpu_base + IO_SYNC_BARRIER_CTL_OFFSET);
	while (readl(coherency_cpu_base + IO_SYNC_BARRIER_CTL_OFFSET) & 0x1);
}

static dma_addr_t mvebu_hwcc_dma_map_page(struct device *dev, struct page *page,
				  unsigned long offset, size_t size,
				  enum dma_data_direction dir,
				  struct dma_attrs *attrs)
{
	if (dir != DMA_TO_DEVICE)
		mvebu_hwcc_sync_io_barrier();
	return pfn_to_dma(dev, page_to_pfn(page)) + offset;
}


static void mvebu_hwcc_dma_unmap_page(struct device *dev, dma_addr_t dma_handle,
			      size_t size, enum dma_data_direction dir,
			      struct dma_attrs *attrs)
{
	if (dir != DMA_TO_DEVICE)
		mvebu_hwcc_sync_io_barrier();
}

static void mvebu_hwcc_dma_sync(struct device *dev, dma_addr_t dma_handle,
			size_t size, enum dma_data_direction dir)
{
	if (dir != DMA_TO_DEVICE)
		mvebu_hwcc_sync_io_barrier();
}

static struct dma_map_ops mvebu_hwcc_dma_ops = {
	.alloc			= arm_dma_alloc,
	.free			= arm_dma_free,
	.mmap			= arm_dma_mmap,
	.map_page		= mvebu_hwcc_dma_map_page,
	.unmap_page		= mvebu_hwcc_dma_unmap_page,
	.get_sgtable		= arm_dma_get_sgtable,
	.map_sg			= arm_dma_map_sg,
	.unmap_sg		= arm_dma_unmap_sg,
	.sync_single_for_cpu	= mvebu_hwcc_dma_sync,
	.sync_single_for_device	= mvebu_hwcc_dma_sync,
	.sync_sg_for_cpu	= arm_dma_sync_sg_for_cpu,
	.sync_sg_for_device	= arm_dma_sync_sg_for_device,
	.set_dma_mask		= arm_dma_set_mask,
};

static int mvebu_hwcc_notifier(struct notifier_block *nb,
			       unsigned long event, void *__dev)
{
	struct device *dev = __dev;

	if (event != BUS_NOTIFY_ADD_DEVICE)
		return NOTIFY_DONE;
	set_dma_ops(dev, &mvebu_hwcc_dma_ops);

	return NOTIFY_OK;
}

static struct notifier_block mvebu_hwcc_nb = {
	.notifier_call = mvebu_hwcc_notifier,
};

static struct notifier_block mvebu_hwcc_pci_nb = {
	.notifier_call = mvebu_hwcc_notifier,
};

static void __init armada_370_coherency_init(struct device_node *np)
{
	struct resource res;

	of_address_to_resource(np, 0, &res);
	coherency_phys_base = res.start;
	/*
	 * Ensure secondary CPUs will see the updated value,
	 * which they read before they join the coherency
	 * fabric, and therefore before they are coherent with
	 * the boot CPU cache.
	 */
	sync_cache_w(&coherency_phys_base);
	coherency_base = of_iomap(np, 0);
	coherency_cpu_base = of_iomap(np, 1);
	set_cpu_coherent();
}

/*
 * This ioremap hook is used on Armada 375/38x to ensure that PCIe
 * memory areas are mapped as MT_UNCACHED instead of MT_DEVICE. This
 * is needed as a workaround for a deadlock issue between the PCIe
 * interface and the cache controller.
 */
static void __iomem *
armada_pcie_wa_ioremap_caller(phys_addr_t phys_addr, size_t size,
			      unsigned int mtype, void *caller)
{
	struct resource pcie_mem;

	mvebu_mbus_get_pcie_mem_aperture(&pcie_mem);

	if (pcie_mem.start <= phys_addr && (phys_addr + size) <= pcie_mem.end)
		mtype = MT_UNCACHED;

	return __arm_ioremap_caller(phys_addr, size, mtype, caller);
}

static void __init armada_375_380_coherency_init(struct device_node *np)
{
	struct device_node *cache_dn;

	coherency_cpu_base = of_iomap(np, 0);
	arch_ioremap_caller = armada_pcie_wa_ioremap_caller;

	/*
	 * Add the PL310 property "arm,io-coherent". This makes sure the
	 * outer sync operation is not used, which allows to
	 * workaround the system erratum that causes deadlocks when
	 * doing PCIe in an SMP situation on Armada 375 and Armada
	 * 38x.
	 */
	for_each_compatible_node(cache_dn, NULL, "arm,pl310-cache") {
		struct property *p;

		p = kzalloc(sizeof(*p), GFP_KERNEL);
		p->name = kstrdup("arm,io-coherent", GFP_KERNEL);
		of_add_property(cache_dn, p);
	}
}

static int coherency_type(void)
{
	struct device_node *np;
	const struct of_device_id *match;
	int type;

	/*
	 * The coherency fabric is needed:
	 * - For coherency between processors on Armada XP, so only
	 *   when SMP is enabled.
	 * - For coherency between the processor and I/O devices, but
	 *   this coherency requires many pre-requisites (write
	 *   allocate cache policy, shareable pages, SMP bit set) that
	 *   are only meant in SMP situations.
	 *
	 * Note that this means that on Armada 370, there is currently
	 * no way to use hardware I/O coherency, because even when
	 * CONFIG_SMP is enabled, is_smp() returns false due to the
	 * Armada 370 being a single-core processor. To lift this
	 * limitation, we would have to find a way to make the cache
	 * policy set to write-allocate (on all Armada SoCs), and to
	 * set the shareable attribute in page tables (on all Armada
	 * SoCs except the Armada 370). Unfortunately, such decisions
	 * are taken very early in the kernel boot process, at a point
	 * where we don't know yet on which SoC we are running.

	 */
	if (!is_smp())
		return COHERENCY_FABRIC_TYPE_NONE;

	np = of_find_matching_node_and_match(NULL, of_coherency_table, &match);
	if (!np)
		return COHERENCY_FABRIC_TYPE_NONE;

	type = (int) match->data;

	of_node_put(np);

	return type;
}

/*
 * As a precaution, we currently completely disable hardware I/O
 * coherency, until enough testing is done with automatic I/O
 * synchronization barriers to validate that it is a proper solution.
 */
int coherency_available(void)
{
	return false;
}

int __init coherency_init(void)
{
	int type = coherency_type();
	struct device_node *np;

	np = of_find_matching_node(NULL, of_coherency_table);

	if (type == COHERENCY_FABRIC_TYPE_ARMADA_370_XP)
		armada_370_coherency_init(np);
	else if (type == COHERENCY_FABRIC_TYPE_ARMADA_375 ||
		 type == COHERENCY_FABRIC_TYPE_ARMADA_380)
		armada_375_380_coherency_init(np);

	of_node_put(np);

	return 0;
}

static int __init coherency_late_init(void)
{
	if (coherency_available())
		bus_register_notifier(&platform_bus_type,
				      &mvebu_hwcc_nb);
	return 0;
}

postcore_initcall(coherency_late_init);

#if IS_ENABLED(CONFIG_PCI)
static int __init coherency_pci_init(void)
{
	if (coherency_available())
		bus_register_notifier(&pci_bus_type,
				       &mvebu_hwcc_pci_nb);
	return 0;
}

arch_initcall(coherency_pci_init);
#endif
Commit	Line	Data
009f1315	1	/*
e12f12ac TP	2	* Coherency fabric (Aurora) support for Armada 370, 375, 38x and XP
e12f12ac TP	3	* platforms.
009f1315 GC	4	*
	5	* Copyright (C) 2012 Marvell
	6	*
	7	* Yehuda Yitschak <yehuday@marvell.com>
	8	* Gregory Clement <gregory.clement@free-electrons.com>
	9	* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
	10	*
	11	* This file is licensed under the terms of the GNU General Public
	12	* License version 2. This program is licensed "as is" without any
	13	* warranty of any kind, whether express or implied.
	14	*
e12f12ac	15	* The Armada 370, 375, 38x and XP SOCs have a coherency fabric which is
009f1315 GC	16	* responsible for ensuring hardware coherency between all CPUs and between
	17	* CPUs and I/O masters. This file initializes the coherency fabric and
	18	* supplies basic routines for configuring and controlling hardware coherency
	19	*/
	20
5ab5afd8 TP	21	#define pr_fmt(fmt) "mvebu-coherency: " fmt
5ab5afd8 TP	22
009f1315 GC	23	#include <linux/kernel.h>
	24	#include <linux/init.h>
	25	#include <linux/of_address.h>
	26	#include <linux/io.h>
	27	#include <linux/smp.h>
e60304f8 GC	28	#include <linux/dma-mapping.h>
e60304f8 GC	29	#include <linux/platform_device.h>
5ab5afd8 TP	30	#include <linux/slab.h>
5ab5afd8 TP	31	#include <linux/mbus.h>
b0063aad	32	#include <linux/pci.h>
009f1315	33	#include <asm/smp_plat.h>
580ff0ee	34	#include <asm/cacheflush.h>
497a9230	35	#include <asm/mach/map.h>
b12634e3	36	#include "coherency.h"
39438567	37	#include "mvebu-soc-id.h"
009f1315	38
8bd26e3a	39	unsigned long coherency_phys_base;
ccd6a131	40	void __iomem *coherency_base;
e60304f8	41	static void __iomem *coherency_cpu_base;
009f1315 GC	42
009f1315 GC	43	/* Coherency fabric registers */
e60304f8 GC	44	#define IO_SYNC_BARRIER_CTL_OFFSET 0x0
e60304f8 GC	45
924d38f4	46	enum {
501f928e	47	COHERENCY_FABRIC_TYPE_NONE,
924d38f4	48	COHERENCY_FABRIC_TYPE_ARMADA_370_XP,
77fa4b9a	49	COHERENCY_FABRIC_TYPE_ARMADA_375,
d0de9323	50	COHERENCY_FABRIC_TYPE_ARMADA_380,
924d38f4 TP	51	};
924d38f4 TP	52
009f1315	53	static struct of_device_id of_coherency_table[] = {
924d38f4 TP	54	{.compatible = "marvell,coherency-fabric",
924d38f4 TP	55	.data = (void *) COHERENCY_FABRIC_TYPE_ARMADA_370_XP },
77fa4b9a TP	56	{.compatible = "marvell,armada-375-coherency-fabric",
77fa4b9a TP	57	.data = (void *) COHERENCY_FABRIC_TYPE_ARMADA_375 },
d0de9323 TP	58	{.compatible = "marvell,armada-380-coherency-fabric",
d0de9323 TP	59	.data = (void *) COHERENCY_FABRIC_TYPE_ARMADA_380 },
009f1315 GC	60	{ /* end of list */ },
	61	};
	62
2e8a5942 GC	63	/* Functions defined in coherency_ll.S */
	64	int ll_enable_coherency(void);
	65	void ll_add_cpu_to_smp_group(void);
009f1315	66
952f4ca7	67	int set_cpu_coherent(void)
009f1315 GC	68	{
009f1315 GC	69	if (!coherency_base) {
b41375f7	70	pr_warn("Can't make current CPU cache coherent.\n");
009f1315 GC	71	pr_warn("Coherency fabric is not initialized\n");
	72	return 1;
	73	}
	74
2e8a5942 GC	75	ll_add_cpu_to_smp_group();
2e8a5942 GC	76	return ll_enable_coherency();
009f1315 GC	77	}
009f1315 GC	78
e60304f8 GC	79	static inline void mvebu_hwcc_sync_io_barrier(void)
	80	{
	81	writel(0x1, coherency_cpu_base + IO_SYNC_BARRIER_CTL_OFFSET);
	82	while (readl(coherency_cpu_base + IO_SYNC_BARRIER_CTL_OFFSET) & 0x1);
	83	}
	84
	85	static dma_addr_t mvebu_hwcc_dma_map_page(struct device dev, struct page page,
	86	unsigned long offset, size_t size,
	87	enum dma_data_direction dir,
	88	struct dma_attrs *attrs)
	89	{
	90	if (dir != DMA_TO_DEVICE)
	91	mvebu_hwcc_sync_io_barrier();
	92	return pfn_to_dma(dev, page_to_pfn(page)) + offset;
	93	}
	94
	95
	96	static void mvebu_hwcc_dma_unmap_page(struct device *dev, dma_addr_t dma_handle,
	97	size_t size, enum dma_data_direction dir,
	98	struct dma_attrs *attrs)
	99	{
	100	if (dir != DMA_TO_DEVICE)
	101	mvebu_hwcc_sync_io_barrier();
	102	}
	103
	104	static void mvebu_hwcc_dma_sync(struct device *dev, dma_addr_t dma_handle,
	105	size_t size, enum dma_data_direction dir)
	106	{
	107	if (dir != DMA_TO_DEVICE)
	108	mvebu_hwcc_sync_io_barrier();
	109	}
	110
	111	static struct dma_map_ops mvebu_hwcc_dma_ops = {
	112	.alloc = arm_dma_alloc,
	113	.free = arm_dma_free,
	114	.mmap = arm_dma_mmap,
	115	.map_page = mvebu_hwcc_dma_map_page,
	116	.unmap_page = mvebu_hwcc_dma_unmap_page,
	117	.get_sgtable = arm_dma_get_sgtable,
	118	.map_sg = arm_dma_map_sg,
	119	.unmap_sg = arm_dma_unmap_sg,
	120	.sync_single_for_cpu = mvebu_hwcc_dma_sync,
	121	.sync_single_for_device = mvebu_hwcc_dma_sync,
	122	.sync_sg_for_cpu = arm_dma_sync_sg_for_cpu,
	123	.sync_sg_for_device = arm_dma_sync_sg_for_device,
	124	.set_dma_mask = arm_dma_set_mask,
	125	};
	126
b0063aad TP	127	static int mvebu_hwcc_notifier(struct notifier_block *nb,
b0063aad TP	128	unsigned long event, void *__dev)
e60304f8 GC	129	{
	130	struct device *dev = __dev;
	131
	132	if (event != BUS_NOTIFY_ADD_DEVICE)
	133	return NOTIFY_DONE;
	134	set_dma_ops(dev, &mvebu_hwcc_dma_ops);
	135
	136	return NOTIFY_OK;
	137	}
	138
b0063aad TP	139	static struct notifier_block mvebu_hwcc_nb = {
b0063aad TP	140	.notifier_call = mvebu_hwcc_notifier,
e60304f8 GC	141	};
e60304f8 GC	142
a728b977 EG	143	static struct notifier_block mvebu_hwcc_pci_nb = {
	144	.notifier_call = mvebu_hwcc_notifier,
	145	};
	146
924d38f4 TP	147	static void __init armada_370_coherency_init(struct device_node *np)
	148	{
	149	struct resource res;
	150
	151	of_address_to_resource(np, 0, &res);
	152	coherency_phys_base = res.start;
	153	/*
	154	* Ensure secondary CPUs will see the updated value,
	155	* which they read before they join the coherency
	156	* fabric, and therefore before they are coherent with
	157	* the boot CPU cache.
	158	*/
	159	sync_cache_w(&coherency_phys_base);
	160	coherency_base = of_iomap(np, 0);
	161	coherency_cpu_base = of_iomap(np, 1);
952f4ca7	162	set_cpu_coherent();
924d38f4 TP	163	}
924d38f4 TP	164
497a9230 TP	165	/*
	166	* This ioremap hook is used on Armada 375/38x to ensure that PCIe
	167	* memory areas are mapped as MT_UNCACHED instead of MT_DEVICE. This
	168	* is needed as a workaround for a deadlock issue between the PCIe
	169	* interface and the cache controller.
	170	*/
	171	static void __iomem *
	172	armada_pcie_wa_ioremap_caller(phys_addr_t phys_addr, size_t size,
	173	unsigned int mtype, void *caller)
	174	{
	175	struct resource pcie_mem;
	176
	177	mvebu_mbus_get_pcie_mem_aperture(&pcie_mem);
	178
	179	if (pcie_mem.start <= phys_addr && (phys_addr + size) <= pcie_mem.end)
	180	mtype = MT_UNCACHED;
	181
	182	return __arm_ioremap_caller(phys_addr, size, mtype, caller);
	183	}
	184
d0de9323	185	static void __init armada_375_380_coherency_init(struct device_node *np)
77fa4b9a	186	{
497a9230 TP	187	struct device_node *cache_dn;
497a9230 TP	188
77fa4b9a	189	coherency_cpu_base = of_iomap(np, 0);
497a9230 TP	190	arch_ioremap_caller = armada_pcie_wa_ioremap_caller;
	191
	192	/*
	193	* Add the PL310 property "arm,io-coherent". This makes sure the
	194	* outer sync operation is not used, which allows to
	195	* workaround the system erratum that causes deadlocks when
	196	* doing PCIe in an SMP situation on Armada 375 and Armada
	197	* 38x.
	198	*/
	199	for_each_compatible_node(cache_dn, NULL, "arm,pl310-cache") {
	200	struct property *p;
	201
	202	p = kzalloc(sizeof(*p), GFP_KERNEL);
	203	p->name = kstrdup("arm,io-coherent", GFP_KERNEL);
	204	of_add_property(cache_dn, p);
	205	}
77fa4b9a TP	206	}
77fa4b9a TP	207
501f928e	208	static int coherency_type(void)
009f1315 GC	209	{
009f1315 GC	210	struct device_node *np;
5fbba080	211	const struct of_device_id *match;
e5535545	212	int type;
009f1315	213
e5535545 TP	214	/*
	215	* The coherency fabric is needed:
	216	* - For coherency between processors on Armada XP, so only
	217	* when SMP is enabled.
	218	* - For coherency between the processor and I/O devices, but
	219	* this coherency requires many pre-requisites (write
	220	* allocate cache policy, shareable pages, SMP bit set) that
	221	* are only meant in SMP situations.
	222	*
	223	* Note that this means that on Armada 370, there is currently
	224	* no way to use hardware I/O coherency, because even when
	225	* CONFIG_SMP is enabled, is_smp() returns false due to the
	226	* Armada 370 being a single-core processor. To lift this
	227	* limitation, we would have to find a way to make the cache
	228	* policy set to write-allocate (on all Armada SoCs), and to
	229	* set the shareable attribute in page tables (on all Armada
	230	* SoCs except the Armada 370). Unfortunately, such decisions
	231	* are taken very early in the kernel boot process, at a point
	232	* where we don't know yet on which SoC we are running.
	233
	234	*/
	235	if (!is_smp())
	236	return COHERENCY_FABRIC_TYPE_NONE;
924d38f4	237
e5535545 TP	238	np = of_find_matching_node_and_match(NULL, of_coherency_table, &match);
	239	if (!np)
	240	return COHERENCY_FABRIC_TYPE_NONE;
924d38f4	241
e5535545	242	type = (int) match->data;
77fa4b9a	243
e5535545	244	of_node_put(np);
009f1315	245
e5535545	246	return type;
009f1315	247	}
865e0527	248
8f1e8ee2 TP	249	/*
	250	* As a precaution, we currently completely disable hardware I/O
	251	* coherency, until enough testing is done with automatic I/O
	252	* synchronization barriers to validate that it is a proper solution.
	253	*/
501f928e	254	int coherency_available(void)
865e0527	255	{
8f1e8ee2	256	return false;
501f928e TP	257	}
	258
	259	int __init coherency_init(void)
	260	{
	261	int type = coherency_type();
abe511ac JZ	262	struct device_node *np;
	263
	264	np = of_find_matching_node(NULL, of_coherency_table);
501f928e TP	265
	266	if (type == COHERENCY_FABRIC_TYPE_ARMADA_370_XP)
	267	armada_370_coherency_init(np);
d0de9323 TP	268	else if (type == COHERENCY_FABRIC_TYPE_ARMADA_375 \|\|
	269	type == COHERENCY_FABRIC_TYPE_ARMADA_380)
	270	armada_375_380_coherency_init(np);
501f928e	271
2eb04ae0 TP	272	of_node_put(np);
2eb04ae0 TP	273
501f928e TP	274	return 0;
	275	}
	276
	277	static int __init coherency_late_init(void)
	278	{
ef01c6c3 TP	279	if (coherency_available())
	280	bus_register_notifier(&platform_bus_type,
	281	&mvebu_hwcc_nb);
865e0527 TP	282	return 0;
	283	}
	284
	285	postcore_initcall(coherency_late_init);
b0063aad	286
8828ccc3	287	#if IS_ENABLED(CONFIG_PCI)
b0063aad TP	288	static int __init coherency_pci_init(void)
	289	{
	290	if (coherency_available())
	291	bus_register_notifier(&pci_bus_type,
a728b977	292	&mvebu_hwcc_pci_nb);
b0063aad TP	293	return 0;
	294	}
	295
	296	arch_initcall(coherency_pci_init);
8828ccc3	297	#endif