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7444dad2 GC |
1 | /* |
2 | * Power Management Service Unit(PMSU) support for Armada 370/XP platforms. | |
3 | * | |
4 | * Copyright (C) 2012 Marvell | |
5 | * | |
6 | * Yehuda Yitschak <yehuday@marvell.com> | |
7 | * Gregory Clement <gregory.clement@free-electrons.com> | |
8 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | |
9 | * | |
10 | * This file is licensed under the terms of the GNU General Public | |
11 | * License version 2. This program is licensed "as is" without any | |
12 | * warranty of any kind, whether express or implied. | |
13 | * | |
14 | * The Armada 370 and Armada XP SOCs have a power management service | |
15 | * unit which is responsible for powering down and waking up CPUs and | |
16 | * other SOC units | |
17 | */ | |
18 | ||
bd045a1e TP |
19 | #define pr_fmt(fmt) "mvebu-pmsu: " fmt |
20 | ||
d163ee16 | 21 | #include <linux/cpu_pm.h> |
7444dad2 | 22 | #include <linux/init.h> |
7444dad2 | 23 | #include <linux/io.h> |
3e328428 | 24 | #include <linux/kernel.h> |
3076cc58 | 25 | #include <linux/mbus.h> |
3e328428 | 26 | #include <linux/of_address.h> |
8c16babc | 27 | #include <linux/platform_device.h> |
49754ffe | 28 | #include <linux/resource.h> |
3e328428 | 29 | #include <linux/smp.h> |
c3e04cab GC |
30 | #include <asm/cacheflush.h> |
31 | #include <asm/cp15.h> | |
7444dad2 | 32 | #include <asm/smp_plat.h> |
c3e04cab GC |
33 | #include <asm/suspend.h> |
34 | #include <asm/tlbflush.h> | |
49754ffe | 35 | #include "common.h" |
7444dad2 GC |
36 | |
37 | static void __iomem *pmsu_mp_base; | |
7444dad2 | 38 | |
0c3acc74 GC |
39 | #define PMSU_BASE_OFFSET 0x100 |
40 | #define PMSU_REG_SIZE 0x1000 | |
41 | ||
f713c7e7 | 42 | /* PMSU MP registers */ |
c3e04cab GC |
43 | #define PMSU_CONTROL_AND_CONFIG(cpu) ((cpu * 0x100) + 0x104) |
44 | #define PMSU_CONTROL_AND_CONFIG_DFS_REQ BIT(18) | |
45 | #define PMSU_CONTROL_AND_CONFIG_PWDDN_REQ BIT(16) | |
46 | #define PMSU_CONTROL_AND_CONFIG_L2_PWDDN BIT(20) | |
47 | ||
48 | #define PMSU_CPU_POWER_DOWN_CONTROL(cpu) ((cpu * 0x100) + 0x108) | |
49 | ||
50 | #define PMSU_CPU_POWER_DOWN_DIS_SNP_Q_SKIP BIT(0) | |
51 | ||
52 | #define PMSU_STATUS_AND_MASK(cpu) ((cpu * 0x100) + 0x10c) | |
53 | #define PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT BIT(16) | |
54 | #define PMSU_STATUS_AND_MASK_SNP_Q_EMPTY_WAIT BIT(17) | |
55 | #define PMSU_STATUS_AND_MASK_IRQ_WAKEUP BIT(20) | |
56 | #define PMSU_STATUS_AND_MASK_FIQ_WAKEUP BIT(21) | |
57 | #define PMSU_STATUS_AND_MASK_DBG_WAKEUP BIT(22) | |
58 | #define PMSU_STATUS_AND_MASK_IRQ_MASK BIT(24) | |
59 | #define PMSU_STATUS_AND_MASK_FIQ_MASK BIT(25) | |
60 | ||
f713c7e7 GC |
61 | #define PMSU_BOOT_ADDR_REDIRECT_OFFSET(cpu) ((cpu * 0x100) + 0x124) |
62 | ||
63 | /* PMSU fabric registers */ | |
64 | #define L2C_NFABRIC_PM_CTL 0x4 | |
65 | #define L2C_NFABRIC_PM_CTL_PWR_DOWN BIT(20) | |
7444dad2 | 66 | |
3076cc58 GC |
67 | #define SRAM_PHYS_BASE 0xFFFF0000 |
68 | #define BOOTROM_BASE 0xFFF00000 | |
69 | #define BOOTROM_SIZE 0x100000 | |
70 | ||
c3e04cab GC |
71 | extern void ll_disable_coherency(void); |
72 | extern void ll_enable_coherency(void); | |
73 | ||
6509dc74 TP |
74 | extern void armada_370_xp_cpu_resume(void); |
75 | ||
8c16babc GC |
76 | static struct platform_device armada_xp_cpuidle_device = { |
77 | .name = "cpuidle-armada-370-xp", | |
78 | }; | |
79 | ||
7444dad2 | 80 | static struct of_device_id of_pmsu_table[] = { |
0c3acc74 GC |
81 | { .compatible = "marvell,armada-370-pmsu", }, |
82 | { .compatible = "marvell,armada-370-xp-pmsu", }, | |
b4bca249 | 83 | { .compatible = "marvell,armada-380-pmsu", }, |
7444dad2 GC |
84 | { /* end of list */ }, |
85 | }; | |
86 | ||
05ad6906 | 87 | void mvebu_pmsu_set_cpu_boot_addr(int hw_cpu, void *boot_addr) |
02e7b067 GC |
88 | { |
89 | writel(virt_to_phys(boot_addr), pmsu_mp_base + | |
90 | PMSU_BOOT_ADDR_REDIRECT_OFFSET(hw_cpu)); | |
91 | } | |
92 | ||
3076cc58 GC |
93 | extern unsigned char mvebu_boot_wa_start; |
94 | extern unsigned char mvebu_boot_wa_end; | |
95 | ||
96 | /* | |
97 | * This function sets up the boot address workaround needed for SMP | |
98 | * boot on Armada 375 Z1 and cpuidle on Armada 370. It unmaps the | |
99 | * BootROM Mbus window, and instead remaps a crypto SRAM into which a | |
100 | * custom piece of code is copied to replace the problematic BootROM. | |
101 | */ | |
102 | int mvebu_setup_boot_addr_wa(unsigned int crypto_eng_target, | |
103 | unsigned int crypto_eng_attribute, | |
104 | phys_addr_t resume_addr_reg) | |
105 | { | |
106 | void __iomem *sram_virt_base; | |
107 | u32 code_len = &mvebu_boot_wa_end - &mvebu_boot_wa_start; | |
108 | ||
109 | mvebu_mbus_del_window(BOOTROM_BASE, BOOTROM_SIZE); | |
110 | mvebu_mbus_add_window_by_id(crypto_eng_target, crypto_eng_attribute, | |
111 | SRAM_PHYS_BASE, SZ_64K); | |
112 | ||
113 | sram_virt_base = ioremap(SRAM_PHYS_BASE, SZ_64K); | |
114 | if (!sram_virt_base) { | |
115 | pr_err("Unable to map SRAM to setup the boot address WA\n"); | |
116 | return -ENOMEM; | |
117 | } | |
118 | ||
119 | memcpy(sram_virt_base, &mvebu_boot_wa_start, code_len); | |
120 | ||
121 | /* | |
122 | * The last word of the code copied in SRAM must contain the | |
123 | * physical base address of the PMSU register. We | |
124 | * intentionally store this address in the native endianness | |
125 | * of the system. | |
126 | */ | |
127 | __raw_writel((unsigned long)resume_addr_reg, | |
128 | sram_virt_base + code_len - 4); | |
129 | ||
130 | iounmap(sram_virt_base); | |
131 | ||
132 | return 0; | |
133 | } | |
134 | ||
b12634e3 | 135 | static int __init armada_370_xp_pmsu_init(void) |
7444dad2 GC |
136 | { |
137 | struct device_node *np; | |
bd045a1e TP |
138 | struct resource res; |
139 | int ret = 0; | |
7444dad2 GC |
140 | |
141 | np = of_find_matching_node(NULL, of_pmsu_table); | |
bd045a1e TP |
142 | if (!np) |
143 | return 0; | |
144 | ||
145 | pr_info("Initializing Power Management Service Unit\n"); | |
146 | ||
147 | if (of_address_to_resource(np, 0, &res)) { | |
148 | pr_err("unable to get resource\n"); | |
149 | ret = -ENOENT; | |
150 | goto out; | |
7444dad2 GC |
151 | } |
152 | ||
0c3acc74 GC |
153 | if (of_device_is_compatible(np, "marvell,armada-370-xp-pmsu")) { |
154 | pr_warn(FW_WARN "deprecated pmsu binding\n"); | |
155 | res.start = res.start - PMSU_BASE_OFFSET; | |
156 | res.end = res.start + PMSU_REG_SIZE - 1; | |
157 | } | |
158 | ||
bd045a1e TP |
159 | if (!request_mem_region(res.start, resource_size(&res), |
160 | np->full_name)) { | |
161 | pr_err("unable to request region\n"); | |
162 | ret = -EBUSY; | |
163 | goto out; | |
164 | } | |
165 | ||
166 | pmsu_mp_base = ioremap(res.start, resource_size(&res)); | |
167 | if (!pmsu_mp_base) { | |
168 | pr_err("unable to map registers\n"); | |
169 | release_mem_region(res.start, resource_size(&res)); | |
170 | ret = -ENOMEM; | |
171 | goto out; | |
172 | } | |
173 | ||
174 | out: | |
175 | of_node_put(np); | |
176 | return ret; | |
7444dad2 GC |
177 | } |
178 | ||
f713c7e7 GC |
179 | static void armada_370_xp_pmsu_enable_l2_powerdown_onidle(void) |
180 | { | |
181 | u32 reg; | |
182 | ||
183 | if (pmsu_mp_base == NULL) | |
184 | return; | |
185 | ||
186 | /* Enable L2 & Fabric powerdown in Deep-Idle mode - Fabric */ | |
187 | reg = readl(pmsu_mp_base + L2C_NFABRIC_PM_CTL); | |
188 | reg |= L2C_NFABRIC_PM_CTL_PWR_DOWN; | |
189 | writel(reg, pmsu_mp_base + L2C_NFABRIC_PM_CTL); | |
190 | } | |
191 | ||
c3e04cab | 192 | /* No locking is needed because we only access per-CPU registers */ |
9ce35884 | 193 | static int armada_370_xp_prepare(unsigned long deepidle) |
c3e04cab GC |
194 | { |
195 | unsigned int hw_cpu = cpu_logical_map(smp_processor_id()); | |
196 | u32 reg; | |
197 | ||
198 | if (pmsu_mp_base == NULL) | |
bbb92284 | 199 | return -EINVAL; |
c3e04cab GC |
200 | |
201 | /* | |
202 | * Adjust the PMSU configuration to wait for WFI signal, enable | |
203 | * IRQ and FIQ as wakeup events, set wait for snoop queue empty | |
204 | * indication and mask IRQ and FIQ from CPU | |
205 | */ | |
206 | reg = readl(pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu)); | |
207 | reg |= PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT | | |
208 | PMSU_STATUS_AND_MASK_IRQ_WAKEUP | | |
209 | PMSU_STATUS_AND_MASK_FIQ_WAKEUP | | |
210 | PMSU_STATUS_AND_MASK_SNP_Q_EMPTY_WAIT | | |
211 | PMSU_STATUS_AND_MASK_IRQ_MASK | | |
212 | PMSU_STATUS_AND_MASK_FIQ_MASK; | |
213 | writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu)); | |
214 | ||
215 | reg = readl(pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu)); | |
216 | /* ask HW to power down the L2 Cache if needed */ | |
217 | if (deepidle) | |
218 | reg |= PMSU_CONTROL_AND_CONFIG_L2_PWDDN; | |
219 | ||
220 | /* request power down */ | |
221 | reg |= PMSU_CONTROL_AND_CONFIG_PWDDN_REQ; | |
222 | writel(reg, pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu)); | |
223 | ||
224 | /* Disable snoop disable by HW - SW is taking care of it */ | |
225 | reg = readl(pmsu_mp_base + PMSU_CPU_POWER_DOWN_CONTROL(hw_cpu)); | |
226 | reg |= PMSU_CPU_POWER_DOWN_DIS_SNP_Q_SKIP; | |
227 | writel(reg, pmsu_mp_base + PMSU_CPU_POWER_DOWN_CONTROL(hw_cpu)); | |
c3e04cab | 228 | |
9ce35884 GC |
229 | return 0; |
230 | } | |
231 | ||
232 | int armada_370_xp_pmsu_idle_enter(unsigned long deepidle) | |
233 | { | |
234 | int ret; | |
235 | ||
236 | ret = armada_370_xp_prepare(deepidle); | |
237 | if (ret) | |
238 | return ret; | |
239 | ||
c3e04cab GC |
240 | v7_exit_coherency_flush(all); |
241 | ||
242 | ll_disable_coherency(); | |
243 | ||
244 | dsb(); | |
245 | ||
246 | wfi(); | |
247 | ||
248 | /* If we are here, wfi failed. As processors run out of | |
249 | * coherency for some time, tlbs might be stale, so flush them | |
250 | */ | |
251 | local_flush_tlb_all(); | |
252 | ||
253 | ll_enable_coherency(); | |
254 | ||
255 | /* Test the CR_C bit and set it if it was cleared */ | |
256 | asm volatile( | |
0d461e1b GC |
257 | "mrc p15, 0, r0, c1, c0, 0 \n\t" |
258 | "tst r0, #(1 << 2) \n\t" | |
259 | "orreq r0, r0, #(1 << 2) \n\t" | |
260 | "mcreq p15, 0, r0, c1, c0, 0 \n\t" | |
c3e04cab | 261 | "isb " |
0d461e1b | 262 | : : : "r0"); |
c3e04cab GC |
263 | |
264 | pr_warn("Failed to suspend the system\n"); | |
265 | ||
266 | return 0; | |
267 | } | |
268 | ||
269 | static int armada_370_xp_cpu_suspend(unsigned long deepidle) | |
270 | { | |
bbb92284 | 271 | return cpu_suspend(deepidle, armada_370_xp_pmsu_idle_enter); |
c3e04cab GC |
272 | } |
273 | ||
274 | /* No locking is needed because we only access per-CPU registers */ | |
8ea875e7 | 275 | void armada_370_xp_pmsu_idle_exit(void) |
c3e04cab GC |
276 | { |
277 | unsigned int hw_cpu = cpu_logical_map(smp_processor_id()); | |
278 | u32 reg; | |
279 | ||
280 | if (pmsu_mp_base == NULL) | |
281 | return; | |
282 | ||
283 | /* cancel ask HW to power down the L2 Cache if possible */ | |
284 | reg = readl(pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu)); | |
285 | reg &= ~PMSU_CONTROL_AND_CONFIG_L2_PWDDN; | |
286 | writel(reg, pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu)); | |
287 | ||
288 | /* cancel Enable wakeup events and mask interrupts */ | |
289 | reg = readl(pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu)); | |
290 | reg &= ~(PMSU_STATUS_AND_MASK_IRQ_WAKEUP | PMSU_STATUS_AND_MASK_FIQ_WAKEUP); | |
291 | reg &= ~PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT; | |
292 | reg &= ~PMSU_STATUS_AND_MASK_SNP_Q_EMPTY_WAIT; | |
293 | reg &= ~(PMSU_STATUS_AND_MASK_IRQ_MASK | PMSU_STATUS_AND_MASK_FIQ_MASK); | |
294 | writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu)); | |
295 | } | |
296 | ||
d163ee16 GC |
297 | static int armada_370_xp_cpu_pm_notify(struct notifier_block *self, |
298 | unsigned long action, void *hcpu) | |
299 | { | |
300 | if (action == CPU_PM_ENTER) { | |
301 | unsigned int hw_cpu = cpu_logical_map(smp_processor_id()); | |
302 | mvebu_pmsu_set_cpu_boot_addr(hw_cpu, armada_370_xp_cpu_resume); | |
303 | } else if (action == CPU_PM_EXIT) { | |
bbb92284 | 304 | armada_370_xp_pmsu_idle_exit(); |
d163ee16 GC |
305 | } |
306 | ||
307 | return NOTIFY_OK; | |
308 | } | |
309 | ||
310 | static struct notifier_block armada_370_xp_cpu_pm_notifier = { | |
311 | .notifier_call = armada_370_xp_cpu_pm_notify, | |
312 | }; | |
313 | ||
6fc770f2 | 314 | static int __init armada_370_xp_cpu_pm_init(void) |
8c16babc GC |
315 | { |
316 | struct device_node *np; | |
317 | ||
318 | /* | |
319 | * Check that all the requirements are available to enable | |
320 | * cpuidle. So far, it is only supported on Armada XP, cpuidle | |
321 | * needs the coherency fabric and the PMSU enabled | |
322 | */ | |
323 | ||
324 | if (!of_machine_is_compatible("marvell,armadaxp")) | |
325 | return 0; | |
326 | ||
327 | np = of_find_compatible_node(NULL, NULL, "marvell,coherency-fabric"); | |
328 | if (!np) | |
329 | return 0; | |
330 | of_node_put(np); | |
331 | ||
332 | np = of_find_matching_node(NULL, of_pmsu_table); | |
333 | if (!np) | |
334 | return 0; | |
335 | of_node_put(np); | |
336 | ||
337 | armada_370_xp_pmsu_enable_l2_powerdown_onidle(); | |
338 | armada_xp_cpuidle_device.dev.platform_data = armada_370_xp_cpu_suspend; | |
339 | platform_device_register(&armada_xp_cpuidle_device); | |
340 | cpu_pm_register_notifier(&armada_370_xp_cpu_pm_notifier); | |
341 | ||
342 | return 0; | |
343 | } | |
344 | ||
345 | arch_initcall(armada_370_xp_cpu_pm_init); | |
7444dad2 | 346 | early_initcall(armada_370_xp_pmsu_init); |