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7444dad2 GC |
1 | /* |
2 | * Power Management Service Unit(PMSU) support for Armada 370/XP platforms. | |
3 | * | |
4 | * Copyright (C) 2012 Marvell | |
5 | * | |
6 | * Yehuda Yitschak <yehuday@marvell.com> | |
7 | * Gregory Clement <gregory.clement@free-electrons.com> | |
8 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | |
9 | * | |
10 | * This file is licensed under the terms of the GNU General Public | |
11 | * License version 2. This program is licensed "as is" without any | |
12 | * warranty of any kind, whether express or implied. | |
13 | * | |
14 | * The Armada 370 and Armada XP SOCs have a power management service | |
15 | * unit which is responsible for powering down and waking up CPUs and | |
16 | * other SOC units | |
17 | */ | |
18 | ||
bd045a1e TP |
19 | #define pr_fmt(fmt) "mvebu-pmsu: " fmt |
20 | ||
d163ee16 | 21 | #include <linux/cpu_pm.h> |
7444dad2 GC |
22 | #include <linux/kernel.h> |
23 | #include <linux/init.h> | |
24 | #include <linux/of_address.h> | |
25 | #include <linux/io.h> | |
8c16babc | 26 | #include <linux/platform_device.h> |
7444dad2 | 27 | #include <linux/smp.h> |
49754ffe | 28 | #include <linux/resource.h> |
c3e04cab GC |
29 | #include <asm/cacheflush.h> |
30 | #include <asm/cp15.h> | |
7444dad2 | 31 | #include <asm/smp_plat.h> |
c3e04cab GC |
32 | #include <asm/suspend.h> |
33 | #include <asm/tlbflush.h> | |
49754ffe | 34 | #include "common.h" |
7444dad2 GC |
35 | |
36 | static void __iomem *pmsu_mp_base; | |
7444dad2 | 37 | |
0c3acc74 GC |
38 | #define PMSU_BASE_OFFSET 0x100 |
39 | #define PMSU_REG_SIZE 0x1000 | |
40 | ||
f713c7e7 | 41 | /* PMSU MP registers */ |
c3e04cab GC |
42 | #define PMSU_CONTROL_AND_CONFIG(cpu) ((cpu * 0x100) + 0x104) |
43 | #define PMSU_CONTROL_AND_CONFIG_DFS_REQ BIT(18) | |
44 | #define PMSU_CONTROL_AND_CONFIG_PWDDN_REQ BIT(16) | |
45 | #define PMSU_CONTROL_AND_CONFIG_L2_PWDDN BIT(20) | |
46 | ||
47 | #define PMSU_CPU_POWER_DOWN_CONTROL(cpu) ((cpu * 0x100) + 0x108) | |
48 | ||
49 | #define PMSU_CPU_POWER_DOWN_DIS_SNP_Q_SKIP BIT(0) | |
50 | ||
51 | #define PMSU_STATUS_AND_MASK(cpu) ((cpu * 0x100) + 0x10c) | |
52 | #define PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT BIT(16) | |
53 | #define PMSU_STATUS_AND_MASK_SNP_Q_EMPTY_WAIT BIT(17) | |
54 | #define PMSU_STATUS_AND_MASK_IRQ_WAKEUP BIT(20) | |
55 | #define PMSU_STATUS_AND_MASK_FIQ_WAKEUP BIT(21) | |
56 | #define PMSU_STATUS_AND_MASK_DBG_WAKEUP BIT(22) | |
57 | #define PMSU_STATUS_AND_MASK_IRQ_MASK BIT(24) | |
58 | #define PMSU_STATUS_AND_MASK_FIQ_MASK BIT(25) | |
59 | ||
f713c7e7 GC |
60 | #define PMSU_BOOT_ADDR_REDIRECT_OFFSET(cpu) ((cpu * 0x100) + 0x124) |
61 | ||
62 | /* PMSU fabric registers */ | |
63 | #define L2C_NFABRIC_PM_CTL 0x4 | |
64 | #define L2C_NFABRIC_PM_CTL_PWR_DOWN BIT(20) | |
7444dad2 | 65 | |
c3e04cab GC |
66 | extern void ll_disable_coherency(void); |
67 | extern void ll_enable_coherency(void); | |
68 | ||
6509dc74 TP |
69 | extern void armada_370_xp_cpu_resume(void); |
70 | ||
8c16babc GC |
71 | static struct platform_device armada_xp_cpuidle_device = { |
72 | .name = "cpuidle-armada-370-xp", | |
73 | }; | |
74 | ||
7444dad2 | 75 | static struct of_device_id of_pmsu_table[] = { |
0c3acc74 GC |
76 | { .compatible = "marvell,armada-370-pmsu", }, |
77 | { .compatible = "marvell,armada-370-xp-pmsu", }, | |
b4bca249 | 78 | { .compatible = "marvell,armada-380-pmsu", }, |
7444dad2 GC |
79 | { /* end of list */ }, |
80 | }; | |
81 | ||
05ad6906 | 82 | void mvebu_pmsu_set_cpu_boot_addr(int hw_cpu, void *boot_addr) |
02e7b067 GC |
83 | { |
84 | writel(virt_to_phys(boot_addr), pmsu_mp_base + | |
85 | PMSU_BOOT_ADDR_REDIRECT_OFFSET(hw_cpu)); | |
86 | } | |
87 | ||
b12634e3 | 88 | static int __init armada_370_xp_pmsu_init(void) |
7444dad2 GC |
89 | { |
90 | struct device_node *np; | |
bd045a1e TP |
91 | struct resource res; |
92 | int ret = 0; | |
7444dad2 GC |
93 | |
94 | np = of_find_matching_node(NULL, of_pmsu_table); | |
bd045a1e TP |
95 | if (!np) |
96 | return 0; | |
97 | ||
98 | pr_info("Initializing Power Management Service Unit\n"); | |
99 | ||
100 | if (of_address_to_resource(np, 0, &res)) { | |
101 | pr_err("unable to get resource\n"); | |
102 | ret = -ENOENT; | |
103 | goto out; | |
7444dad2 GC |
104 | } |
105 | ||
0c3acc74 GC |
106 | if (of_device_is_compatible(np, "marvell,armada-370-xp-pmsu")) { |
107 | pr_warn(FW_WARN "deprecated pmsu binding\n"); | |
108 | res.start = res.start - PMSU_BASE_OFFSET; | |
109 | res.end = res.start + PMSU_REG_SIZE - 1; | |
110 | } | |
111 | ||
bd045a1e TP |
112 | if (!request_mem_region(res.start, resource_size(&res), |
113 | np->full_name)) { | |
114 | pr_err("unable to request region\n"); | |
115 | ret = -EBUSY; | |
116 | goto out; | |
117 | } | |
118 | ||
119 | pmsu_mp_base = ioremap(res.start, resource_size(&res)); | |
120 | if (!pmsu_mp_base) { | |
121 | pr_err("unable to map registers\n"); | |
122 | release_mem_region(res.start, resource_size(&res)); | |
123 | ret = -ENOMEM; | |
124 | goto out; | |
125 | } | |
126 | ||
127 | out: | |
128 | of_node_put(np); | |
129 | return ret; | |
7444dad2 GC |
130 | } |
131 | ||
f713c7e7 GC |
132 | static void armada_370_xp_pmsu_enable_l2_powerdown_onidle(void) |
133 | { | |
134 | u32 reg; | |
135 | ||
136 | if (pmsu_mp_base == NULL) | |
137 | return; | |
138 | ||
139 | /* Enable L2 & Fabric powerdown in Deep-Idle mode - Fabric */ | |
140 | reg = readl(pmsu_mp_base + L2C_NFABRIC_PM_CTL); | |
141 | reg |= L2C_NFABRIC_PM_CTL_PWR_DOWN; | |
142 | writel(reg, pmsu_mp_base + L2C_NFABRIC_PM_CTL); | |
143 | } | |
144 | ||
c3e04cab | 145 | /* No locking is needed because we only access per-CPU registers */ |
8ea875e7 | 146 | int armada_370_xp_pmsu_idle_enter(unsigned long deepidle) |
c3e04cab GC |
147 | { |
148 | unsigned int hw_cpu = cpu_logical_map(smp_processor_id()); | |
149 | u32 reg; | |
150 | ||
151 | if (pmsu_mp_base == NULL) | |
bbb92284 | 152 | return -EINVAL; |
c3e04cab GC |
153 | |
154 | /* | |
155 | * Adjust the PMSU configuration to wait for WFI signal, enable | |
156 | * IRQ and FIQ as wakeup events, set wait for snoop queue empty | |
157 | * indication and mask IRQ and FIQ from CPU | |
158 | */ | |
159 | reg = readl(pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu)); | |
160 | reg |= PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT | | |
161 | PMSU_STATUS_AND_MASK_IRQ_WAKEUP | | |
162 | PMSU_STATUS_AND_MASK_FIQ_WAKEUP | | |
163 | PMSU_STATUS_AND_MASK_SNP_Q_EMPTY_WAIT | | |
164 | PMSU_STATUS_AND_MASK_IRQ_MASK | | |
165 | PMSU_STATUS_AND_MASK_FIQ_MASK; | |
166 | writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu)); | |
167 | ||
168 | reg = readl(pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu)); | |
169 | /* ask HW to power down the L2 Cache if needed */ | |
170 | if (deepidle) | |
171 | reg |= PMSU_CONTROL_AND_CONFIG_L2_PWDDN; | |
172 | ||
173 | /* request power down */ | |
174 | reg |= PMSU_CONTROL_AND_CONFIG_PWDDN_REQ; | |
175 | writel(reg, pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu)); | |
176 | ||
177 | /* Disable snoop disable by HW - SW is taking care of it */ | |
178 | reg = readl(pmsu_mp_base + PMSU_CPU_POWER_DOWN_CONTROL(hw_cpu)); | |
179 | reg |= PMSU_CPU_POWER_DOWN_DIS_SNP_Q_SKIP; | |
180 | writel(reg, pmsu_mp_base + PMSU_CPU_POWER_DOWN_CONTROL(hw_cpu)); | |
c3e04cab GC |
181 | |
182 | v7_exit_coherency_flush(all); | |
183 | ||
184 | ll_disable_coherency(); | |
185 | ||
186 | dsb(); | |
187 | ||
188 | wfi(); | |
189 | ||
190 | /* If we are here, wfi failed. As processors run out of | |
191 | * coherency for some time, tlbs might be stale, so flush them | |
192 | */ | |
193 | local_flush_tlb_all(); | |
194 | ||
195 | ll_enable_coherency(); | |
196 | ||
197 | /* Test the CR_C bit and set it if it was cleared */ | |
198 | asm volatile( | |
0d461e1b GC |
199 | "mrc p15, 0, r0, c1, c0, 0 \n\t" |
200 | "tst r0, #(1 << 2) \n\t" | |
201 | "orreq r0, r0, #(1 << 2) \n\t" | |
202 | "mcreq p15, 0, r0, c1, c0, 0 \n\t" | |
c3e04cab | 203 | "isb " |
0d461e1b | 204 | : : : "r0"); |
c3e04cab GC |
205 | |
206 | pr_warn("Failed to suspend the system\n"); | |
207 | ||
208 | return 0; | |
209 | } | |
210 | ||
211 | static int armada_370_xp_cpu_suspend(unsigned long deepidle) | |
212 | { | |
bbb92284 | 213 | return cpu_suspend(deepidle, armada_370_xp_pmsu_idle_enter); |
c3e04cab GC |
214 | } |
215 | ||
216 | /* No locking is needed because we only access per-CPU registers */ | |
8ea875e7 | 217 | void armada_370_xp_pmsu_idle_exit(void) |
c3e04cab GC |
218 | { |
219 | unsigned int hw_cpu = cpu_logical_map(smp_processor_id()); | |
220 | u32 reg; | |
221 | ||
222 | if (pmsu_mp_base == NULL) | |
223 | return; | |
224 | ||
225 | /* cancel ask HW to power down the L2 Cache if possible */ | |
226 | reg = readl(pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu)); | |
227 | reg &= ~PMSU_CONTROL_AND_CONFIG_L2_PWDDN; | |
228 | writel(reg, pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu)); | |
229 | ||
230 | /* cancel Enable wakeup events and mask interrupts */ | |
231 | reg = readl(pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu)); | |
232 | reg &= ~(PMSU_STATUS_AND_MASK_IRQ_WAKEUP | PMSU_STATUS_AND_MASK_FIQ_WAKEUP); | |
233 | reg &= ~PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT; | |
234 | reg &= ~PMSU_STATUS_AND_MASK_SNP_Q_EMPTY_WAIT; | |
235 | reg &= ~(PMSU_STATUS_AND_MASK_IRQ_MASK | PMSU_STATUS_AND_MASK_FIQ_MASK); | |
236 | writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu)); | |
237 | } | |
238 | ||
d163ee16 GC |
239 | static int armada_370_xp_cpu_pm_notify(struct notifier_block *self, |
240 | unsigned long action, void *hcpu) | |
241 | { | |
242 | if (action == CPU_PM_ENTER) { | |
243 | unsigned int hw_cpu = cpu_logical_map(smp_processor_id()); | |
244 | mvebu_pmsu_set_cpu_boot_addr(hw_cpu, armada_370_xp_cpu_resume); | |
245 | } else if (action == CPU_PM_EXIT) { | |
bbb92284 | 246 | armada_370_xp_pmsu_idle_exit(); |
d163ee16 GC |
247 | } |
248 | ||
249 | return NOTIFY_OK; | |
250 | } | |
251 | ||
252 | static struct notifier_block armada_370_xp_cpu_pm_notifier = { | |
253 | .notifier_call = armada_370_xp_cpu_pm_notify, | |
254 | }; | |
255 | ||
6fc770f2 | 256 | static int __init armada_370_xp_cpu_pm_init(void) |
8c16babc GC |
257 | { |
258 | struct device_node *np; | |
259 | ||
260 | /* | |
261 | * Check that all the requirements are available to enable | |
262 | * cpuidle. So far, it is only supported on Armada XP, cpuidle | |
263 | * needs the coherency fabric and the PMSU enabled | |
264 | */ | |
265 | ||
266 | if (!of_machine_is_compatible("marvell,armadaxp")) | |
267 | return 0; | |
268 | ||
269 | np = of_find_compatible_node(NULL, NULL, "marvell,coherency-fabric"); | |
270 | if (!np) | |
271 | return 0; | |
272 | of_node_put(np); | |
273 | ||
274 | np = of_find_matching_node(NULL, of_pmsu_table); | |
275 | if (!np) | |
276 | return 0; | |
277 | of_node_put(np); | |
278 | ||
279 | armada_370_xp_pmsu_enable_l2_powerdown_onidle(); | |
280 | armada_xp_cpuidle_device.dev.platform_data = armada_370_xp_cpu_suspend; | |
281 | platform_device_register(&armada_xp_cpuidle_device); | |
282 | cpu_pm_register_notifier(&armada_370_xp_cpu_pm_notifier); | |
283 | ||
284 | return 0; | |
285 | } | |
286 | ||
287 | arch_initcall(armada_370_xp_cpu_pm_init); | |
7444dad2 | 288 | early_initcall(armada_370_xp_pmsu_init); |