[mirror_ubuntu-eoan-kernel.git] / arch / arm / mach-mx3 / cpu.c

/*
 * MX3 CPU type detection
 *
 * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/module.h>
#include <linux/io.h>
#include <mach/hardware.h>
#include <mach/iim.h>

unsigned int mx31_cpu_rev;
EXPORT_SYMBOL(mx31_cpu_rev);

struct mx3_cpu_type {
	u8 srev;
	const char *name;
	const char *v;
	unsigned int rev;
};

static struct mx3_cpu_type mx31_cpu_type[] __initdata = {
	{ .srev = 0x00, .name = "i.MX31(L)", .v = "1.0",  .rev = IMX_CHIP_REVISION_1_0	},
	{ .srev = 0x10, .name = "i.MX31",    .v = "1.1",  .rev = IMX_CHIP_REVISION_1_1	},
	{ .srev = 0x11, .name = "i.MX31L",   .v = "1.1",  .rev = IMX_CHIP_REVISION_1_1	},
	{ .srev = 0x12, .name = "i.MX31",    .v = "1.15", .rev = IMX_CHIP_REVISION_1_1	},
	{ .srev = 0x13, .name = "i.MX31L",   .v = "1.15", .rev = IMX_CHIP_REVISION_1_1	},
	{ .srev = 0x14, .name = "i.MX31",    .v = "1.2",  .rev = IMX_CHIP_REVISION_1_2	},
	{ .srev = 0x15, .name = "i.MX31L",   .v = "1.2",  .rev = IMX_CHIP_REVISION_1_2	},
	{ .srev = 0x28, .name = "i.MX31",    .v = "2.0",  .rev = IMX_CHIP_REVISION_2_0	},
	{ .srev = 0x29, .name = "i.MX31L",   .v = "2.0",  .rev = IMX_CHIP_REVISION_2_0	},
};

void __init mx31_read_cpu_rev(void)
{
	u32 i, srev;

	/* read SREV register from IIM module */
	srev = __raw_readl(MX31_IO_ADDRESS(MX31_IIM_BASE_ADDR + MXC_IIMSREV));

	for (i = 0; i < ARRAY_SIZE(mx31_cpu_type); i++)
		if (srev == mx31_cpu_type[i].srev) {
			printk(KERN_INFO
				"CPU identified as %s, silicon rev %s\n",
				mx31_cpu_type[i].name, mx31_cpu_type[i].v);

			mx31_cpu_rev = mx31_cpu_type[i].rev;
			return;
		}

	mx31_cpu_rev = IMX_CHIP_REVISION_UNKNOWN;

	printk(KERN_WARNING "Unknown CPU identifier. srev = %02x\n", srev);
}

unsigned int mx35_cpu_rev;
EXPORT_SYMBOL(mx35_cpu_rev);

void __init mx35_read_cpu_rev(void)
{
	u32 rev;
	char *srev;

	rev = __raw_readl(MX35_IO_ADDRESS(MX35_IIM_BASE_ADDR + MXC_IIMSREV));
	switch (rev) {
	case 0x00:
		mx35_cpu_rev = IMX_CHIP_REVISION_1_0;
		srev = "1.0";
		break;
	case 0x10:
		mx35_cpu_rev = IMX_CHIP_REVISION_2_0;
		srev = "2.0";
		break;
	case 0x11:
		mx35_cpu_rev = IMX_CHIP_REVISION_2_1;
		srev = "2.1";
		break;
	default:
		mx35_cpu_rev = IMX_CHIP_REVISION_UNKNOWN;
		srev = "unknown";
	}

	printk(KERN_INFO "CPU identified as i.MX35, silicon rev %s\n", srev);
}
Commit	Line	Data
52939c03 DM	1	/*
	2	* MX3 CPU type detection
	3	*
	4	* Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*/
	11
	12	#include <linux/module.h>
	13	#include <linux/io.h>
	14	#include <mach/hardware.h>
	15	#include <mach/iim.h>
	16
	17	unsigned int mx31_cpu_rev;
	18	EXPORT_SYMBOL(mx31_cpu_rev);
	19
	20	struct mx3_cpu_type {
	21	u8 srev;
	22	const char *name;
	23	const char *v;
	24	unsigned int rev;
	25	};
	26
	27	static struct mx3_cpu_type mx31_cpu_type[] __initdata = {
9ab4650f DN	28	{ .srev = 0x00, .name = "i.MX31(L)", .v = "1.0", .rev = IMX_CHIP_REVISION_1_0 },
	29	{ .srev = 0x10, .name = "i.MX31", .v = "1.1", .rev = IMX_CHIP_REVISION_1_1 },
	30	{ .srev = 0x11, .name = "i.MX31L", .v = "1.1", .rev = IMX_CHIP_REVISION_1_1 },
	31	{ .srev = 0x12, .name = "i.MX31", .v = "1.15", .rev = IMX_CHIP_REVISION_1_1 },
	32	{ .srev = 0x13, .name = "i.MX31L", .v = "1.15", .rev = IMX_CHIP_REVISION_1_1 },
	33	{ .srev = 0x14, .name = "i.MX31", .v = "1.2", .rev = IMX_CHIP_REVISION_1_2 },
	34	{ .srev = 0x15, .name = "i.MX31L", .v = "1.2", .rev = IMX_CHIP_REVISION_1_2 },
	35	{ .srev = 0x28, .name = "i.MX31", .v = "2.0", .rev = IMX_CHIP_REVISION_2_0 },
	36	{ .srev = 0x29, .name = "i.MX31L", .v = "2.0", .rev = IMX_CHIP_REVISION_2_0 },
52939c03 DM	37	};
	38
	39	void __init mx31_read_cpu_rev(void)
	40	{
	41	u32 i, srev;
	42
	43	/* read SREV register from IIM module */
fdb03870	44	srev = __raw_readl(MX31_IO_ADDRESS(MX31_IIM_BASE_ADDR + MXC_IIMSREV));
52939c03 DM	45
	46	for (i = 0; i < ARRAY_SIZE(mx31_cpu_type); i++)
	47	if (srev == mx31_cpu_type[i].srev) {
	48	printk(KERN_INFO
	49	"CPU identified as %s, silicon rev %s\n",
	50	mx31_cpu_type[i].name, mx31_cpu_type[i].v);
	51
	52	mx31_cpu_rev = mx31_cpu_type[i].rev;
	53	return;
	54	}
	55
9ab4650f DN	56	mx31_cpu_rev = IMX_CHIP_REVISION_UNKNOWN;
9ab4650f DN	57
52939c03 DM	58	printk(KERN_WARNING "Unknown CPU identifier. srev = %02x\n", srev);
52939c03 DM	59	}
67520f3a EB	60
	61	unsigned int mx35_cpu_rev;
	62	EXPORT_SYMBOL(mx35_cpu_rev);
	63
	64	void __init mx35_read_cpu_rev(void)
	65	{
	66	u32 rev;
9ab4650f	67	char *srev;
67520f3a EB	68
	69	rev = __raw_readl(MX35_IO_ADDRESS(MX35_IIM_BASE_ADDR + MXC_IIMSREV));
	70	switch (rev) {
	71	case 0x00:
9ab4650f	72	mx35_cpu_rev = IMX_CHIP_REVISION_1_0;
67520f3a EB	73	srev = "1.0";
	74	break;
	75	case 0x10:
9ab4650f	76	mx35_cpu_rev = IMX_CHIP_REVISION_2_0;
67520f3a EB	77	srev = "2.0";
	78	break;
	79	case 0x11:
9ab4650f	80	mx35_cpu_rev = IMX_CHIP_REVISION_2_1;
67520f3a EB	81	srev = "2.1";
67520f3a EB	82	break;
9ab4650f DN	83	default:
	84	mx35_cpu_rev = IMX_CHIP_REVISION_UNKNOWN;
	85	srev = "unknown";
67520f3a EB	86	}
	87
	88	printk(KERN_INFO "CPU identified as i.MX35, silicon rev %s\n", srev);
	89	}