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ARM: mx3: dynamically allocate mxc-ehci devices
[mirror_ubuntu-eoan-kernel.git] / arch / arm / mach-mx3 / mach-pcm037.c
CommitLineData
ce8ffef0
SH		 1/*
2 * Copyright (C) 2008 Sascha Hauer, Pengutronix
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
ce8ffef0
SH		 13 */
14
15#include <linux/types.h>
16#include <linux/init.h>
32c1ad9a 17#include <linux/dma-mapping.h>
ce8ffef0
SH		 18#include <linux/platform_device.h>
19#include <linux/mtd/physmap.h>
3dad21a9 20#include <linux/mtd/plat-ram.h>
ce8ffef0 21#include <linux/memory.h>
ba54b958 22#include <linux/gpio.h>
4353318e 23#include <linux/smsc911x.h>
ba54b958 24#include <linux/interrupt.h>
79206750
SH		 25#include <linux/i2c.h>
26#include <linux/i2c/at24.h>
dddd4a49
SH		 27#include <linux/delay.h>
28#include <linux/spi/spi.h>
29#include <linux/irq.h>
91bf9a25 30#include <linux/can/platform/sja1000.h>
ee14373c
SH		 31#include <linux/usb/otg.h>
32#include <linux/usb/ulpi.h>
5a0e3ad6 33#include <linux/gfp.h>
ce8ffef0 34
32c1ad9a
GL		 35#include <media/soc_camera.h>
36
ce8ffef0
SH		 37#include <asm/mach-types.h>
38#include <asm/mach/arch.h>
39#include <asm/mach/time.h>
40#include <asm/mach/map.h>
a09e64fb 41#include <mach/common.h>
32c1ad9a 42#include <mach/hardware.h>
a09e64fb 43#include <mach/iomux-mx3.h>
a8df0ee8 44#include <mach/ipu.h>
32c1ad9a 45#include <mach/mx3_camera.h>
a8df0ee8 46#include <mach/mx3fb.h>
ee14373c 47#include <mach/ulpi.h>
ce8ffef0 48
a2ceeef5 49#include "devices-imx31.h"
5cf09421 50#include "devices.h"
574ec547
GL		 51#include "pcm037.h"
52
53static enum pcm037_board_variant pcm037_instance = PCM037_PCM970;
54
55static int __init pcm037_variant_setup(char *str)
56{
57 if (!strcmp("eet", str))
58 pcm037_instance = PCM037_EET;
59 else if (strcmp("pcm970", str))
60 pr_warning("Unknown pcm037 baseboard variant %s\n", str);
61
62 return 1;
63}
64
65/* Supported values: "pcm970" (default) and "eet" */
66__setup("pcm037_variant=", pcm037_variant_setup);
67
68enum pcm037_board_variant pcm037_variant(void)
69{
70 return pcm037_instance;
71}
72
73/* UART1 with RTS/CTS handshake signals */
74static unsigned int pcm037_uart1_handshake_pins[] = {
75 MX31_PIN_CTS1__CTS1,
76 MX31_PIN_RTS1__RTS1,
77 MX31_PIN_TXD1__TXD1,
78 MX31_PIN_RXD1__RXD1,
79};
80
81/* UART1 without RTS/CTS handshake signals */
82static unsigned int pcm037_uart1_pins[] = {
83 MX31_PIN_TXD1__TXD1,
84 MX31_PIN_RXD1__RXD1,
85};
5cf09421 86
01ac7d58
SH		 87static unsigned int pcm037_pins[] = {
88 /* I2C */
89 MX31_PIN_CSPI2_MOSI__SCL,
90 MX31_PIN_CSPI2_MISO__SDA,
32c1ad9a
GL		 91 MX31_PIN_CSPI2_SS2__I2C3_SDA,
92 MX31_PIN_CSPI2_SCLK__I2C3_SCL,
01ac7d58
SH		 93 /* SDHC1 */
94 MX31_PIN_SD1_DATA3__SD1_DATA3,
95 MX31_PIN_SD1_DATA2__SD1_DATA2,
96 MX31_PIN_SD1_DATA1__SD1_DATA1,
97 MX31_PIN_SD1_DATA0__SD1_DATA0,
98 MX31_PIN_SD1_CLK__SD1_CLK,
99 MX31_PIN_SD1_CMD__SD1_CMD,
100 IOMUX_MODE(MX31_PIN_SCK6, IOMUX_CONFIG_GPIO), /* card detect */
101 IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_GPIO), /* write protect */
102 /* SPI1 */
103 MX31_PIN_CSPI1_MOSI__MOSI,
104 MX31_PIN_CSPI1_MISO__MISO,
105 MX31_PIN_CSPI1_SCLK__SCLK,
106 MX31_PIN_CSPI1_SPI_RDY__SPI_RDY,
107 MX31_PIN_CSPI1_SS0__SS0,
108 MX31_PIN_CSPI1_SS1__SS1,
109 MX31_PIN_CSPI1_SS2__SS2,
01ac7d58
SH		 110 /* UART2 */
111 MX31_PIN_TXD2__TXD2,
112 MX31_PIN_RXD2__RXD2,
113 MX31_PIN_CTS2__CTS2,
114 MX31_PIN_RTS2__RTS2,
115 /* UART3 */
116 MX31_PIN_CSPI3_MOSI__RXD3,
117 MX31_PIN_CSPI3_MISO__TXD3,
118 MX31_PIN_CSPI3_SCLK__RTS3,
119 MX31_PIN_CSPI3_SPI_RDY__CTS3,
120 /* LAN9217 irq pin */
121 IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO),
122 /* Onewire */
123 MX31_PIN_BATT_LINE__OWIRE,
124 /* Framebuffer */
125 MX31_PIN_LD0__LD0,
126 MX31_PIN_LD1__LD1,
127 MX31_PIN_LD2__LD2,
128 MX31_PIN_LD3__LD3,
129 MX31_PIN_LD4__LD4,
130 MX31_PIN_LD5__LD5,
131 MX31_PIN_LD6__LD6,
132 MX31_PIN_LD7__LD7,
133 MX31_PIN_LD8__LD8,
134 MX31_PIN_LD9__LD9,
135 MX31_PIN_LD10__LD10,
136 MX31_PIN_LD11__LD11,
137 MX31_PIN_LD12__LD12,
138 MX31_PIN_LD13__LD13,
139 MX31_PIN_LD14__LD14,
140 MX31_PIN_LD15__LD15,
141 MX31_PIN_LD16__LD16,
142 MX31_PIN_LD17__LD17,
143 MX31_PIN_VSYNC3__VSYNC3,
144 MX31_PIN_HSYNC__HSYNC,
145 MX31_PIN_FPSHIFT__FPSHIFT,
146 MX31_PIN_DRDY0__DRDY0,
147 MX31_PIN_D3_REV__D3_REV,
148 MX31_PIN_CONTRAST__CONTRAST,
149 MX31_PIN_D3_SPL__D3_SPL,
150 MX31_PIN_D3_CLS__D3_CLS,
151 MX31_PIN_LCS0__GPI03_23,
32c1ad9a
GL		 152 /* CSI */
153 IOMUX_MODE(MX31_PIN_CSI_D5, IOMUX_CONFIG_GPIO),
154 MX31_PIN_CSI_D6__CSI_D6,
155 MX31_PIN_CSI_D7__CSI_D7,
156 MX31_PIN_CSI_D8__CSI_D8,
157 MX31_PIN_CSI_D9__CSI_D9,
158 MX31_PIN_CSI_D10__CSI_D10,
159 MX31_PIN_CSI_D11__CSI_D11,
160 MX31_PIN_CSI_D12__CSI_D12,
161 MX31_PIN_CSI_D13__CSI_D13,
162 MX31_PIN_CSI_D14__CSI_D14,
163 MX31_PIN_CSI_D15__CSI_D15,
164 MX31_PIN_CSI_HSYNC__CSI_HSYNC,
165 MX31_PIN_CSI_MCLK__CSI_MCLK,
166 MX31_PIN_CSI_PIXCLK__CSI_PIXCLK,
167 MX31_PIN_CSI_VSYNC__CSI_VSYNC,
e0fd4db3
LF		 168 /* GPIO */
169 IOMUX_MODE(MX31_PIN_ATA_DMACK, IOMUX_CONFIG_GPIO),
ee14373c 170 /* OTG */
eb05bbeb
GL		 171 MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
172 MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
173 MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
174 MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
175 MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
176 MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
177 MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
178 MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
179 MX31_PIN_USBOTG_CLK__USBOTG_CLK,
180 MX31_PIN_USBOTG_DIR__USBOTG_DIR,
181 MX31_PIN_USBOTG_NXT__USBOTG_NXT,
182 MX31_PIN_USBOTG_STP__USBOTG_STP,
ee14373c
SH		 183 /* USB host 2 */
184 IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC),
185 IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC),
186 IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC),
187 IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC),
188 IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC),
189 IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC),
190 IOMUX_MODE(MX31_PIN_STXD3, IOMUX_CONFIG_FUNC),
191 IOMUX_MODE(MX31_PIN_SRXD3, IOMUX_CONFIG_FUNC),
192 IOMUX_MODE(MX31_PIN_SCK3, IOMUX_CONFIG_FUNC),
193 IOMUX_MODE(MX31_PIN_SFS3, IOMUX_CONFIG_FUNC),
194 IOMUX_MODE(MX31_PIN_STXD6, IOMUX_CONFIG_FUNC),
195 IOMUX_MODE(MX31_PIN_SRXD6, IOMUX_CONFIG_FUNC),
eb05bbeb
GL		 196};
197
ee14373c
SH		 198static struct physmap_flash_data pcm037_flash_data = {
199 .width = 2,
200};
eb05bbeb 201
ee14373c
SH		 202static struct resource pcm037_flash_resource = {
203 .start = 0xa0000000,
204 .end = 0xa1ffffff,
205 .flags = IORESOURCE_MEM,
eb05bbeb
GL		 206};
207
ce8ffef0
SH		 208static struct platform_device pcm037_flash = {
209 .name = "physmap-flash",
210 .id = 0,
211 .dev = {
212 .platform_data = &pcm037_flash_data,
213 },
214 .resource = &pcm037_flash_resource,
215 .num_resources = 1,
216};
217
16cf5c41 218static const struct imxuart_platform_data uart_pdata __initconst = {
a9b06233 219 .flags = IMXUART_HAVE_RTSCTS,
ce8ffef0
SH		 220};
221
4353318e 222static struct resource smsc911x_resources[] = {
3f4f54b4 223 {
f568dd7f
UKK		 224 .start = MX31_CS1_BASE_ADDR + 0x300,
225 .end = MX31_CS1_BASE_ADDR + 0x300 + SZ_64K - 1,
ba54b958 226 .flags = IORESOURCE_MEM,
3f4f54b4 227 }, {
ba54b958
GL		 228 .start = IOMUX_TO_IRQ(MX31_PIN_GPIO3_1),
229 .end = IOMUX_TO_IRQ(MX31_PIN_GPIO3_1),
4353318e 230 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
ba54b958
GL		 231 },
232};
233
4353318e
SG		 234static struct smsc911x_platform_config smsc911x_info = {
235 .flags = SMSC911X_USE_32BIT | SMSC911X_FORCE_INTERNAL_PHY |
236 SMSC911X_SAVE_MAC_ADDRESS,
237 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
238 .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
239 .phy_interface = PHY_INTERFACE_MODE_MII,
ba54b958
GL		 240};
241
242static struct platform_device pcm037_eth = {
4353318e 243 .name = "smsc911x",
ba54b958 244 .id = -1,
4353318e
SG		 245 .num_resources = ARRAY_SIZE(smsc911x_resources),
246 .resource = smsc911x_resources,
ba54b958 247 .dev = {
4353318e 248 .platform_data = &smsc911x_info,
ba54b958
GL		 249 },
250};
251
3dad21a9
SH		 252static struct platdata_mtd_ram pcm038_sram_data = {
253 .bankwidth = 2,
254};
255
256static struct resource pcm038_sram_resource = {
f568dd7f
UKK		 257 .start = MX31_CS4_BASE_ADDR,
258 .end = MX31_CS4_BASE_ADDR + 512 * 1024 - 1,
3dad21a9
SH		 259 .flags = IORESOURCE_MEM,
260};
261
262static struct platform_device pcm037_sram_device = {
263 .name = "mtd-ram",
264 .id = 0,
265 .dev = {
266 .platform_data = &pcm038_sram_data,
267 },
268 .num_resources = 1,
269 .resource = &pcm038_sram_resource,
270};
271
a2ceeef5
UKK		 272static const struct mxc_nand_platform_data
273pcm037_nand_board_info __initconst = {
3287abbd
SH		 274 .width = 1,
275 .hw_ecc = 1,
276};
277
4a9b8b0b 278static const struct imxi2c_platform_data pcm037_i2c1_data __initconst = {
79206750 279 .bitrate = 100000,
79206750
SH		 280};
281
4a9b8b0b 282static const struct imxi2c_platform_data pcm037_i2c2_data __initconst = {
32c1ad9a
GL		 283 .bitrate = 20000,
284};
285
79206750
SH		 286static struct at24_platform_data board_eeprom = {
287 .byte_len = 4096,
288 .page_size = 32,
289 .flags = AT24_FLAG_ADDR16,
290};
291
32c1ad9a
GL		 292static int pcm037_camera_power(struct device *dev, int on)
293{
294 /* disable or enable the camera in X7 or X8 PCM970 connector */
295 gpio_set_value(IOMUX_TO_GPIO(MX31_PIN_CSI_D5), !on);
296 return 0;
297}
298
9d00278d 299static struct i2c_board_info pcm037_i2c_camera[] = {
32c1ad9a
GL		 300 {
301 I2C_BOARD_INFO("mt9t031", 0x5d),
9d00278d
GL		 302 }, {
303 I2C_BOARD_INFO("mt9v022", 0x48),
32c1ad9a
GL		 304 },
305};
306
9d00278d
GL		 307static struct soc_camera_link iclink_mt9v022 = {
308 .bus_id = 0, /* Must match with the camera ID */
309 .board_info = &pcm037_i2c_camera[1],
310 .i2c_adapter_id = 2,
311 .module_name = "mt9v022",
312};
313
314static struct soc_camera_link iclink_mt9t031 = {
32c1ad9a
GL		 315 .bus_id = 0, /* Must match with the camera ID */
316 .power = pcm037_camera_power,
9d00278d 317 .board_info = &pcm037_i2c_camera[0],
32c1ad9a
GL		 318 .i2c_adapter_id = 2,
319 .module_name = "mt9t031",
320};
321
79206750 322static struct i2c_board_info pcm037_i2c_devices[] = {
32c1ad9a 323 {
79206750
SH		 324 I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
325 .platform_data = &board_eeprom,
326 }, {
cf87a6e2 327 I2C_BOARD_INFO("pcf8563", 0x51),
79206750
SH		 328 }
329};
32c1ad9a 330
9d00278d 331static struct platform_device pcm037_mt9t031 = {
32c1ad9a
GL		 332 .name = "soc-camera-pdrv",
333 .id = 0,
334 .dev = {
9d00278d
GL		 335 .platform_data = &iclink_mt9t031,
336 },
337};
338
339static struct platform_device pcm037_mt9v022 = {
340 .name = "soc-camera-pdrv",
341 .id = 1,
342 .dev = {
343 .platform_data = &iclink_mt9v022,
32c1ad9a
GL		 344 },
345};
79206750 346
dddd4a49
SH		 347/* Not connected by default */
348#ifdef PCM970_SDHC_RW_SWITCH
349static int pcm970_sdhc1_get_ro(struct device *dev)
f2cb641f 350{
dddd4a49
SH		 351 return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_SFS6));
352}
353#endif
354
4f163eb8
SH		 355#define SDHC1_GPIO_WP IOMUX_TO_GPIO(MX31_PIN_SFS6)
356#define SDHC1_GPIO_DET IOMUX_TO_GPIO(MX31_PIN_SCK6)
357
dddd4a49
SH		 358static int pcm970_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
359 void *data)
360{
361 int ret;
dddd4a49 362
4f163eb8
SH		 363 ret = gpio_request(SDHC1_GPIO_DET, "sdhc-detect");
364 if (ret)
365 return ret;
366
367 gpio_direction_input(SDHC1_GPIO_DET);
dddd4a49 368
4f163eb8
SH		 369#ifdef PCM970_SDHC_RW_SWITCH
370 ret = gpio_request(SDHC1_GPIO_WP, "sdhc-wp");
371 if (ret)
372 goto err_gpio_free;
373 gpio_direction_input(SDHC1_GPIO_WP);
374#endif
dddd4a49
SH		 375
376 ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_SCK6), detect_irq,
377 IRQF_DISABLED | IRQF_TRIGGER_FALLING,
378 "sdhc-detect", data);
4f163eb8
SH		 379 if (ret)
380 goto err_gpio_free_2;
381
382 return 0;
383
384err_gpio_free_2:
385#ifdef PCM970_SDHC_RW_SWITCH
386 gpio_free(SDHC1_GPIO_WP);
387err_gpio_free:
388#endif
389 gpio_free(SDHC1_GPIO_DET);
390
dddd4a49 391 return ret;
f2cb641f
SH		 392}
393
394static void pcm970_sdhc1_exit(struct device *dev, void *data)
395{
dddd4a49 396 free_irq(IOMUX_TO_IRQ(MX31_PIN_SCK6), data);
4f163eb8
SH		 397 gpio_free(SDHC1_GPIO_DET);
398 gpio_free(SDHC1_GPIO_WP);
f2cb641f
SH		 399}
400
6a697e3d 401static const struct imxmmc_platform_data sdhc_pdata __initconst = {
dddd4a49
SH		 402#ifdef PCM970_SDHC_RW_SWITCH
403 .get_ro = pcm970_sdhc1_get_ro,
404#endif
f2cb641f
SH		 405 .init = pcm970_sdhc1_init,
406 .exit = pcm970_sdhc1_exit,
407};
408
32c1ad9a
GL		 409struct mx3_camera_pdata camera_pdata = {
410 .dma_dev = &mx3_ipu.dev,
411 .flags = MX3_CAMERA_DATAWIDTH_8 | MX3_CAMERA_DATAWIDTH_10,
412 .mclk_10khz = 2000,
413};
414
415static int __init pcm037_camera_alloc_dma(const size_t buf_size)
416{
417 dma_addr_t dma_handle;
418 void *buf;
419 int dma;
420
421 if (buf_size < 2 * 1024 * 1024)
422 return -EINVAL;
423
424 buf = dma_alloc_coherent(NULL, buf_size, &dma_handle, GFP_KERNEL);
425 if (!buf) {
426 pr_err("%s: cannot allocate camera buffer-memory\n", __func__);
427 return -ENOMEM;
428 }
429
430 memset(buf, 0, buf_size);
431
432 dma = dma_declare_coherent_memory(&mx3_camera.dev,
433 dma_handle, dma_handle, buf_size,
434 DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
435
436 /* The way we call dma_declare_coherent_memory only a malloc can fail */
437 return dma & DMA_MEMORY_MAP ? 0 : -ENOMEM;
438}
439
ce8ffef0
SH		 440static struct platform_device *devices[] __initdata = {
441 &pcm037_flash,
3dad21a9 442 &pcm037_sram_device,
3170ba54 443 &imx_wdt_device0,
9d00278d
GL		 444 &pcm037_mt9t031,
445 &pcm037_mt9v022,
ce8ffef0
SH		 446};
447
a8df0ee8
GL		 448static struct ipu_platform_data mx3_ipu_data = {
449 .irq_base = MXC_IPU_IRQ_START,
450};
451
452static const struct fb_videomode fb_modedb[] = {
453 {
454 /* 240x320 @ 60 Hz Sharp */
455 .name = "Sharp-LQ035Q7DH06-QVGA",
456 .refresh = 60,
457 .xres = 240,
458 .yres = 320,
459 .pixclock = 185925,
460 .left_margin = 9,
461 .right_margin = 16,
462 .upper_margin = 7,
463 .lower_margin = 9,
464 .hsync_len = 1,
465 .vsync_len = 1,
466 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE |
467 FB_SYNC_CLK_INVERT | FB_SYNC_CLK_IDLE_EN,
468 .vmode = FB_VMODE_NONINTERLACED,
469 .flag = 0,
470 }, {
471 /* 240x320 @ 60 Hz */
472 .name = "TX090",
473 .refresh = 60,
474 .xres = 240,
475 .yres = 320,
476 .pixclock = 38255,
477 .left_margin = 144,
478 .right_margin = 0,
479 .upper_margin = 7,
480 .lower_margin = 40,
481 .hsync_len = 96,
482 .vsync_len = 1,
483 .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH,
484 .vmode = FB_VMODE_NONINTERLACED,
485 .flag = 0,
574ec547
GL		 486 }, {
487 /* 240x320 @ 60 Hz */
488 .name = "CMEL-OLED",
489 .refresh = 60,
490 .xres = 240,
491 .yres = 320,
492 .pixclock = 185925,
493 .left_margin = 9,
494 .right_margin = 16,
495 .upper_margin = 7,
496 .lower_margin = 9,
497 .hsync_len = 1,
498 .vsync_len = 1,
499 .sync = FB_SYNC_OE_ACT_HIGH | FB_SYNC_CLK_INVERT,
500 .vmode = FB_VMODE_NONINTERLACED,
501 .flag = 0,
a8df0ee8
GL		 502 },
503};
504
505static struct mx3fb_platform_data mx3fb_pdata = {
506 .dma_dev = &mx3_ipu.dev,
507 .name = "Sharp-LQ035Q7DH06-QVGA",
508 .mode = fb_modedb,
509 .num_modes = ARRAY_SIZE(fb_modedb),
510};
511
91bf9a25
SH		 512static struct resource pcm970_sja1000_resources[] = {
513 {
f568dd7f
UKK		 514 .start = MX31_CS5_BASE_ADDR,
515 .end = MX31_CS5_BASE_ADDR + 0x100 - 1,
91bf9a25
SH		 516 .flags = IORESOURCE_MEM,
517 }, {
518 .start = IOMUX_TO_IRQ(IOMUX_PIN(48, 105)),
519 .end = IOMUX_TO_IRQ(IOMUX_PIN(48, 105)),
520 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
521 },
522};
523
524struct sja1000_platform_data pcm970_sja1000_platform_data = {
56e6943b
WG		 525 .osc_freq = 16000000,
526 .ocr = OCR_TX1_PULLDOWN | OCR_TX0_PUSHPULL,
527 .cdr = CDR_CBP,
91bf9a25
SH		 528};
529
530static struct platform_device pcm970_sja1000 = {
531 .name = "sja1000_platform",
532 .dev = {
533 .platform_data = &pcm970_sja1000_platform_data,
534 },
535 .resource = pcm970_sja1000_resources,
536 .num_resources = ARRAY_SIZE(pcm970_sja1000_resources),
537};
538
c18e8fa5 539#if defined(CONFIG_USB_ULPI)
2d58de28 540static struct mxc_usbh_platform_data otg_pdata __initdata = {
ee14373c
SH		 541 .portsc = MXC_EHCI_MODE_ULPI,
542 .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
543};
544
2d58de28 545static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
ee14373c
SH		 546 .portsc = MXC_EHCI_MODE_ULPI,
547 .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
548};
c18e8fa5 549#endif
ee14373c 550
9e1dde33 551static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
ee14373c
SH		 552 .operating_mode = FSL_USB2_DR_DEVICE,
553 .phy_mode = FSL_USB2_PHY_ULPI,
554};
555
556static int otg_mode_host;
557
558static int __init pcm037_otg_mode(char *options)
559{
560 if (!strcmp(options, "host"))
561 otg_mode_host = 1;
562 else if (!strcmp(options, "device"))
563 otg_mode_host = 0;
564 else
565 pr_info("otg_mode neither \"host\" nor \"device\". "
566 "Defaulting to device\n");
567 return 0;
568}
569__setup("otg_mode=", pcm037_otg_mode);
570
ce8ffef0
SH		 571/*
572 * Board specific initialization.
573 */
574static void __init mxc_board_init(void)
575{
4f163eb8 576 int ret;
ee14373c
SH		 577
578 mxc_iomux_set_gpr(MUX_PGP_UH2, 1);
4f163eb8 579
01ac7d58
SH		 580 mxc_iomux_setup_multiple_pins(pcm037_pins, ARRAY_SIZE(pcm037_pins),
581 "pcm037");
582
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SH		 583#define H2_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS \
584 | PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
585
586 mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, H2_PAD_CFG);
587 mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, H2_PAD_CFG);
588 mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, H2_PAD_CFG);
589 mxc_iomux_set_pad(MX31_PIN_USBH2_STP, H2_PAD_CFG);
590 mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, H2_PAD_CFG); /* USBH2_DATA0 */
591 mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, H2_PAD_CFG); /* USBH2_DATA1 */
592 mxc_iomux_set_pad(MX31_PIN_SRXD6, H2_PAD_CFG); /* USBH2_DATA2 */
593 mxc_iomux_set_pad(MX31_PIN_STXD6, H2_PAD_CFG); /* USBH2_DATA3 */
594 mxc_iomux_set_pad(MX31_PIN_SFS3, H2_PAD_CFG); /* USBH2_DATA4 */
595 mxc_iomux_set_pad(MX31_PIN_SCK3, H2_PAD_CFG); /* USBH2_DATA5 */
596 mxc_iomux_set_pad(MX31_PIN_SRXD3, H2_PAD_CFG); /* USBH2_DATA6 */
597 mxc_iomux_set_pad(MX31_PIN_STXD3, H2_PAD_CFG); /* USBH2_DATA7 */
598
574ec547
GL		 599 if (pcm037_variant() == PCM037_EET)
600 mxc_iomux_setup_multiple_pins(pcm037_uart1_pins,
601 ARRAY_SIZE(pcm037_uart1_pins), "pcm037_uart1");
602 else
603 mxc_iomux_setup_multiple_pins(pcm037_uart1_handshake_pins,
604 ARRAY_SIZE(pcm037_uart1_handshake_pins),
605 "pcm037_uart1");
606
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SH		 607 platform_add_devices(devices, ARRAY_SIZE(devices));
608
16cf5c41
UKK		 609 imx31_add_imx_uart0(&uart_pdata);
610 /* XXX: should't this have .flags = 0 (i.e. no RTSCTS) on PCM037_EET? */
611 imx31_add_imx_uart1(&uart_pdata);
612 imx31_add_imx_uart2(&uart_pdata);
d517cab1 613
ae71a562 614 imx31_add_mxc_w1(NULL);
ba54b958 615
f8e5143b 616 /* LAN9217 IRQ pin */
4f163eb8
SH		 617 ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1), "lan9217-irq");
618 if (ret)
619 pr_warning("could not get LAN irq gpio\n");
620 else {
621 gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1));
622 platform_device_register(&pcm037_eth);
623 }
624
3287abbd 625
32c1ad9a 626 /* I2C adapters and devices */
79206750
SH		 627 i2c_register_board_info(1, pcm037_i2c_devices,
628 ARRAY_SIZE(pcm037_i2c_devices));
629
4a9b8b0b
UKK		 630 imx31_add_imx_i2c1(&pcm037_i2c1_data);
631 imx31_add_imx_i2c2(&pcm037_i2c2_data);
32c1ad9a 632
a2ceeef5 633 imx31_add_mxc_nand(&pcm037_nand_board_info);
6a697e3d 634 imx31_add_mxc_mmc(0, &sdhc_pdata);
a8df0ee8
GL		 635 mxc_register_device(&mx3_ipu, &mx3_ipu_data);
636 mxc_register_device(&mx3_fb, &mx3fb_pdata);
32c1ad9a
GL		 637
638 /* CSI */
639 /* Camera power: default - off */
640 ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_CSI_D5), "mt9t031-power");
641 if (!ret)
642 gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_CSI_D5), 1);
643 else
9d00278d 644 iclink_mt9t031.power = NULL;
32c1ad9a
GL		 645
646 if (!pcm037_camera_alloc_dma(4 * 1024 * 1024))
647 mxc_register_device(&mx3_camera, &camera_pdata);
91bf9a25
SH		 648
649 platform_device_register(&pcm970_sja1000);
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SH		 650
651#if defined(CONFIG_USB_ULPI)
652 if (otg_mode_host) {
653 otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
13dd0c97 654 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
ee14373c 655
2d58de28 656 imx31_add_mxc_ehci_otg(&otg_pdata);
ee14373c
SH		 657 }
658
659 usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
13dd0c97 660 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
ee14373c 661
2d58de28 662 imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
ee14373c
SH		 663#endif
664 if (!otg_mode_host)
9e1dde33 665 imx31_add_fsl_usb2_udc(&otg_device_pdata);
ee14373c 666
ce8ffef0
SH		 667}
668
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SH		 669static void __init pcm037_timer_init(void)
670{
30c730f8 671 mx31_clocks_init(26000000);
ce8ffef0
SH		 672}
673
674struct sys_timer pcm037_timer = {
675 .init = pcm037_timer_init,
676};
677
678MACHINE_START(PCM037, "Phytec Phycore pcm037")
679 /* Maintainer: Pengutronix */
34101237 680 .boot_params = MX3x_PHYS_OFFSET + 0x100,
cd4a05f9 681 .map_io = mx31_map_io,
c5aa0ad0 682 .init_irq = mx31_init_irq,
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SH		 683 .init_machine = mxc_board_init,
684 .timer = &pcm037_timer,
685MACHINE_END
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