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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit...
[mirror_ubuntu-zesty-kernel.git] / arch / arm / mach-mx3 / mach-pcm037.c
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ce8ffef0
SH		 1/*
2 * Copyright (C) 2008 Sascha Hauer, Pengutronix
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */
18
19#include <linux/types.h>
20#include <linux/init.h>
32c1ad9a 21#include <linux/dma-mapping.h>
ce8ffef0
SH		 22#include <linux/platform_device.h>
23#include <linux/mtd/physmap.h>
3dad21a9 24#include <linux/mtd/plat-ram.h>
ce8ffef0 25#include <linux/memory.h>
ba54b958 26#include <linux/gpio.h>
4353318e 27#include <linux/smsc911x.h>
ba54b958 28#include <linux/interrupt.h>
79206750
SH		 29#include <linux/i2c.h>
30#include <linux/i2c/at24.h>
dddd4a49
SH		 31#include <linux/delay.h>
32#include <linux/spi/spi.h>
33#include <linux/irq.h>
eb05bbeb 34#include <linux/fsl_devices.h>
91bf9a25 35#include <linux/can/platform/sja1000.h>
ee14373c
SH		 36#include <linux/usb/otg.h>
37#include <linux/usb/ulpi.h>
38#include <linux/fsl_devices.h>
5a0e3ad6 39#include <linux/gfp.h>
ce8ffef0 40
32c1ad9a
GL		 41#include <media/soc_camera.h>
42
ce8ffef0
SH		 43#include <asm/mach-types.h>
44#include <asm/mach/arch.h>
45#include <asm/mach/time.h>
46#include <asm/mach/map.h>
32c1ad9a 47#include <mach/board-pcm037.h>
a09e64fb 48#include <mach/common.h>
32c1ad9a
GL		 49#include <mach/hardware.h>
50#include <mach/i2c.h>
a09e64fb
RK		 51#include <mach/imx-uart.h>
52#include <mach/iomux-mx3.h>
a8df0ee8 53#include <mach/ipu.h>
32c1ad9a
GL		 54#include <mach/mmc.h>
55#include <mach/mx3_camera.h>
a8df0ee8 56#include <mach/mx3fb.h>
3287abbd 57#include <mach/mxc_nand.h>
ee14373c
SH		 58#include <mach/mxc_ehci.h>
59#include <mach/ulpi.h>
ce8ffef0 60
5cf09421 61#include "devices.h"
574ec547
GL		 62#include "pcm037.h"
63
64static enum pcm037_board_variant pcm037_instance = PCM037_PCM970;
65
66static int __init pcm037_variant_setup(char *str)
67{
68 if (!strcmp("eet", str))
69 pcm037_instance = PCM037_EET;
70 else if (strcmp("pcm970", str))
71 pr_warning("Unknown pcm037 baseboard variant %s\n", str);
72
73 return 1;
74}
75
76/* Supported values: "pcm970" (default) and "eet" */
77__setup("pcm037_variant=", pcm037_variant_setup);
78
79enum pcm037_board_variant pcm037_variant(void)
80{
81 return pcm037_instance;
82}
83
84/* UART1 with RTS/CTS handshake signals */
85static unsigned int pcm037_uart1_handshake_pins[] = {
86 MX31_PIN_CTS1__CTS1,
87 MX31_PIN_RTS1__RTS1,
88 MX31_PIN_TXD1__TXD1,
89 MX31_PIN_RXD1__RXD1,
90};
91
92/* UART1 without RTS/CTS handshake signals */
93static unsigned int pcm037_uart1_pins[] = {
94 MX31_PIN_TXD1__TXD1,
95 MX31_PIN_RXD1__RXD1,
96};
5cf09421 97
01ac7d58
SH		 98static unsigned int pcm037_pins[] = {
99 /* I2C */
100 MX31_PIN_CSPI2_MOSI__SCL,
101 MX31_PIN_CSPI2_MISO__SDA,
32c1ad9a
GL		 102 MX31_PIN_CSPI2_SS2__I2C3_SDA,
103 MX31_PIN_CSPI2_SCLK__I2C3_SCL,
01ac7d58
SH		 104 /* SDHC1 */
105 MX31_PIN_SD1_DATA3__SD1_DATA3,
106 MX31_PIN_SD1_DATA2__SD1_DATA2,
107 MX31_PIN_SD1_DATA1__SD1_DATA1,
108 MX31_PIN_SD1_DATA0__SD1_DATA0,
109 MX31_PIN_SD1_CLK__SD1_CLK,
110 MX31_PIN_SD1_CMD__SD1_CMD,
111 IOMUX_MODE(MX31_PIN_SCK6, IOMUX_CONFIG_GPIO), /* card detect */
112 IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_GPIO), /* write protect */
113 /* SPI1 */
114 MX31_PIN_CSPI1_MOSI__MOSI,
115 MX31_PIN_CSPI1_MISO__MISO,
116 MX31_PIN_CSPI1_SCLK__SCLK,
117 MX31_PIN_CSPI1_SPI_RDY__SPI_RDY,
118 MX31_PIN_CSPI1_SS0__SS0,
119 MX31_PIN_CSPI1_SS1__SS1,
120 MX31_PIN_CSPI1_SS2__SS2,
01ac7d58
SH		 121 /* UART2 */
122 MX31_PIN_TXD2__TXD2,
123 MX31_PIN_RXD2__RXD2,
124 MX31_PIN_CTS2__CTS2,
125 MX31_PIN_RTS2__RTS2,
126 /* UART3 */
127 MX31_PIN_CSPI3_MOSI__RXD3,
128 MX31_PIN_CSPI3_MISO__TXD3,
129 MX31_PIN_CSPI3_SCLK__RTS3,
130 MX31_PIN_CSPI3_SPI_RDY__CTS3,
131 /* LAN9217 irq pin */
132 IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO),
133 /* Onewire */
134 MX31_PIN_BATT_LINE__OWIRE,
135 /* Framebuffer */
136 MX31_PIN_LD0__LD0,
137 MX31_PIN_LD1__LD1,
138 MX31_PIN_LD2__LD2,
139 MX31_PIN_LD3__LD3,
140 MX31_PIN_LD4__LD4,
141 MX31_PIN_LD5__LD5,
142 MX31_PIN_LD6__LD6,
143 MX31_PIN_LD7__LD7,
144 MX31_PIN_LD8__LD8,
145 MX31_PIN_LD9__LD9,
146 MX31_PIN_LD10__LD10,
147 MX31_PIN_LD11__LD11,
148 MX31_PIN_LD12__LD12,
149 MX31_PIN_LD13__LD13,
150 MX31_PIN_LD14__LD14,
151 MX31_PIN_LD15__LD15,
152 MX31_PIN_LD16__LD16,
153 MX31_PIN_LD17__LD17,
154 MX31_PIN_VSYNC3__VSYNC3,
155 MX31_PIN_HSYNC__HSYNC,
156 MX31_PIN_FPSHIFT__FPSHIFT,
157 MX31_PIN_DRDY0__DRDY0,
158 MX31_PIN_D3_REV__D3_REV,
159 MX31_PIN_CONTRAST__CONTRAST,
160 MX31_PIN_D3_SPL__D3_SPL,
161 MX31_PIN_D3_CLS__D3_CLS,
162 MX31_PIN_LCS0__GPI03_23,
32c1ad9a
GL		 163 /* CSI */
164 IOMUX_MODE(MX31_PIN_CSI_D5, IOMUX_CONFIG_GPIO),
165 MX31_PIN_CSI_D6__CSI_D6,
166 MX31_PIN_CSI_D7__CSI_D7,
167 MX31_PIN_CSI_D8__CSI_D8,
168 MX31_PIN_CSI_D9__CSI_D9,
169 MX31_PIN_CSI_D10__CSI_D10,
170 MX31_PIN_CSI_D11__CSI_D11,
171 MX31_PIN_CSI_D12__CSI_D12,
172 MX31_PIN_CSI_D13__CSI_D13,
173 MX31_PIN_CSI_D14__CSI_D14,
174 MX31_PIN_CSI_D15__CSI_D15,
175 MX31_PIN_CSI_HSYNC__CSI_HSYNC,
176 MX31_PIN_CSI_MCLK__CSI_MCLK,
177 MX31_PIN_CSI_PIXCLK__CSI_PIXCLK,
178 MX31_PIN_CSI_VSYNC__CSI_VSYNC,
e0fd4db3
LF		 179 /* GPIO */
180 IOMUX_MODE(MX31_PIN_ATA_DMACK, IOMUX_CONFIG_GPIO),
ee14373c 181 /* OTG */
eb05bbeb
GL		 182 MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
183 MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
184 MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
185 MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
186 MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
187 MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
188 MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
189 MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
190 MX31_PIN_USBOTG_CLK__USBOTG_CLK,
191 MX31_PIN_USBOTG_DIR__USBOTG_DIR,
192 MX31_PIN_USBOTG_NXT__USBOTG_NXT,
193 MX31_PIN_USBOTG_STP__USBOTG_STP,
ee14373c
SH		 194 /* USB host 2 */
195 IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC),
196 IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC),
197 IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC),
198 IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC),
199 IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC),
200 IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC),
201 IOMUX_MODE(MX31_PIN_STXD3, IOMUX_CONFIG_FUNC),
202 IOMUX_MODE(MX31_PIN_SRXD3, IOMUX_CONFIG_FUNC),
203 IOMUX_MODE(MX31_PIN_SCK3, IOMUX_CONFIG_FUNC),
204 IOMUX_MODE(MX31_PIN_SFS3, IOMUX_CONFIG_FUNC),
205 IOMUX_MODE(MX31_PIN_STXD6, IOMUX_CONFIG_FUNC),
206 IOMUX_MODE(MX31_PIN_SRXD6, IOMUX_CONFIG_FUNC),
eb05bbeb
GL		 207};
208
ee14373c
SH		 209static struct physmap_flash_data pcm037_flash_data = {
210 .width = 2,
211};
eb05bbeb 212
ee14373c
SH		 213static struct resource pcm037_flash_resource = {
214 .start = 0xa0000000,
215 .end = 0xa1ffffff,
216 .flags = IORESOURCE_MEM,
eb05bbeb
GL		 217};
218
ce8ffef0
SH		 219static struct platform_device pcm037_flash = {
220 .name = "physmap-flash",
221 .id = 0,
222 .dev = {
223 .platform_data = &pcm037_flash_data,
224 },
225 .resource = &pcm037_flash_resource,
226 .num_resources = 1,
227};
228
229static struct imxuart_platform_data uart_pdata = {
a9b06233 230 .flags = IMXUART_HAVE_RTSCTS,
ce8ffef0
SH		 231};
232
4353318e 233static struct resource smsc911x_resources[] = {
3f4f54b4 234 {
f568dd7f
UKK		 235 .start = MX31_CS1_BASE_ADDR + 0x300,
236 .end = MX31_CS1_BASE_ADDR + 0x300 + SZ_64K - 1,
ba54b958 237 .flags = IORESOURCE_MEM,
3f4f54b4 238 }, {
ba54b958
GL		 239 .start = IOMUX_TO_IRQ(MX31_PIN_GPIO3_1),
240 .end = IOMUX_TO_IRQ(MX31_PIN_GPIO3_1),
4353318e 241 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
ba54b958
GL		 242 },
243};
244
4353318e
SG		 245static struct smsc911x_platform_config smsc911x_info = {
246 .flags = SMSC911X_USE_32BIT | SMSC911X_FORCE_INTERNAL_PHY |
247 SMSC911X_SAVE_MAC_ADDRESS,
248 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
249 .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
250 .phy_interface = PHY_INTERFACE_MODE_MII,
ba54b958
GL		 251};
252
253static struct platform_device pcm037_eth = {
4353318e 254 .name = "smsc911x",
ba54b958 255 .id = -1,
4353318e
SG		 256 .num_resources = ARRAY_SIZE(smsc911x_resources),
257 .resource = smsc911x_resources,
ba54b958 258 .dev = {
4353318e 259 .platform_data = &smsc911x_info,
ba54b958
GL		 260 },
261};
262
3dad21a9
SH		 263static struct platdata_mtd_ram pcm038_sram_data = {
264 .bankwidth = 2,
265};
266
267static struct resource pcm038_sram_resource = {
f568dd7f
UKK		 268 .start = MX31_CS4_BASE_ADDR,
269 .end = MX31_CS4_BASE_ADDR + 512 * 1024 - 1,
3dad21a9
SH		 270 .flags = IORESOURCE_MEM,
271};
272
273static struct platform_device pcm037_sram_device = {
274 .name = "mtd-ram",
275 .id = 0,
276 .dev = {
277 .platform_data = &pcm038_sram_data,
278 },
279 .num_resources = 1,
280 .resource = &pcm038_sram_resource,
281};
282
3287abbd
SH		 283static struct mxc_nand_platform_data pcm037_nand_board_info = {
284 .width = 1,
285 .hw_ecc = 1,
286};
287
79206750
SH		 288static struct imxi2c_platform_data pcm037_i2c_1_data = {
289 .bitrate = 100000,
79206750
SH		 290};
291
32c1ad9a
GL		 292static struct imxi2c_platform_data pcm037_i2c_2_data = {
293 .bitrate = 20000,
294};
295
79206750
SH		 296static struct at24_platform_data board_eeprom = {
297 .byte_len = 4096,
298 .page_size = 32,
299 .flags = AT24_FLAG_ADDR16,
300};
301
32c1ad9a
GL		 302static int pcm037_camera_power(struct device *dev, int on)
303{
304 /* disable or enable the camera in X7 or X8 PCM970 connector */
305 gpio_set_value(IOMUX_TO_GPIO(MX31_PIN_CSI_D5), !on);
306 return 0;
307}
308
9d00278d 309static struct i2c_board_info pcm037_i2c_camera[] = {
32c1ad9a
GL		 310 {
311 I2C_BOARD_INFO("mt9t031", 0x5d),
9d00278d
GL		 312 }, {
313 I2C_BOARD_INFO("mt9v022", 0x48),
32c1ad9a
GL		 314 },
315};
316
9d00278d
GL		 317static struct soc_camera_link iclink_mt9v022 = {
318 .bus_id = 0, /* Must match with the camera ID */
319 .board_info = &pcm037_i2c_camera[1],
320 .i2c_adapter_id = 2,
321 .module_name = "mt9v022",
322};
323
324static struct soc_camera_link iclink_mt9t031 = {
32c1ad9a
GL		 325 .bus_id = 0, /* Must match with the camera ID */
326 .power = pcm037_camera_power,
9d00278d 327 .board_info = &pcm037_i2c_camera[0],
32c1ad9a
GL		 328 .i2c_adapter_id = 2,
329 .module_name = "mt9t031",
330};
331
79206750 332static struct i2c_board_info pcm037_i2c_devices[] = {
32c1ad9a 333 {
79206750
SH		 334 I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
335 .platform_data = &board_eeprom,
336 }, {
cf87a6e2 337 I2C_BOARD_INFO("pcf8563", 0x51),
79206750
SH		 338 }
339};
32c1ad9a 340
9d00278d 341static struct platform_device pcm037_mt9t031 = {
32c1ad9a
GL		 342 .name = "soc-camera-pdrv",
343 .id = 0,
344 .dev = {
9d00278d
GL		 345 .platform_data = &iclink_mt9t031,
346 },
347};
348
349static struct platform_device pcm037_mt9v022 = {
350 .name = "soc-camera-pdrv",
351 .id = 1,
352 .dev = {
353 .platform_data = &iclink_mt9v022,
32c1ad9a
GL		 354 },
355};
79206750 356
dddd4a49
SH		 357/* Not connected by default */
358#ifdef PCM970_SDHC_RW_SWITCH
359static int pcm970_sdhc1_get_ro(struct device *dev)
f2cb641f 360{
dddd4a49
SH		 361 return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_SFS6));
362}
363#endif
364
4f163eb8
SH		 365#define SDHC1_GPIO_WP IOMUX_TO_GPIO(MX31_PIN_SFS6)
366#define SDHC1_GPIO_DET IOMUX_TO_GPIO(MX31_PIN_SCK6)
367
dddd4a49
SH		 368static int pcm970_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
369 void *data)
370{
371 int ret;
dddd4a49 372
4f163eb8
SH		 373 ret = gpio_request(SDHC1_GPIO_DET, "sdhc-detect");
374 if (ret)
375 return ret;
376
377 gpio_direction_input(SDHC1_GPIO_DET);
dddd4a49 378
4f163eb8
SH		 379#ifdef PCM970_SDHC_RW_SWITCH
380 ret = gpio_request(SDHC1_GPIO_WP, "sdhc-wp");
381 if (ret)
382 goto err_gpio_free;
383 gpio_direction_input(SDHC1_GPIO_WP);
384#endif
dddd4a49
SH		 385
386 ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_SCK6), detect_irq,
387 IRQF_DISABLED | IRQF_TRIGGER_FALLING,
388 "sdhc-detect", data);
4f163eb8
SH		 389 if (ret)
390 goto err_gpio_free_2;
391
392 return 0;
393
394err_gpio_free_2:
395#ifdef PCM970_SDHC_RW_SWITCH
396 gpio_free(SDHC1_GPIO_WP);
397err_gpio_free:
398#endif
399 gpio_free(SDHC1_GPIO_DET);
400
dddd4a49 401 return ret;
f2cb641f
SH		 402}
403
404static void pcm970_sdhc1_exit(struct device *dev, void *data)
405{
dddd4a49 406 free_irq(IOMUX_TO_IRQ(MX31_PIN_SCK6), data);
4f163eb8
SH		 407 gpio_free(SDHC1_GPIO_DET);
408 gpio_free(SDHC1_GPIO_WP);
f2cb641f
SH		 409}
410
f2cb641f 411static struct imxmmc_platform_data sdhc_pdata = {
dddd4a49
SH		 412#ifdef PCM970_SDHC_RW_SWITCH
413 .get_ro = pcm970_sdhc1_get_ro,
414#endif
f2cb641f
SH		 415 .init = pcm970_sdhc1_init,
416 .exit = pcm970_sdhc1_exit,
417};
418
32c1ad9a
GL		 419struct mx3_camera_pdata camera_pdata = {
420 .dma_dev = &mx3_ipu.dev,
421 .flags = MX3_CAMERA_DATAWIDTH_8 | MX3_CAMERA_DATAWIDTH_10,
422 .mclk_10khz = 2000,
423};
424
425static int __init pcm037_camera_alloc_dma(const size_t buf_size)
426{
427 dma_addr_t dma_handle;
428 void *buf;
429 int dma;
430
431 if (buf_size < 2 * 1024 * 1024)
432 return -EINVAL;
433
434 buf = dma_alloc_coherent(NULL, buf_size, &dma_handle, GFP_KERNEL);
435 if (!buf) {
436 pr_err("%s: cannot allocate camera buffer-memory\n", __func__);
437 return -ENOMEM;
438 }
439
440 memset(buf, 0, buf_size);
441
442 dma = dma_declare_coherent_memory(&mx3_camera.dev,
443 dma_handle, dma_handle, buf_size,
444 DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
445
446 /* The way we call dma_declare_coherent_memory only a malloc can fail */
447 return dma & DMA_MEMORY_MAP ? 0 : -ENOMEM;
448}
449
ce8ffef0
SH		 450static struct platform_device *devices[] __initdata = {
451 &pcm037_flash,
3dad21a9 452 &pcm037_sram_device,
9d00278d
GL		 453 &pcm037_mt9t031,
454 &pcm037_mt9v022,
ce8ffef0
SH		 455};
456
a8df0ee8
GL		 457static struct ipu_platform_data mx3_ipu_data = {
458 .irq_base = MXC_IPU_IRQ_START,
459};
460
461static const struct fb_videomode fb_modedb[] = {
462 {
463 /* 240x320 @ 60 Hz Sharp */
464 .name = "Sharp-LQ035Q7DH06-QVGA",
465 .refresh = 60,
466 .xres = 240,
467 .yres = 320,
468 .pixclock = 185925,
469 .left_margin = 9,
470 .right_margin = 16,
471 .upper_margin = 7,
472 .lower_margin = 9,
473 .hsync_len = 1,
474 .vsync_len = 1,
475 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE |
476 FB_SYNC_CLK_INVERT | FB_SYNC_CLK_IDLE_EN,
477 .vmode = FB_VMODE_NONINTERLACED,
478 .flag = 0,
479 }, {
480 /* 240x320 @ 60 Hz */
481 .name = "TX090",
482 .refresh = 60,
483 .xres = 240,
484 .yres = 320,
485 .pixclock = 38255,
486 .left_margin = 144,
487 .right_margin = 0,
488 .upper_margin = 7,
489 .lower_margin = 40,
490 .hsync_len = 96,
491 .vsync_len = 1,
492 .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH,
493 .vmode = FB_VMODE_NONINTERLACED,
494 .flag = 0,
574ec547
GL		 495 }, {
496 /* 240x320 @ 60 Hz */
497 .name = "CMEL-OLED",
498 .refresh = 60,
499 .xres = 240,
500 .yres = 320,
501 .pixclock = 185925,
502 .left_margin = 9,
503 .right_margin = 16,
504 .upper_margin = 7,
505 .lower_margin = 9,
506 .hsync_len = 1,
507 .vsync_len = 1,
508 .sync = FB_SYNC_OE_ACT_HIGH | FB_SYNC_CLK_INVERT,
509 .vmode = FB_VMODE_NONINTERLACED,
510 .flag = 0,
a8df0ee8
GL		 511 },
512};
513
514static struct mx3fb_platform_data mx3fb_pdata = {
515 .dma_dev = &mx3_ipu.dev,
516 .name = "Sharp-LQ035Q7DH06-QVGA",
517 .mode = fb_modedb,
518 .num_modes = ARRAY_SIZE(fb_modedb),
519};
520
91bf9a25
SH		 521static struct resource pcm970_sja1000_resources[] = {
522 {
f568dd7f
UKK		 523 .start = MX31_CS5_BASE_ADDR,
524 .end = MX31_CS5_BASE_ADDR + 0x100 - 1,
91bf9a25
SH		 525 .flags = IORESOURCE_MEM,
526 }, {
527 .start = IOMUX_TO_IRQ(IOMUX_PIN(48, 105)),
528 .end = IOMUX_TO_IRQ(IOMUX_PIN(48, 105)),
529 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
530 },
531};
532
533struct sja1000_platform_data pcm970_sja1000_platform_data = {
534 .clock = 16000000 / 2,
535 .ocr = 0x40 | 0x18,
536 .cdr = 0x40,
537};
538
539static struct platform_device pcm970_sja1000 = {
540 .name = "sja1000_platform",
541 .dev = {
542 .platform_data = &pcm970_sja1000_platform_data,
543 },
544 .resource = pcm970_sja1000_resources,
545 .num_resources = ARRAY_SIZE(pcm970_sja1000_resources),
546};
547
ee14373c
SH		 548static struct mxc_usbh_platform_data otg_pdata = {
549 .portsc = MXC_EHCI_MODE_ULPI,
550 .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
551};
552
553static struct mxc_usbh_platform_data usbh2_pdata = {
554 .portsc = MXC_EHCI_MODE_ULPI,
555 .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
556};
557
558static struct fsl_usb2_platform_data otg_device_pdata = {
559 .operating_mode = FSL_USB2_DR_DEVICE,
560 .phy_mode = FSL_USB2_PHY_ULPI,
561};
562
563static int otg_mode_host;
564
565static int __init pcm037_otg_mode(char *options)
566{
567 if (!strcmp(options, "host"))
568 otg_mode_host = 1;
569 else if (!strcmp(options, "device"))
570 otg_mode_host = 0;
571 else
572 pr_info("otg_mode neither \"host\" nor \"device\". "
573 "Defaulting to device\n");
574 return 0;
575}
576__setup("otg_mode=", pcm037_otg_mode);
577
ce8ffef0
SH		 578/*
579 * Board specific initialization.
580 */
581static void __init mxc_board_init(void)
582{
4f163eb8 583 int ret;
ee14373c
SH		 584 u32 tmp;
585
586 mxc_iomux_set_gpr(MUX_PGP_UH2, 1);
4f163eb8 587
01ac7d58
SH		 588 mxc_iomux_setup_multiple_pins(pcm037_pins, ARRAY_SIZE(pcm037_pins),
589 "pcm037");
590
ee14373c
SH		 591#define H2_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS \
592 | PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
593
594 mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, H2_PAD_CFG);
595 mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, H2_PAD_CFG);
596 mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, H2_PAD_CFG);
597 mxc_iomux_set_pad(MX31_PIN_USBH2_STP, H2_PAD_CFG);
598 mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, H2_PAD_CFG); /* USBH2_DATA0 */
599 mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, H2_PAD_CFG); /* USBH2_DATA1 */
600 mxc_iomux_set_pad(MX31_PIN_SRXD6, H2_PAD_CFG); /* USBH2_DATA2 */
601 mxc_iomux_set_pad(MX31_PIN_STXD6, H2_PAD_CFG); /* USBH2_DATA3 */
602 mxc_iomux_set_pad(MX31_PIN_SFS3, H2_PAD_CFG); /* USBH2_DATA4 */
603 mxc_iomux_set_pad(MX31_PIN_SCK3, H2_PAD_CFG); /* USBH2_DATA5 */
604 mxc_iomux_set_pad(MX31_PIN_SRXD3, H2_PAD_CFG); /* USBH2_DATA6 */
605 mxc_iomux_set_pad(MX31_PIN_STXD3, H2_PAD_CFG); /* USBH2_DATA7 */
606
574ec547
GL		 607 if (pcm037_variant() == PCM037_EET)
608 mxc_iomux_setup_multiple_pins(pcm037_uart1_pins,
609 ARRAY_SIZE(pcm037_uart1_pins), "pcm037_uart1");
610 else
611 mxc_iomux_setup_multiple_pins(pcm037_uart1_handshake_pins,
612 ARRAY_SIZE(pcm037_uart1_handshake_pins),
613 "pcm037_uart1");
614
ce8ffef0
SH		 615 platform_add_devices(devices, ARRAY_SIZE(devices));
616
5cf09421 617 mxc_register_device(&mxc_uart_device0, &uart_pdata);
13e9f612 618 mxc_register_device(&mxc_uart_device1, &uart_pdata);
5cf09421 619 mxc_register_device(&mxc_uart_device2, &uart_pdata);
d517cab1 620
d517cab1 621 mxc_register_device(&mxc_w1_master_device, NULL);
ba54b958 622
f8e5143b 623 /* LAN9217 IRQ pin */
4f163eb8
SH		 624 ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1), "lan9217-irq");
625 if (ret)
626 pr_warning("could not get LAN irq gpio\n");
627 else {
628 gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1));
629 platform_device_register(&pcm037_eth);
630 }
631
3287abbd 632
32c1ad9a 633 /* I2C adapters and devices */
79206750
SH		 634 i2c_register_board_info(1, pcm037_i2c_devices,
635 ARRAY_SIZE(pcm037_i2c_devices));
636
637 mxc_register_device(&mxc_i2c_device1, &pcm037_i2c_1_data);
32c1ad9a
GL		 638 mxc_register_device(&mxc_i2c_device2, &pcm037_i2c_2_data);
639
3287abbd 640 mxc_register_device(&mxc_nand_device, &pcm037_nand_board_info);
f2cb641f 641 mxc_register_device(&mxcsdhc_device0, &sdhc_pdata);
a8df0ee8
GL		 642 mxc_register_device(&mx3_ipu, &mx3_ipu_data);
643 mxc_register_device(&mx3_fb, &mx3fb_pdata);
32c1ad9a
GL		 644
645 /* CSI */
646 /* Camera power: default - off */
647 ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_CSI_D5), "mt9t031-power");
648 if (!ret)
649 gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_CSI_D5), 1);
650 else
9d00278d 651 iclink_mt9t031.power = NULL;
32c1ad9a
GL		 652
653 if (!pcm037_camera_alloc_dma(4 * 1024 * 1024))
654 mxc_register_device(&mx3_camera, &camera_pdata);
91bf9a25
SH		 655
656 platform_device_register(&pcm970_sja1000);
ee14373c
SH		 657
658#if defined(CONFIG_USB_ULPI)
659 if (otg_mode_host) {
660 otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
661 USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
662
663 mxc_register_device(&mxc_otg_host, &otg_pdata);
664 }
665
666 usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
667 USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
668
669 mxc_register_device(&mxc_usbh2, &usbh2_pdata);
670#endif
671 if (!otg_mode_host)
672 mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata);
673
ce8ffef0
SH		 674}
675
ce8ffef0
SH		 676static void __init pcm037_timer_init(void)
677{
30c730f8 678 mx31_clocks_init(26000000);
ce8ffef0
SH		 679}
680
681struct sys_timer pcm037_timer = {
682 .init = pcm037_timer_init,
683};
684
685MACHINE_START(PCM037, "Phytec Phycore pcm037")
686 /* Maintainer: Pengutronix */
f568dd7f 687 .phys_io = MX31_AIPS1_BASE_ADDR,
321ed164 688 .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
34101237 689 .boot_params = MX3x_PHYS_OFFSET + 0x100,
cd4a05f9 690 .map_io = mx31_map_io,
c5aa0ad0 691 .init_irq = mx31_init_irq,
ce8ffef0
SH		 692 .init_machine = mxc_board_init,
693 .timer = &pcm037_timer,
694MACHINE_END
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