[mirror_ubuntu-zesty-kernel.git] / arch / arm / mach-mxs / timer.c

/*
 *  Copyright (C) 2000-2001 Deep Blue Solutions
 *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
 *  Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com)
 *  Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
 *  Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 * MA 02110-1301, USA.
 */

#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/clockchips.h>
#include <linux/clk.h>
#include <linux/of.h>
#include <linux/of_irq.h>

#include <asm/mach/time.h>
#include <asm/sched_clock.h>
#include <mach/mxs.h>
#include <mach/common.h>

/*
 * There are 2 versions of the timrot on Freescale MXS-based SoCs.
 * The v1 on MX23 only gets 16 bits counter, while v2 on MX28
 * extends the counter to 32 bits.
 *
 * The implementation uses two timers, one for clock_event and
 * another for clocksource. MX28 uses timrot 0 and 1, while MX23
 * uses 0 and 2.
 */

#define MX23_TIMROT_VERSION_OFFSET	0x0a0
#define MX28_TIMROT_VERSION_OFFSET	0x120
#define BP_TIMROT_MAJOR_VERSION		24
#define BV_TIMROT_VERSION_1		0x01
#define BV_TIMROT_VERSION_2		0x02
#define timrot_is_v1()	(timrot_major_version == BV_TIMROT_VERSION_1)

/*
 * There are 4 registers for each timrotv2 instance, and 2 registers
 * for each timrotv1. So address step 0x40 in macros below strides
 * one instance of timrotv2 while two instances of timrotv1.
 *
 * As the result, HW_TIMROT_XXXn(1) defines the address of timrot1
 * on MX28 while timrot2 on MX23.
 */
/* common between v1 and v2 */
#define HW_TIMROT_ROTCTRL		0x00
#define HW_TIMROT_TIMCTRLn(n)		(0x20 + (n) * 0x40)
/* v1 only */
#define HW_TIMROT_TIMCOUNTn(n)		(0x30 + (n) * 0x40)
/* v2 only */
#define HW_TIMROT_RUNNING_COUNTn(n)	(0x30 + (n) * 0x40)
#define HW_TIMROT_FIXED_COUNTn(n)	(0x40 + (n) * 0x40)

#define BM_TIMROT_TIMCTRLn_RELOAD	(1 << 6)
#define BM_TIMROT_TIMCTRLn_UPDATE	(1 << 7)
#define BM_TIMROT_TIMCTRLn_IRQ_EN	(1 << 14)
#define BM_TIMROT_TIMCTRLn_IRQ		(1 << 15)
#define BP_TIMROT_TIMCTRLn_SELECT	0
#define BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL		0x8
#define BV_TIMROTv2_TIMCTRLn_SELECT__32KHZ_XTAL		0xb
#define BV_TIMROTv2_TIMCTRLn_SELECT__TICK_ALWAYS	0xf

static struct clock_event_device mxs_clockevent_device;
static enum clock_event_mode mxs_clockevent_mode = CLOCK_EVT_MODE_UNUSED;

static void __iomem *mxs_timrot_base = MXS_IO_ADDRESS(MXS_TIMROT_BASE_ADDR);
static u32 timrot_major_version;

static inline void timrot_irq_disable(void)
{
	__mxs_clrl(BM_TIMROT_TIMCTRLn_IRQ_EN,
			mxs_timrot_base + HW_TIMROT_TIMCTRLn(0));
}

static inline void timrot_irq_enable(void)
{
	__mxs_setl(BM_TIMROT_TIMCTRLn_IRQ_EN,
			mxs_timrot_base + HW_TIMROT_TIMCTRLn(0));
}

static void timrot_irq_acknowledge(void)
{
	__mxs_clrl(BM_TIMROT_TIMCTRLn_IRQ,
			mxs_timrot_base + HW_TIMROT_TIMCTRLn(0));
}

static cycle_t timrotv1_get_cycles(struct clocksource *cs)
{
	return ~((__raw_readl(mxs_timrot_base + HW_TIMROT_TIMCOUNTn(1))
			& 0xffff0000) >> 16);
}

static int timrotv1_set_next_event(unsigned long evt,
					struct clock_event_device *dev)
{
	/* timrot decrements the count */
	__raw_writel(evt, mxs_timrot_base + HW_TIMROT_TIMCOUNTn(0));

	return 0;
}

static int timrotv2_set_next_event(unsigned long evt,
					struct clock_event_device *dev)
{
	/* timrot decrements the count */
	__raw_writel(evt, mxs_timrot_base + HW_TIMROT_FIXED_COUNTn(0));

	return 0;
}

static irqreturn_t mxs_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evt = dev_id;

	timrot_irq_acknowledge();
	evt->event_handler(evt);

	return IRQ_HANDLED;
}

static struct irqaction mxs_timer_irq = {
	.name		= "MXS Timer Tick",
	.dev_id		= &mxs_clockevent_device,
	.flags		= IRQF_TIMER | IRQF_IRQPOLL,
	.handler	= mxs_timer_interrupt,
};

#ifdef DEBUG
static const char *clock_event_mode_label[] const = {
	[CLOCK_EVT_MODE_PERIODIC] = "CLOCK_EVT_MODE_PERIODIC",
	[CLOCK_EVT_MODE_ONESHOT]  = "CLOCK_EVT_MODE_ONESHOT",
	[CLOCK_EVT_MODE_SHUTDOWN] = "CLOCK_EVT_MODE_SHUTDOWN",
	[CLOCK_EVT_MODE_UNUSED]   = "CLOCK_EVT_MODE_UNUSED"
};
#endif /* DEBUG */

static void mxs_set_mode(enum clock_event_mode mode,
				struct clock_event_device *evt)
{
	/* Disable interrupt in timer module */
	timrot_irq_disable();

	if (mode != mxs_clockevent_mode) {
		/* Set event time into the furthest future */
		if (timrot_is_v1())
			__raw_writel(0xffff,
				mxs_timrot_base + HW_TIMROT_TIMCOUNTn(1));
		else
			__raw_writel(0xffffffff,
				mxs_timrot_base + HW_TIMROT_FIXED_COUNTn(1));

		/* Clear pending interrupt */
		timrot_irq_acknowledge();
	}

#ifdef DEBUG
	pr_info("%s: changing mode from %s to %s\n", __func__,
		clock_event_mode_label[mxs_clockevent_mode],
		clock_event_mode_label[mode]);
#endif /* DEBUG */

	/* Remember timer mode */
	mxs_clockevent_mode = mode;

	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		pr_err("%s: Periodic mode is not implemented\n", __func__);
		break;
	case CLOCK_EVT_MODE_ONESHOT:
		timrot_irq_enable();
		break;
	case CLOCK_EVT_MODE_SHUTDOWN:
	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_RESUME:
		/* Left event sources disabled, no more interrupts appear */
		break;
	}
}

static struct clock_event_device mxs_clockevent_device = {
	.name		= "mxs_timrot",
	.features	= CLOCK_EVT_FEAT_ONESHOT,
	.set_mode	= mxs_set_mode,
	.set_next_event	= timrotv2_set_next_event,
	.rating		= 200,
};

static int __init mxs_clockevent_init(struct clk *timer_clk)
{
	if (timrot_is_v1())
		mxs_clockevent_device.set_next_event = timrotv1_set_next_event;
	mxs_clockevent_device.cpumask = cpumask_of(0);
	clockevents_config_and_register(&mxs_clockevent_device,
					clk_get_rate(timer_clk),
					timrot_is_v1() ? 0xf : 0x2,
					timrot_is_v1() ? 0xfffe : 0xfffffffe);

	return 0;
}

static struct clocksource clocksource_mxs = {
	.name		= "mxs_timer",
	.rating		= 200,
	.read		= timrotv1_get_cycles,
	.mask		= CLOCKSOURCE_MASK(16),
	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
};

static u32 notrace mxs_read_sched_clock_v2(void)
{
	return ~readl_relaxed(mxs_timrot_base + HW_TIMROT_RUNNING_COUNTn(1));
}

static int __init mxs_clocksource_init(struct clk *timer_clk)
{
	unsigned int c = clk_get_rate(timer_clk);

	if (timrot_is_v1())
		clocksource_register_hz(&clocksource_mxs, c);
	else {
		clocksource_mmio_init(mxs_timrot_base + HW_TIMROT_RUNNING_COUNTn(1),
			"mxs_timer", c, 200, 32, clocksource_mmio_readl_down);
		setup_sched_clock(mxs_read_sched_clock_v2, 32, c);
	}

	return 0;
}

static void __init mxs_timer_init(struct device_node *np)
{
	struct clk *timer_clk;
	int irq;

	timer_clk = clk_get_sys("timrot", NULL);
	if (IS_ERR(timer_clk)) {
		pr_err("%s: failed to get clk\n", __func__);
		return;
	}

	clk_prepare_enable(timer_clk);

	/*
	 * Initialize timers to a known state
	 */
	mxs_reset_block(mxs_timrot_base + HW_TIMROT_ROTCTRL);

	/* get timrot version */
	timrot_major_version = __raw_readl(mxs_timrot_base +
				(cpu_is_mx23() ? MX23_TIMROT_VERSION_OFFSET :
						MX28_TIMROT_VERSION_OFFSET));
	timrot_major_version >>= BP_TIMROT_MAJOR_VERSION;

	/* one for clock_event */
	__raw_writel((timrot_is_v1() ?
			BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL :
			BV_TIMROTv2_TIMCTRLn_SELECT__TICK_ALWAYS) |
			BM_TIMROT_TIMCTRLn_UPDATE |
			BM_TIMROT_TIMCTRLn_IRQ_EN,
			mxs_timrot_base + HW_TIMROT_TIMCTRLn(0));

	/* another for clocksource */
	__raw_writel((timrot_is_v1() ?
			BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL :
			BV_TIMROTv2_TIMCTRLn_SELECT__TICK_ALWAYS) |
			BM_TIMROT_TIMCTRLn_RELOAD,
			mxs_timrot_base + HW_TIMROT_TIMCTRLn(1));

	/* set clocksource timer fixed count to the maximum */
	if (timrot_is_v1())
		__raw_writel(0xffff,
			mxs_timrot_base + HW_TIMROT_TIMCOUNTn(1));
	else
		__raw_writel(0xffffffff,
			mxs_timrot_base + HW_TIMROT_FIXED_COUNTn(1));

	/* init and register the timer to the framework */
	mxs_clocksource_init(timer_clk);
	mxs_clockevent_init(timer_clk);

	/* Make irqs happen */
	irq = irq_of_parse_and_map(np, 0);
	setup_irq(irq, &mxs_timer_irq);
}
CLOCKSOURCE_OF_DECLARE(mxs, "fsl,timrot", mxs_timer_init)
Commit	Line	Data
4e472096 SG	1	/*
	2	* Copyright (C) 2000-2001 Deep Blue Solutions
	3	* Copyright (C) 2002 Shane Nay (shane@minirl.com)
	4	* Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com)
	5	* Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
	6	* Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License
	10	* as published by the Free Software Foundation; either version 2
	11	* of the License, or (at your option) any later version.
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
	20	* MA 02110-1301, USA.
	21	*/
	22
39d1367e	23	#include <linux/err.h>
4e472096 SG	24	#include <linux/interrupt.h>
	25	#include <linux/irq.h>
	26	#include <linux/clockchips.h>
	27	#include <linux/clk.h>
eeca6e60 SG	28	#include <linux/of.h>
eeca6e60 SG	29	#include <linux/of_irq.h>
4e472096 SG	30
4e472096 SG	31	#include <asm/mach/time.h>
67948ada	32	#include <asm/sched_clock.h>
4e472096 SG	33	#include <mach/mxs.h>
	34	#include <mach/common.h>
	35
	36	/*
	37	* There are 2 versions of the timrot on Freescale MXS-based SoCs.
	38	* The v1 on MX23 only gets 16 bits counter, while v2 on MX28
	39	* extends the counter to 32 bits.
	40	*
	41	* The implementation uses two timers, one for clock_event and
	42	* another for clocksource. MX28 uses timrot 0 and 1, while MX23
	43	* uses 0 and 2.
	44	*/
	45
	46	#define MX23_TIMROT_VERSION_OFFSET 0x0a0
	47	#define MX28_TIMROT_VERSION_OFFSET 0x120
	48	#define BP_TIMROT_MAJOR_VERSION 24
	49	#define BV_TIMROT_VERSION_1 0x01
	50	#define BV_TIMROT_VERSION_2 0x02
	51	#define timrot_is_v1() (timrot_major_version == BV_TIMROT_VERSION_1)
	52
	53	/*
	54	* There are 4 registers for each timrotv2 instance, and 2 registers
	55	* for each timrotv1. So address step 0x40 in macros below strides
	56	* one instance of timrotv2 while two instances of timrotv1.
	57	*
	58	* As the result, HW_TIMROT_XXXn(1) defines the address of timrot1
	59	* on MX28 while timrot2 on MX23.
	60	*/
	61	/* common between v1 and v2 */
	62	#define HW_TIMROT_ROTCTRL 0x00
	63	#define HW_TIMROT_TIMCTRLn(n) (0x20 + (n) * 0x40)
	64	/* v1 only */
	65	#define HW_TIMROT_TIMCOUNTn(n) (0x30 + (n) * 0x40)
	66	/* v2 only */
	67	#define HW_TIMROT_RUNNING_COUNTn(n) (0x30 + (n) * 0x40)
	68	#define HW_TIMROT_FIXED_COUNTn(n) (0x40 + (n) * 0x40)
	69
	70	#define BM_TIMROT_TIMCTRLn_RELOAD (1 << 6)
	71	#define BM_TIMROT_TIMCTRLn_UPDATE (1 << 7)
	72	#define BM_TIMROT_TIMCTRLn_IRQ_EN (1 << 14)
	73	#define BM_TIMROT_TIMCTRLn_IRQ (1 << 15)
	74	#define BP_TIMROT_TIMCTRLn_SELECT 0
2fb318ff TH	75	#define BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL 0x8
	76	#define BV_TIMROTv2_TIMCTRLn_SELECT__32KHZ_XTAL 0xb
	77	#define BV_TIMROTv2_TIMCTRLn_SELECT__TICK_ALWAYS 0xf
4e472096 SG	78
	79	static struct clock_event_device mxs_clockevent_device;
	80	static enum clock_event_mode mxs_clockevent_mode = CLOCK_EVT_MODE_UNUSED;
	81
	82	static void __iomem *mxs_timrot_base = MXS_IO_ADDRESS(MXS_TIMROT_BASE_ADDR);
	83	static u32 timrot_major_version;
	84
	85	static inline void timrot_irq_disable(void)
	86	{
	87	__mxs_clrl(BM_TIMROT_TIMCTRLn_IRQ_EN,
	88	mxs_timrot_base + HW_TIMROT_TIMCTRLn(0));
	89	}
	90
	91	static inline void timrot_irq_enable(void)
	92	{
	93	__mxs_setl(BM_TIMROT_TIMCTRLn_IRQ_EN,
	94	mxs_timrot_base + HW_TIMROT_TIMCTRLn(0));
	95	}
	96
	97	static void timrot_irq_acknowledge(void)
	98	{
	99	__mxs_clrl(BM_TIMROT_TIMCTRLn_IRQ,
	100	mxs_timrot_base + HW_TIMROT_TIMCTRLn(0));
	101	}
	102
	103	static cycle_t timrotv1_get_cycles(struct clocksource *cs)
	104	{
	105	return ~((__raw_readl(mxs_timrot_base + HW_TIMROT_TIMCOUNTn(1))
	106	& 0xffff0000) >> 16);
	107	}
	108
4e472096 SG	109	static int timrotv1_set_next_event(unsigned long evt,
	110	struct clock_event_device *dev)
	111	{
	112	/* timrot decrements the count */
	113	__raw_writel(evt, mxs_timrot_base + HW_TIMROT_TIMCOUNTn(0));
	114
	115	return 0;
	116	}
	117
	118	static int timrotv2_set_next_event(unsigned long evt,
	119	struct clock_event_device *dev)
	120	{
	121	/* timrot decrements the count */
	122	__raw_writel(evt, mxs_timrot_base + HW_TIMROT_FIXED_COUNTn(0));
	123
	124	return 0;
	125	}
	126
	127	static irqreturn_t mxs_timer_interrupt(int irq, void *dev_id)
	128	{
	129	struct clock_event_device *evt = dev_id;
	130
	131	timrot_irq_acknowledge();
	132	evt->event_handler(evt);
	133
	134	return IRQ_HANDLED;
	135	}
	136
	137	static struct irqaction mxs_timer_irq = {
	138	.name = "MXS Timer Tick",
	139	.dev_id = &mxs_clockevent_device,
	140	.flags = IRQF_TIMER \| IRQF_IRQPOLL,
	141	.handler = mxs_timer_interrupt,
	142	};
	143
	144	#ifdef DEBUG
	145	static const char *clock_event_mode_label[] const = {
	146	[CLOCK_EVT_MODE_PERIODIC] = "CLOCK_EVT_MODE_PERIODIC",
	147	[CLOCK_EVT_MODE_ONESHOT] = "CLOCK_EVT_MODE_ONESHOT",
	148	[CLOCK_EVT_MODE_SHUTDOWN] = "CLOCK_EVT_MODE_SHUTDOWN",
	149	[CLOCK_EVT_MODE_UNUSED] = "CLOCK_EVT_MODE_UNUSED"
	150	};
	151	#endif /* DEBUG */
	152
	153	static void mxs_set_mode(enum clock_event_mode mode,
	154	struct clock_event_device *evt)
	155	{
	156	/* Disable interrupt in timer module */
	157	timrot_irq_disable();
	158
	159	if (mode != mxs_clockevent_mode) {
	160	/* Set event time into the furthest future */
	161	if (timrot_is_v1())
	162	__raw_writel(0xffff,
	163	mxs_timrot_base + HW_TIMROT_TIMCOUNTn(1));
	164	else
	165	__raw_writel(0xffffffff,
	166	mxs_timrot_base + HW_TIMROT_FIXED_COUNTn(1));
	167
	168	/* Clear pending interrupt */
	169	timrot_irq_acknowledge();
	170	}
	171
	172	#ifdef DEBUG
173	pr_info("%s: changing mode from %s to %s\n", __func__,
174	clock_event_mode_label[mxs_clockevent_mode],
175	clock_event_mode_label[mode]);
176	#endif /* DEBUG */
177
178	/* Remember timer mode */
179	mxs_clockevent_mode = mode;
180
181	switch (mode) {
182	case CLOCK_EVT_MODE_PERIODIC:
183	pr_err("%s: Periodic mode is not implemented\n", __func__);
184	break;
185	case CLOCK_EVT_MODE_ONESHOT:
186	timrot_irq_enable();
187	break;
188	case CLOCK_EVT_MODE_SHUTDOWN:
189	case CLOCK_EVT_MODE_UNUSED:
190	case CLOCK_EVT_MODE_RESUME:
191	/* Left event sources disabled, no more interrupts appear */
192	break;
193	}
194	}
195
196	static struct clock_event_device mxs_clockevent_device = {
197	.name = "mxs_timrot",
198	.features = CLOCK_EVT_FEAT_ONESHOT,
4e472096 SG	199	.set_mode = mxs_set_mode,
	200	.set_next_event = timrotv2_set_next_event,
	201	.rating = 200,
	202	};
	203
	204	static int __init mxs_clockevent_init(struct clk *timer_clk)
	205	{
838a2ae8	206	if (timrot_is_v1())
4e472096	207	mxs_clockevent_device.set_next_event = timrotv1_set_next_event;
838a2ae8 SG	208	mxs_clockevent_device.cpumask = cpumask_of(0);
838a2ae8 SG	209	clockevents_config_and_register(&mxs_clockevent_device,
93044fa1 TH	210	clk_get_rate(timer_clk),
93044fa1 TH	211	timrot_is_v1() ? 0xf : 0x2,
838a2ae8	212	timrot_is_v1() ? 0xfffe : 0xfffffffe);
4e472096 SG	213
	214	return 0;
	215	}
	216
	217	static struct clocksource clocksource_mxs = {
	218	.name = "mxs_timer",
	219	.rating = 200,
5c61ddcf RK	220	.read = timrotv1_get_cycles,
5c61ddcf RK	221	.mask = CLOCKSOURCE_MASK(16),
4e472096 SG	222	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	223	};
	224
67948ada SM	225	static u32 notrace mxs_read_sched_clock_v2(void)
	226	{
	227	return ~readl_relaxed(mxs_timrot_base + HW_TIMROT_RUNNING_COUNTn(1));
	228	}
	229
4e472096 SG	230	static int __init mxs_clocksource_init(struct clk *timer_clk)
	231	{
	232	unsigned int c = clk_get_rate(timer_clk);
	233
5c61ddcf RK	234	if (timrot_is_v1())
5c61ddcf RK	235	clocksource_register_hz(&clocksource_mxs, c);
67948ada	236	else {
5c61ddcf RK	237	clocksource_mmio_init(mxs_timrot_base + HW_TIMROT_RUNNING_COUNTn(1),
5c61ddcf RK	238	"mxs_timer", c, 200, 32, clocksource_mmio_readl_down);
67948ada SM	239	setup_sched_clock(mxs_read_sched_clock_v2, 32, c);
67948ada SM	240	}
4e472096 SG	241
	242	return 0;
	243	}
	244
633ef4c7	245	static void __init mxs_timer_init(struct device_node *np)
4e472096	246	{
50260924	247	struct clk *timer_clk;
eeca6e60 SG	248	int irq;
eeca6e60 SG	249
50260924 SG	250	timer_clk = clk_get_sys("timrot", NULL);
	251	if (IS_ERR(timer_clk)) {
	252	pr_err("%s: failed to get clk\n", __func__);
	253	return;
39d1367e SG	254	}
39d1367e SG	255
ae68f7af	256	clk_prepare_enable(timer_clk);
4e472096 SG	257
	258	/*
	259	* Initialize timers to a known state
	260	*/
	261	mxs_reset_block(mxs_timrot_base + HW_TIMROT_ROTCTRL);
	262
	263	/* get timrot version */
	264	timrot_major_version = __raw_readl(mxs_timrot_base +
	265	(cpu_is_mx23() ? MX23_TIMROT_VERSION_OFFSET :
	266	MX28_TIMROT_VERSION_OFFSET));
	267	timrot_major_version >>= BP_TIMROT_MAJOR_VERSION;
	268
	269	/* one for clock_event */
	270	__raw_writel((timrot_is_v1() ?
	271	BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL :
2fb318ff	272	BV_TIMROTv2_TIMCTRLn_SELECT__TICK_ALWAYS) \|
4e472096 SG	273	BM_TIMROT_TIMCTRLn_UPDATE \|
	274	BM_TIMROT_TIMCTRLn_IRQ_EN,
	275	mxs_timrot_base + HW_TIMROT_TIMCTRLn(0));
	276
	277	/* another for clocksource */
	278	__raw_writel((timrot_is_v1() ?
	279	BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL :
2fb318ff	280	BV_TIMROTv2_TIMCTRLn_SELECT__TICK_ALWAYS) \|
4e472096 SG	281	BM_TIMROT_TIMCTRLn_RELOAD,
	282	mxs_timrot_base + HW_TIMROT_TIMCTRLn(1));
	283
	284	/* set clocksource timer fixed count to the maximum */
	285	if (timrot_is_v1())
	286	__raw_writel(0xffff,
	287	mxs_timrot_base + HW_TIMROT_TIMCOUNTn(1));
	288	else
	289	__raw_writel(0xffffffff,
	290	mxs_timrot_base + HW_TIMROT_FIXED_COUNTn(1));
	291
	292	/* init and register the timer to the framework */
	293	mxs_clocksource_init(timer_clk);
	294	mxs_clockevent_init(timer_clk);
	295
	296	/* Make irqs happen */
eeca6e60	297	irq = irq_of_parse_and_map(np, 0);
4e472096 SG	298	setup_irq(irq, &mxs_timer_irq);
4e472096 SG	299	}
633ef4c7	300	CLOCKSOURCE_OF_DECLARE(mxs, "fsl,timrot", mxs_timer_init)