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45051539 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
af614ba0 SH |
2 | /* |
3 | * arch/arm/mach-netx/nxdb500.c | |
4 | * | |
5 | * Copyright (c) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix | |
af614ba0 SH |
6 | */ |
7 | ||
8 | #include <linux/dma-mapping.h> | |
9 | #include <linux/init.h> | |
10 | #include <linux/interrupt.h> | |
11 | #include <linux/mtd/plat-ram.h> | |
12 | #include <linux/platform_device.h> | |
13 | #include <linux/amba/bus.h> | |
14 | #include <linux/amba/clcd.h> | |
15 | ||
a09e64fb | 16 | #include <mach/hardware.h> |
af614ba0 SH |
17 | #include <asm/mach-types.h> |
18 | #include <asm/mach/arch.h> | |
a09e64fb | 19 | #include <mach/netx-regs.h> |
2960ed34 | 20 | #include <linux/platform_data/eth-netx.h> |
af614ba0 SH |
21 | |
22 | #include "generic.h" | |
23 | #include "fb.h" | |
24 | ||
25 | static struct clcd_panel qvga = { | |
26 | .mode = { | |
27 | .name = "QVGA", | |
28 | .refresh = 60, | |
29 | .xres = 240, | |
30 | .yres = 320, | |
31 | .pixclock = 187617, | |
32 | .left_margin = 6, | |
33 | .right_margin = 26, | |
34 | .upper_margin = 0, | |
35 | .lower_margin = 6, | |
36 | .hsync_len = 6, | |
37 | .vsync_len = 1, | |
38 | .sync = 0, | |
39 | .vmode = FB_VMODE_NONINTERLACED, | |
40 | }, | |
41 | .width = -1, | |
42 | .height = -1, | |
43 | .tim2 = 16, | |
44 | .cntl = CNTL_LCDTFT | CNTL_BGR, | |
45 | .bpp = 16, | |
46 | .grayscale = 0, | |
47 | }; | |
48 | ||
49 | static inline int nxdb500_check(struct clcd_fb *fb, struct fb_var_screeninfo *var) | |
50 | { | |
51 | var->green.length = 5; | |
52 | var->green.msb_right = 0; | |
53 | ||
54 | return clcdfb_check(fb, var); | |
55 | } | |
56 | ||
57 | static int nxdb500_clcd_setup(struct clcd_fb *fb) | |
58 | { | |
59 | unsigned int val; | |
60 | ||
61 | fb->fb.var.green.length = 5; | |
62 | fb->fb.var.green.msb_right = 0; | |
63 | ||
64 | /* enable asic control */ | |
65 | val = readl(NETX_SYSTEM_IOC_ACCESS_KEY); | |
66 | writel(val, NETX_SYSTEM_IOC_ACCESS_KEY); | |
67 | ||
68 | writel(3, NETX_SYSTEM_IOC_CR); | |
69 | ||
70 | val = readl(NETX_PIO_OUTPIO); | |
71 | writel(val | 1, NETX_PIO_OUTPIO); | |
72 | ||
73 | val = readl(NETX_PIO_OEPIO); | |
74 | writel(val | 1, NETX_PIO_OEPIO); | |
75 | return netx_clcd_setup(fb); | |
76 | } | |
77 | ||
78 | static struct clcd_board clcd_data = { | |
79 | .name = "netX", | |
80 | .check = nxdb500_check, | |
81 | .decode = clcdfb_decode, | |
82 | .enable = netx_clcd_enable, | |
83 | .setup = nxdb500_clcd_setup, | |
84 | .mmap = netx_clcd_mmap, | |
85 | .remove = netx_clcd_remove, | |
86 | }; | |
87 | ||
88 | static struct netxeth_platform_data eth0_platform_data = { | |
89 | .xcno = 0, | |
90 | }; | |
91 | ||
92 | static struct platform_device netx_eth0_device = { | |
93 | .name = "netx-eth", | |
94 | .id = 0, | |
95 | .num_resources = 0, | |
96 | .resource = NULL, | |
97 | .dev = { | |
98 | .platform_data = ð0_platform_data, | |
99 | } | |
100 | }; | |
101 | ||
102 | static struct netxeth_platform_data eth1_platform_data = { | |
103 | .xcno = 1, | |
104 | }; | |
105 | ||
106 | static struct platform_device netx_eth1_device = { | |
107 | .name = "netx-eth", | |
108 | .id = 1, | |
109 | .num_resources = 0, | |
110 | .resource = NULL, | |
111 | .dev = { | |
112 | .platform_data = ð1_platform_data, | |
113 | } | |
114 | }; | |
115 | ||
116 | static struct resource netx_uart0_resources[] = { | |
117 | [0] = { | |
118 | .start = 0x00100A00, | |
119 | .end = 0x00100A3F, | |
120 | .flags = IORESOURCE_MEM, | |
121 | }, | |
122 | [1] = { | |
123 | .start = (NETX_IRQ_UART0), | |
124 | .end = (NETX_IRQ_UART0), | |
125 | .flags = IORESOURCE_IRQ, | |
126 | }, | |
127 | }; | |
128 | ||
129 | static struct platform_device netx_uart0_device = { | |
130 | .name = "netx-uart", | |
131 | .id = 0, | |
132 | .num_resources = ARRAY_SIZE(netx_uart0_resources), | |
133 | .resource = netx_uart0_resources, | |
134 | }; | |
135 | ||
136 | static struct resource netx_uart1_resources[] = { | |
137 | [0] = { | |
138 | .start = 0x00100A40, | |
139 | .end = 0x00100A7F, | |
140 | .flags = IORESOURCE_MEM, | |
141 | }, | |
142 | [1] = { | |
143 | .start = (NETX_IRQ_UART1), | |
144 | .end = (NETX_IRQ_UART1), | |
145 | .flags = IORESOURCE_IRQ, | |
146 | }, | |
147 | }; | |
148 | ||
149 | static struct platform_device netx_uart1_device = { | |
150 | .name = "netx-uart", | |
151 | .id = 1, | |
152 | .num_resources = ARRAY_SIZE(netx_uart1_resources), | |
153 | .resource = netx_uart1_resources, | |
154 | }; | |
155 | ||
156 | static struct resource netx_uart2_resources[] = { | |
157 | [0] = { | |
158 | .start = 0x00100A80, | |
159 | .end = 0x00100ABF, | |
160 | .flags = IORESOURCE_MEM, | |
161 | }, | |
162 | [1] = { | |
163 | .start = (NETX_IRQ_UART2), | |
164 | .end = (NETX_IRQ_UART2), | |
165 | .flags = IORESOURCE_IRQ, | |
166 | }, | |
167 | }; | |
168 | ||
169 | static struct platform_device netx_uart2_device = { | |
170 | .name = "netx-uart", | |
171 | .id = 2, | |
172 | .num_resources = ARRAY_SIZE(netx_uart2_resources), | |
173 | .resource = netx_uart2_resources, | |
174 | }; | |
175 | ||
176 | static struct platform_device *devices[] __initdata = { | |
177 | &netx_eth0_device, | |
178 | &netx_eth1_device, | |
179 | &netx_uart0_device, | |
180 | &netx_uart1_device, | |
181 | &netx_uart2_device, | |
182 | }; | |
183 | ||
184 | static void __init nxdb500_init(void) | |
185 | { | |
186 | netx_fb_init(&clcd_data, &qvga); | |
187 | platform_add_devices(devices, ARRAY_SIZE(devices)); | |
188 | } | |
189 | ||
190 | MACHINE_START(NXDB500, "Hilscher nxdb500") | |
b11fd42c | 191 | .atag_offset = 0x100, |
af614ba0 SH |
192 | .map_io = netx_map_io, |
193 | .init_irq = netx_init_irq, | |
6bb27d73 | 194 | .init_time = netx_timer_init, |
af614ba0 | 195 | .init_machine = nxdb500_init, |
8fb06b12 | 196 | .restart = netx_restart, |
af614ba0 | 197 | MACHINE_END |