[mirror_ubuntu-jammy-kernel.git] / arch / arm / mach-omap1 / board-h3.c

/*
 * linux/arch/arm/mach-omap1/board-h3.c
 *
 * This file contains OMAP1710 H3 specific code.
 *
 * Copyright (C) 2004 Texas Instruments, Inc.
 * Copyright (C) 2002 MontaVista Software, Inc.
 * Copyright (C) 2001 RidgeRun, Inc.
 * Author: RidgeRun, Inc.
 *         Greg Lonnon (glonnon@ridgerun.com) or info@ridgerun.com
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/types.h>
#include <linux/init.h>
#include <linux/major.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/errno.h>
#include <linux/workqueue.h>
#include <linux/i2c.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/partitions.h>
#include <linux/input.h>
#include <linux/spi/spi.h>
#include <linux/i2c/tps65010.h>

#include <asm/setup.h>
#include <asm/page.h>
#include <mach/hardware.h>
#include <asm/gpio.h>

#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/flash.h>
#include <asm/mach/map.h>

#include <mach/irqs.h>
#include <plat/mux.h>
#include <plat/tc.h>
#include <plat/nand.h>
#include <plat/usb.h>
#include <plat/keypad.h>
#include <plat/dma.h>
#include <plat/common.h>

#include "board-h3.h"

/* In OMAP1710 H3 the Ethernet is directly connected to CS1 */
#define OMAP1710_ETHR_START		0x04000300

#define H3_TS_GPIO	48

static int h3_keymap[] = {
	KEY(0, 0, KEY_LEFT),
	KEY(0, 1, KEY_RIGHT),
	KEY(0, 2, KEY_3),
	KEY(0, 3, KEY_F10),
	KEY(0, 4, KEY_F5),
	KEY(0, 5, KEY_9),
	KEY(1, 0, KEY_DOWN),
	KEY(1, 1, KEY_UP),
	KEY(1, 2, KEY_2),
	KEY(1, 3, KEY_F9),
	KEY(1, 4, KEY_F7),
	KEY(1, 5, KEY_0),
	KEY(2, 0, KEY_ENTER),
	KEY(2, 1, KEY_6),
	KEY(2, 2, KEY_1),
	KEY(2, 3, KEY_F2),
	KEY(2, 4, KEY_F6),
	KEY(2, 5, KEY_HOME),
	KEY(3, 0, KEY_8),
	KEY(3, 1, KEY_5),
	KEY(3, 2, KEY_F12),
	KEY(3, 3, KEY_F3),
	KEY(3, 4, KEY_F8),
	KEY(3, 5, KEY_END),
	KEY(4, 0, KEY_7),
	KEY(4, 1, KEY_4),
	KEY(4, 2, KEY_F11),
	KEY(4, 3, KEY_F1),
	KEY(4, 4, KEY_F4),
	KEY(4, 5, KEY_ESC),
	KEY(5, 0, KEY_F13),
	KEY(5, 1, KEY_F14),
	KEY(5, 2, KEY_F15),
	KEY(5, 3, KEY_F16),
	KEY(5, 4, KEY_SLEEP),
	0
};


static struct mtd_partition nor_partitions[] = {
	/* bootloader (U-Boot, etc) in first sector */
	{
	      .name		= "bootloader",
	      .offset		= 0,
	      .size		= SZ_128K,
	      .mask_flags	= MTD_WRITEABLE, /* force read-only */
	},
	/* bootloader params in the next sector */
	{
	      .name		= "params",
	      .offset		= MTDPART_OFS_APPEND,
	      .size		= SZ_128K,
	      .mask_flags	= 0,
	},
	/* kernel */
	{
	      .name		= "kernel",
	      .offset		= MTDPART_OFS_APPEND,
	      .size		= SZ_2M,
	      .mask_flags	= 0
	},
	/* file system */
	{
	      .name		= "filesystem",
	      .offset		= MTDPART_OFS_APPEND,
	      .size		= MTDPART_SIZ_FULL,
	      .mask_flags	= 0
	}
};

static struct flash_platform_data nor_data = {
	.map_name	= "cfi_probe",
	.width		= 2,
	.parts		= nor_partitions,
	.nr_parts	= ARRAY_SIZE(nor_partitions),
};

static struct resource nor_resource = {
	/* This is on CS3, wherever it's mapped */
	.flags		= IORESOURCE_MEM,
};

static struct platform_device nor_device = {
	.name		= "omapflash",
	.id		= 0,
	.dev		= {
		.platform_data	= &nor_data,
	},
	.num_resources	= 1,
	.resource	= &nor_resource,
};

static struct mtd_partition nand_partitions[] = {
#if 0
	/* REVISIT: enable these partitions if you make NAND BOOT work */
	{
		.name		= "xloader",
		.offset		= 0,
		.size		= 64 * 1024,
		.mask_flags	= MTD_WRITEABLE,	/* force read-only */
	},
	{
		.name		= "bootloader",
		.offset		= MTDPART_OFS_APPEND,
		.size		= 256 * 1024,
		.mask_flags	= MTD_WRITEABLE,	/* force read-only */
	},
	{
		.name		= "params",
		.offset		= MTDPART_OFS_APPEND,
		.size		= 192 * 1024,
	},
	{
		.name		= "kernel",
		.offset		= MTDPART_OFS_APPEND,
		.size		= 2 * SZ_1M,
	},
#endif
	{
		.name		= "filesystem",
		.size		= MTDPART_SIZ_FULL,
		.offset		= MTDPART_OFS_APPEND,
	},
};

/* dip switches control NAND chip access:  8 bit, 16 bit, or neither */
static struct omap_nand_platform_data nand_data = {
	.options	= NAND_SAMSUNG_LP_OPTIONS,
	.parts		= nand_partitions,
	.nr_parts	= ARRAY_SIZE(nand_partitions),
};

static struct resource nand_resource = {
	.flags		= IORESOURCE_MEM,
};

static struct platform_device nand_device = {
	.name		= "omapnand",
	.id		= 0,
	.dev		= {
		.platform_data	= &nand_data,
	},
	.num_resources	= 1,
	.resource	= &nand_resource,
};

static struct resource smc91x_resources[] = {
	[0] = {
		.start	= OMAP1710_ETHR_START,		/* Physical */
		.end	= OMAP1710_ETHR_START + 0xf,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= OMAP_GPIO_IRQ(40),
		.end	= OMAP_GPIO_IRQ(40),
		.flags	= IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
	},
};

static struct platform_device smc91x_device = {
	.name		= "smc91x",
	.id		= 0,
	.num_resources	= ARRAY_SIZE(smc91x_resources),
	.resource	= smc91x_resources,
};

#define GPTIMER_BASE		0xFFFB1400
#define GPTIMER_REGS(x)	(0xFFFB1400 + (x * 0x800))
#define GPTIMER_REGS_SIZE	0x46

static struct resource intlat_resources[] = {
	[0] = {
		.start  = GPTIMER_REGS(0),	      /* Physical */
		.end    = GPTIMER_REGS(0) + GPTIMER_REGS_SIZE,
		.flags  = IORESOURCE_MEM,
	},
	[1] = {
		.start  = INT_1610_GPTIMER1,
		.end    = INT_1610_GPTIMER1,
		.flags  = IORESOURCE_IRQ,
	},
};

static struct platform_device intlat_device = {
	.name	   = "omap_intlat",
	.id	     = 0,
	.num_resources  = ARRAY_SIZE(intlat_resources),
	.resource       = intlat_resources,
};

static struct resource h3_kp_resources[] = {
	[0] = {
		.start	= INT_KEYBOARD,
		.end	= INT_KEYBOARD,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct omap_kp_platform_data h3_kp_data = {
	.rows		= 8,
	.cols		= 8,
	.keymap		= h3_keymap,
	.keymapsize	= ARRAY_SIZE(h3_keymap),
	.rep		= 1,
	.delay		= 9,
	.dbounce	= 1,
};

static struct platform_device h3_kp_device = {
	.name		= "omap-keypad",
	.id		= -1,
	.dev		= {
		.platform_data = &h3_kp_data,
	},
	.num_resources	= ARRAY_SIZE(h3_kp_resources),
	.resource	= h3_kp_resources,
};

static struct platform_device h3_lcd_device = {
	.name		= "lcd_h3",
	.id		= -1,
};

static struct spi_board_info h3_spi_board_info[] __initdata = {
	[0] = {
		.modalias	= "tsc2101",
		.bus_num	= 2,
		.chip_select	= 0,
		.irq		= OMAP_GPIO_IRQ(H3_TS_GPIO),
		.max_speed_hz	= 16000000,
		/* .platform_data	= &tsc_platform_data, */
	},
};

static struct platform_device *devices[] __initdata = {
	&nor_device,
	&nand_device,
        &smc91x_device,
	&intlat_device,
	&h3_kp_device,
	&h3_lcd_device,
};

static struct omap_usb_config h3_usb_config __initdata = {
	/* usb1 has a Mini-AB port and external isp1301 transceiver */
	.otg	    = 2,

#ifdef CONFIG_USB_GADGET_OMAP
	.hmc_mode       = 19,   /* 0:host(off) 1:dev|otg 2:disabled */
#elif  defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
	/* NONSTANDARD CABLE NEEDED (B-to-Mini-B) */
	.hmc_mode       = 20,   /* 1:dev|otg(off) 1:host 2:disabled */
#endif

	.pins[1]	= 3,
};

static struct omap_lcd_config h3_lcd_config __initdata = {
	.ctrl_name	= "internal",
};

static struct omap_board_config_kernel h3_config[] __initdata = {
	{ OMAP_TAG_LCD,		&h3_lcd_config },
};

static struct i2c_board_info __initdata h3_i2c_board_info[] = {
       {
		I2C_BOARD_INFO("tps65013", 0x48),
               /* .irq         = OMAP_GPIO_IRQ(??), */
       },
	{
		I2C_BOARD_INFO("isp1301_omap", 0x2d),
		.irq		= OMAP_GPIO_IRQ(14),
	},
};

#define H3_NAND_RB_GPIO_PIN	10

static int nand_dev_ready(struct omap_nand_platform_data *data)
{
	return gpio_get_value(H3_NAND_RB_GPIO_PIN);
}

static void __init h3_init(void)
{
	/* Here we assume the NOR boot config:  NOR on CS3 (possibly swapped
	 * to address 0 by a dip switch), NAND on CS2B.  The NAND driver will
	 * notice whether a NAND chip is enabled at probe time.
	 *
	 * H3 support NAND-boot, with a dip switch to put NOR on CS2B and NAND
	 * (which on H2 may be 16bit) on CS3.  Try detecting that in code here,
	 * to avoid probing every possible flash configuration...
	 */
	nor_resource.end = nor_resource.start = omap_cs3_phys();
	nor_resource.end += SZ_32M - 1;

	nand_resource.end = nand_resource.start = OMAP_CS2B_PHYS;
	nand_resource.end += SZ_4K - 1;
	if (gpio_request(H3_NAND_RB_GPIO_PIN, "NAND ready") < 0)
		BUG();
	nand_data.dev_ready = nand_dev_ready;

	/* GPIO10 Func_MUX_CTRL reg bit 29:27, Configure V2 to mode1 as GPIO */
	/* GPIO10 pullup/down register, Enable pullup on GPIO10 */
	omap_cfg_reg(V2_1710_GPIO10);

	platform_add_devices(devices, ARRAY_SIZE(devices));
	spi_register_board_info(h3_spi_board_info,
				ARRAY_SIZE(h3_spi_board_info));
	omap_board_config = h3_config;
	omap_board_config_size = ARRAY_SIZE(h3_config);
	omap_serial_init();
	omap_register_i2c_bus(1, 100, h3_i2c_board_info,
			      ARRAY_SIZE(h3_i2c_board_info));
	omap_usb_init(&h3_usb_config);
	h3_mmc_init();
}

static void __init h3_init_smc91x(void)
{
	omap_cfg_reg(W15_1710_GPIO40);
	if (gpio_request(40, "SMC91x irq") < 0) {
		printk("Error requesting gpio 40 for smc91x irq\n");
		return;
	}
}

static void __init h3_init_irq(void)
{
	omap1_init_common_hw();
	omap_init_irq();
	omap_gpio_init();
	h3_init_smc91x();
}

static void __init h3_map_io(void)
{
	omap1_map_common_io();
}

MACHINE_START(OMAP_H3, "TI OMAP1710 H3 board")
	/* Maintainer: Texas Instruments, Inc. */
	.phys_io	= 0xfff00000,
	.io_pg_offst	= ((0xfef00000) >> 18) & 0xfffc,
	.boot_params	= 0x10000100,
	.map_io		= h3_map_io,
	.init_irq	= h3_init_irq,
	.init_machine	= h3_init,
	.timer		= &omap_timer,
MACHINE_END
Commit	Line	Data
1da177e4	1	/*
dbdf9ced	2	* linux/arch/arm/mach-omap1/board-h3.c
1da177e4 LT	3	*
	4	* This file contains OMAP1710 H3 specific code.
	5	*
	6	* Copyright (C) 2004 Texas Instruments, Inc.
	7	* Copyright (C) 2002 MontaVista Software, Inc.
	8	* Copyright (C) 2001 RidgeRun, Inc.
	9	* Author: RidgeRun, Inc.
	10	* Greg Lonnon (glonnon@ridgerun.com) or info@ridgerun.com
	11	*
	12	* This program is free software; you can redistribute it and/or modify
	13	* it under the terms of the GNU General Public License version 2 as
	14	* published by the Free Software Foundation.
	15	*/
	16
1da177e4 LT	17	#include <linux/types.h>
	18	#include <linux/init.h>
	19	#include <linux/major.h>
	20	#include <linux/kernel.h>
d052d1be	21	#include <linux/platform_device.h>
1da177e4	22	#include <linux/errno.h>
9b6553cd	23	#include <linux/workqueue.h>
8056c6cb	24	#include <linux/i2c.h>
1da177e4	25	#include <linux/mtd/mtd.h>
9b6553cd	26	#include <linux/mtd/nand.h>
1da177e4	27	#include <linux/mtd/partitions.h>
9b6553cd	28	#include <linux/input.h>
0cc0a441	29	#include <linux/spi/spi.h>
6d16bfb5	30	#include <linux/i2c/tps65010.h>
1da177e4 LT	31
	32	#include <asm/setup.h>
	33	#include <asm/page.h>
a09e64fb	34	#include <mach/hardware.h>
8056c6cb DB	35	#include <asm/gpio.h>
8056c6cb DB	36
1da177e4 LT	37	#include <asm/mach-types.h>
	38	#include <asm/mach/arch.h>
	39	#include <asm/mach/flash.h>
	40	#include <asm/mach/map.h>
	41
a09e64fb	42	#include <mach/irqs.h>
ce491cf8 TL	43	#include <plat/mux.h>
	44	#include <plat/tc.h>
	45	#include <plat/nand.h>
	46	#include <plat/usb.h>
	47	#include <plat/keypad.h>
	48	#include <plat/dma.h>
	49	#include <plat/common.h>
1da177e4	50
228fe42e TL	51	#include "board-h3.h"
	52
	53	/* In OMAP1710 H3 the Ethernet is directly connected to CS1 */
	54	#define OMAP1710_ETHR_START 0x04000300
	55
0cc0a441 DB	56	#define H3_TS_GPIO 48
0cc0a441 DB	57
9b6553cd TL	58	static int h3_keymap[] = {
	59	KEY(0, 0, KEY_LEFT),
	60	KEY(0, 1, KEY_RIGHT),
	61	KEY(0, 2, KEY_3),
	62	KEY(0, 3, KEY_F10),
	63	KEY(0, 4, KEY_F5),
	64	KEY(0, 5, KEY_9),
	65	KEY(1, 0, KEY_DOWN),
	66	KEY(1, 1, KEY_UP),
	67	KEY(1, 2, KEY_2),
	68	KEY(1, 3, KEY_F9),
	69	KEY(1, 4, KEY_F7),
	70	KEY(1, 5, KEY_0),
	71	KEY(2, 0, KEY_ENTER),
	72	KEY(2, 1, KEY_6),
	73	KEY(2, 2, KEY_1),
	74	KEY(2, 3, KEY_F2),
	75	KEY(2, 4, KEY_F6),
	76	KEY(2, 5, KEY_HOME),
	77	KEY(3, 0, KEY_8),
	78	KEY(3, 1, KEY_5),
	79	KEY(3, 2, KEY_F12),
	80	KEY(3, 3, KEY_F3),
	81	KEY(3, 4, KEY_F8),
	82	KEY(3, 5, KEY_END),
	83	KEY(4, 0, KEY_7),
	84	KEY(4, 1, KEY_4),
	85	KEY(4, 2, KEY_F11),
	86	KEY(4, 3, KEY_F1),
	87	KEY(4, 4, KEY_F4),
	88	KEY(4, 5, KEY_ESC),
	89	KEY(5, 0, KEY_F13),
	90	KEY(5, 1, KEY_F14),
	91	KEY(5, 2, KEY_F15),
	92	KEY(5, 3, KEY_F16),
	93	KEY(5, 4, KEY_SLEEP),
	94	0
	95	};
	96
	97
	98	static struct mtd_partition nor_partitions[] = {
1da177e4 LT	99	/* bootloader (U-Boot, etc) in first sector */
	100	{
	101	.name = "bootloader",
	102	.offset = 0,
	103	.size = SZ_128K,
	104	.mask_flags = MTD_WRITEABLE, /* force read-only */
	105	},
	106	/* bootloader params in the next sector */
	107	{
	108	.name = "params",
	109	.offset = MTDPART_OFS_APPEND,
	110	.size = SZ_128K,
	111	.mask_flags = 0,
	112	},
	113	/* kernel */
	114	{
	115	.name = "kernel",
	116	.offset = MTDPART_OFS_APPEND,
	117	.size = SZ_2M,
	118	.mask_flags = 0
	119	},
	120	/* file system */
	121	{
	122	.name = "filesystem",
	123	.offset = MTDPART_OFS_APPEND,
	124	.size = MTDPART_SIZ_FULL,
	125	.mask_flags = 0
	126	}
	127	};
	128
9b6553cd	129	static struct flash_platform_data nor_data = {
1da177e4 LT	130	.map_name = "cfi_probe",
1da177e4 LT	131	.width = 2,
9b6553cd TL	132	.parts = nor_partitions,
9b6553cd TL	133	.nr_parts = ARRAY_SIZE(nor_partitions),
1da177e4 LT	134	};
1da177e4 LT	135
9b6553cd	136	static struct resource nor_resource = {
7c38cf02	137	/* This is on CS3, wherever it's mapped */
1da177e4 LT	138	.flags = IORESOURCE_MEM,
	139	};
	140
9b6553cd	141	static struct platform_device nor_device = {
1da177e4 LT	142	.name = "omapflash",
	143	.id = 0,
	144	.dev = {
9b6553cd TL	145	.platform_data = &nor_data,
	146	},
	147	.num_resources = 1,
	148	.resource = &nor_resource,
	149	};
	150
	151	static struct mtd_partition nand_partitions[] = {
	152	#if 0
	153	/* REVISIT: enable these partitions if you make NAND BOOT work */
	154	{
	155	.name = "xloader",
	156	.offset = 0,
	157	.size = 64 * 1024,
	158	.mask_flags = MTD_WRITEABLE, /* force read-only */
	159	},
	160	{
	161	.name = "bootloader",
	162	.offset = MTDPART_OFS_APPEND,
	163	.size = 256 * 1024,
	164	.mask_flags = MTD_WRITEABLE, /* force read-only */
	165	},
	166	{
	167	.name = "params",
	168	.offset = MTDPART_OFS_APPEND,
	169	.size = 192 * 1024,
	170	},
	171	{
	172	.name = "kernel",
	173	.offset = MTDPART_OFS_APPEND,
	174	.size = 2 * SZ_1M,
	175	},
	176	#endif
	177	{
	178	.name = "filesystem",
	179	.size = MTDPART_SIZ_FULL,
	180	.offset = MTDPART_OFS_APPEND,
	181	},
	182	};
	183
	184	/* dip switches control NAND chip access: 8 bit, 16 bit, or neither */
78be6325	185	static struct omap_nand_platform_data nand_data = {
9b6553cd TL	186	.options = NAND_SAMSUNG_LP_OPTIONS,
	187	.parts = nand_partitions,
	188	.nr_parts = ARRAY_SIZE(nand_partitions),
	189	};
	190
	191	static struct resource nand_resource = {
	192	.flags = IORESOURCE_MEM,
	193	};
	194
	195	static struct platform_device nand_device = {
	196	.name = "omapnand",
	197	.id = 0,
	198	.dev = {
	199	.platform_data = &nand_data,
1da177e4 LT	200	},
1da177e4 LT	201	.num_resources = 1,
9b6553cd	202	.resource = &nand_resource,
1da177e4 LT	203	};
	204
	205	static struct resource smc91x_resources[] = {
	206	[0] = {
	207	.start = OMAP1710_ETHR_START, /* Physical */
	208	.end = OMAP1710_ETHR_START + 0xf,
	209	.flags = IORESOURCE_MEM,
	210	},
	211	[1] = {
	212	.start = OMAP_GPIO_IRQ(40),
	213	.end = OMAP_GPIO_IRQ(40),
e7b3dc7e	214	.flags = IORESOURCE_IRQ \| IORESOURCE_IRQ_LOWEDGE,
1da177e4 LT	215	},
	216	};
	217
	218	static struct platform_device smc91x_device = {
	219	.name = "smc91x",
	220	.id = 0,
	221	.num_resources = ARRAY_SIZE(smc91x_resources),
	222	.resource = smc91x_resources,
	223	};
	224
	225	#define GPTIMER_BASE 0xFFFB1400
	226	#define GPTIMER_REGS(x) (0xFFFB1400 + (x * 0x800))
	227	#define GPTIMER_REGS_SIZE 0x46
	228
	229	static struct resource intlat_resources[] = {
	230	[0] = {
	231	.start = GPTIMER_REGS(0), /* Physical */
	232	.end = GPTIMER_REGS(0) + GPTIMER_REGS_SIZE,
	233	.flags = IORESOURCE_MEM,
	234	},
	235	[1] = {
	236	.start = INT_1610_GPTIMER1,
	237	.end = INT_1610_GPTIMER1,
	238	.flags = IORESOURCE_IRQ,
	239	},
	240	};
	241
	242	static struct platform_device intlat_device = {
	243	.name = "omap_intlat",
	244	.id = 0,
	245	.num_resources = ARRAY_SIZE(intlat_resources),
	246	.resource = intlat_resources,
	247	};
	248
9b6553cd TL	249	static struct resource h3_kp_resources[] = {
	250	[0] = {
	251	.start = INT_KEYBOARD,
	252	.end = INT_KEYBOARD,
	253	.flags = IORESOURCE_IRQ,
	254	},
	255	};
	256
	257	static struct omap_kp_platform_data h3_kp_data = {
4d24607b KS	258	.rows = 8,
	259	.cols = 8,
	260	.keymap = h3_keymap,
	261	.keymapsize = ARRAY_SIZE(h3_keymap),
	262	.rep = 1,
	263	.delay = 9,
	264	.dbounce = 1,
9b6553cd TL	265	};
	266
	267	static struct platform_device h3_kp_device = {
	268	.name = "omap-keypad",
	269	.id = -1,
	270	.dev = {
	271	.platform_data = &h3_kp_data,
	272	},
	273	.num_resources = ARRAY_SIZE(h3_kp_resources),
	274	.resource = h3_kp_resources,
	275	};
	276
9b6553cd TL	277	static struct platform_device h3_lcd_device = {
	278	.name = "lcd_h3",
	279	.id = -1,
	280	};
	281
0cc0a441 DB	282	static struct spi_board_info h3_spi_board_info[] __initdata = {
	283	[0] = {
	284	.modalias = "tsc2101",
	285	.bus_num = 2,
	286	.chip_select = 0,
	287	.irq = OMAP_GPIO_IRQ(H3_TS_GPIO),
	288	.max_speed_hz = 16000000,
	289	/* .platform_data = &tsc_platform_data, */
	290	},
	291	};
	292
1da177e4	293	static struct platform_device *devices[] __initdata = {
9b6553cd TL	294	&nor_device,
9b6553cd TL	295	&nand_device,
1da177e4 LT	296	&smc91x_device,
1da177e4 LT	297	&intlat_device,
9b6553cd TL	298	&h3_kp_device,
9b6553cd TL	299	&h3_lcd_device,
1da177e4 LT	300	};
	301
	302	static struct omap_usb_config h3_usb_config __initdata = {
	303	/* usb1 has a Mini-AB port and external isp1301 transceiver */
	304	.otg = 2,
	305
	306	#ifdef CONFIG_USB_GADGET_OMAP
	307	.hmc_mode = 19, /* 0:host(off) 1:dev\|otg 2:disabled */
	308	#elif defined(CONFIG_USB_OHCI_HCD) \|\| defined(CONFIG_USB_OHCI_HCD_MODULE)
	309	/* NONSTANDARD CABLE NEEDED (B-to-Mini-B) */
	310	.hmc_mode = 20, /* 1:dev\|otg(off) 1:host 2:disabled */
	311	#endif
	312
	313	.pins[1] = 3,
	314	};
	315
3179a019	316	static struct omap_lcd_config h3_lcd_config __initdata = {
3179a019 TL	317	.ctrl_name = "internal",
	318	};
	319
e27a93a9	320	static struct omap_board_config_kernel h3_config[] __initdata = {
3179a019	321	{ OMAP_TAG_LCD, &h3_lcd_config },
1da177e4 LT	322	};
1da177e4 LT	323
0cc0a441 DB	324	static struct i2c_board_info __initdata h3_i2c_board_info[] = {
0cc0a441 DB	325	{
3760f736	326	I2C_BOARD_INFO("tps65013", 0x48),
0cc0a441 DB	327	/* .irq = OMAP_GPIO_IRQ(??), */
0cc0a441 DB	328	},
9df013b3 JD	329	{
	330	I2C_BOARD_INFO("isp1301_omap", 0x2d),
	331	.irq = OMAP_GPIO_IRQ(14),
	332	},
0cc0a441 DB	333	};
0cc0a441 DB	334
9b6553cd TL	335	#define H3_NAND_RB_GPIO_PIN 10
9b6553cd TL	336
78be6325	337	static int nand_dev_ready(struct omap_nand_platform_data *data)
9b6553cd	338	{
0b84b5ca	339	return gpio_get_value(H3_NAND_RB_GPIO_PIN);
9b6553cd TL	340	}
9b6553cd TL	341
1da177e4 LT	342	static void __init h3_init(void)
1da177e4 LT	343	{
9b6553cd TL	344	/* Here we assume the NOR boot config: NOR on CS3 (possibly swapped
	345	* to address 0 by a dip switch), NAND on CS2B. The NAND driver will
	346	* notice whether a NAND chip is enabled at probe time.
	347	*
	348	* H3 support NAND-boot, with a dip switch to put NOR on CS2B and NAND
	349	* (which on H2 may be 16bit) on CS3. Try detecting that in code here,
	350	* to avoid probing every possible flash configuration...
	351	*/
	352	nor_resource.end = nor_resource.start = omap_cs3_phys();
	353	nor_resource.end += SZ_32M - 1;
	354
	355	nand_resource.end = nand_resource.start = OMAP_CS2B_PHYS;
	356	nand_resource.end += SZ_4K - 1;
f2d18fea JN	357	if (gpio_request(H3_NAND_RB_GPIO_PIN, "NAND ready") < 0)
	358	BUG();
	359	nand_data.dev_ready = nand_dev_ready;
9b6553cd TL	360
	361	/* GPIO10 Func_MUX_CTRL reg bit 29:27, Configure V2 to mode1 as GPIO */
	362	/* GPIO10 pullup/down register, Enable pullup on GPIO10 */
	363	omap_cfg_reg(V2_1710_GPIO10);
	364
	365	platform_add_devices(devices, ARRAY_SIZE(devices));
e27a93a9 TL	366	spi_register_board_info(h3_spi_board_info,
e27a93a9 TL	367	ARRAY_SIZE(h3_spi_board_info));
7c38cf02 TL	368	omap_board_config = h3_config;
7c38cf02 TL	369	omap_board_config_size = ARRAY_SIZE(h3_config);
3179a019	370	omap_serial_init();
1ed16a86 JN	371	omap_register_i2c_bus(1, 100, h3_i2c_board_info,
1ed16a86 JN	372	ARRAY_SIZE(h3_i2c_board_info));
b0b5aa3f	373	omap_usb_init(&h3_usb_config);
138ab9f8	374	h3_mmc_init();
1da177e4 LT	375	}
	376
	377	static void __init h3_init_smc91x(void)
	378	{
	379	omap_cfg_reg(W15_1710_GPIO40);
f2d18fea	380	if (gpio_request(40, "SMC91x irq") < 0) {
1da177e4 LT	381	printk("Error requesting gpio 40 for smc91x irq\n");
	382	return;
	383	}
1da177e4 LT	384	}
1da177e4 LT	385
277d58ef	386	static void __init h3_init_irq(void)
1da177e4	387	{
87bd63f6	388	omap1_init_common_hw();
1da177e4 LT	389	omap_init_irq();
	390	omap_gpio_init();
	391	h3_init_smc91x();
	392	}
	393
	394	static void __init h3_map_io(void)
	395	{
87bd63f6	396	omap1_map_common_io();
1da177e4 LT	397	}
	398
	399	MACHINE_START(OMAP_H3, "TI OMAP1710 H3 board")
e9dea0c6	400	/* Maintainer: Texas Instruments, Inc. */
e9dea0c6 RK	401	.phys_io = 0xfff00000,
	402	.io_pg_offst = ((0xfef00000) >> 18) & 0xfffc,
	403	.boot_params = 0x10000100,
	404	.map_io = h3_map_io,
	405	.init_irq = h3_init_irq,
	406	.init_machine = h3_init,
1da177e4 LT	407	.timer = &omap_timer,
1da177e4 LT	408	MACHINE_END