]>
Commit | Line | Data |
---|---|---|
3179a019 TL |
1 | /* |
2 | * linux/arch/arm/mach-omap1/clock.c | |
3 | * | |
4 | * Copyright (C) 2004 - 2005 Nokia corporation | |
5 | * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> | |
6 | * | |
7 | * Modified to use omap shared clock framework by | |
8 | * Tony Lindgren <tony@atomide.com> | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | #include <linux/module.h> | |
15 | #include <linux/kernel.h> | |
16 | #include <linux/list.h> | |
17 | #include <linux/errno.h> | |
18 | #include <linux/err.h> | |
f8ce2547 | 19 | #include <linux/clk.h> |
fced80c7 | 20 | #include <linux/io.h> |
3179a019 | 21 | |
90afd5cb | 22 | #include <asm/mach-types.h> |
3179a019 | 23 | |
a09e64fb RK |
24 | #include <mach/cpu.h> |
25 | #include <mach/usb.h> | |
26 | #include <mach/clock.h> | |
27 | #include <mach/sram.h> | |
3179a019 | 28 | |
548d8495 RK |
29 | static const struct clkops clkops_generic; |
30 | static const struct clkops clkops_uart; | |
31 | static const struct clkops clkops_dspck; | |
32 | ||
3179a019 TL |
33 | #include "clock.h" |
34 | ||
548d8495 RK |
35 | static int omap1_clk_enable_generic(struct clk * clk); |
36 | static int omap1_clk_enable(struct clk *clk); | |
37 | static void omap1_clk_disable_generic(struct clk * clk); | |
38 | static void omap1_clk_disable(struct clk *clk); | |
39 | ||
3179a019 TL |
40 | __u32 arm_idlect1_mask; |
41 | ||
42 | /*------------------------------------------------------------------------- | |
43 | * Omap1 specific clock functions | |
44 | *-------------------------------------------------------------------------*/ | |
45 | ||
46 | static void omap1_watchdog_recalc(struct clk * clk) | |
47 | { | |
48 | clk->rate = clk->parent->rate / 14; | |
49 | } | |
50 | ||
51 | static void omap1_uart_recalc(struct clk * clk) | |
52 | { | |
53 | unsigned int val = omap_readl(clk->enable_reg); | |
54 | if (val & clk->enable_bit) | |
55 | clk->rate = 48000000; | |
56 | else | |
57 | clk->rate = 12000000; | |
58 | } | |
59 | ||
df2c2e70 ID |
60 | static void omap1_sossi_recalc(struct clk *clk) |
61 | { | |
62 | u32 div = omap_readl(MOD_CONF_CTRL_1); | |
63 | ||
64 | div = (div >> 17) & 0x7; | |
65 | div++; | |
66 | clk->rate = clk->parent->rate / div; | |
67 | } | |
68 | ||
3179a019 TL |
69 | static int omap1_clk_enable_dsp_domain(struct clk *clk) |
70 | { | |
71 | int retval; | |
72 | ||
10b55794 | 73 | retval = omap1_clk_enable(&api_ck.clk); |
3179a019 | 74 | if (!retval) { |
10b55794 TL |
75 | retval = omap1_clk_enable_generic(clk); |
76 | omap1_clk_disable(&api_ck.clk); | |
3179a019 TL |
77 | } |
78 | ||
79 | return retval; | |
80 | } | |
81 | ||
82 | static void omap1_clk_disable_dsp_domain(struct clk *clk) | |
83 | { | |
10b55794 TL |
84 | if (omap1_clk_enable(&api_ck.clk) == 0) { |
85 | omap1_clk_disable_generic(clk); | |
86 | omap1_clk_disable(&api_ck.clk); | |
3179a019 TL |
87 | } |
88 | } | |
89 | ||
548d8495 RK |
90 | static const struct clkops clkops_dspck = { |
91 | .enable = &omap1_clk_enable_dsp_domain, | |
92 | .disable = &omap1_clk_disable_dsp_domain, | |
93 | }; | |
94 | ||
3179a019 TL |
95 | static int omap1_clk_enable_uart_functional(struct clk *clk) |
96 | { | |
97 | int ret; | |
98 | struct uart_clk *uclk; | |
99 | ||
10b55794 | 100 | ret = omap1_clk_enable_generic(clk); |
3179a019 TL |
101 | if (ret == 0) { |
102 | /* Set smart idle acknowledgement mode */ | |
103 | uclk = (struct uart_clk *)clk; | |
104 | omap_writeb((omap_readb(uclk->sysc_addr) & ~0x10) | 8, | |
105 | uclk->sysc_addr); | |
106 | } | |
107 | ||
108 | return ret; | |
109 | } | |
110 | ||
111 | static void omap1_clk_disable_uart_functional(struct clk *clk) | |
112 | { | |
113 | struct uart_clk *uclk; | |
114 | ||
115 | /* Set force idle acknowledgement mode */ | |
116 | uclk = (struct uart_clk *)clk; | |
117 | omap_writeb((omap_readb(uclk->sysc_addr) & ~0x18), uclk->sysc_addr); | |
118 | ||
10b55794 | 119 | omap1_clk_disable_generic(clk); |
3179a019 TL |
120 | } |
121 | ||
548d8495 RK |
122 | static const struct clkops clkops_uart = { |
123 | .enable = &omap1_clk_enable_uart_functional, | |
124 | .disable = &omap1_clk_disable_uart_functional, | |
125 | }; | |
126 | ||
3179a019 TL |
127 | static void omap1_clk_allow_idle(struct clk *clk) |
128 | { | |
129 | struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk; | |
130 | ||
131 | if (!(clk->flags & CLOCK_IDLE_CONTROL)) | |
132 | return; | |
133 | ||
134 | if (iclk->no_idle_count > 0 && !(--iclk->no_idle_count)) | |
135 | arm_idlect1_mask |= 1 << iclk->idlect_shift; | |
136 | } | |
137 | ||
138 | static void omap1_clk_deny_idle(struct clk *clk) | |
139 | { | |
140 | struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk; | |
141 | ||
142 | if (!(clk->flags & CLOCK_IDLE_CONTROL)) | |
143 | return; | |
144 | ||
145 | if (iclk->no_idle_count++ == 0) | |
146 | arm_idlect1_mask &= ~(1 << iclk->idlect_shift); | |
147 | } | |
148 | ||
149 | static __u16 verify_ckctl_value(__u16 newval) | |
150 | { | |
151 | /* This function checks for following limitations set | |
152 | * by the hardware (all conditions must be true): | |
153 | * DSPMMU_CK == DSP_CK or DSPMMU_CK == DSP_CK/2 | |
154 | * ARM_CK >= TC_CK | |
155 | * DSP_CK >= TC_CK | |
156 | * DSPMMU_CK >= TC_CK | |
157 | * | |
158 | * In addition following rules are enforced: | |
159 | * LCD_CK <= TC_CK | |
160 | * ARMPER_CK <= TC_CK | |
161 | * | |
162 | * However, maximum frequencies are not checked for! | |
163 | */ | |
164 | __u8 per_exp; | |
165 | __u8 lcd_exp; | |
166 | __u8 arm_exp; | |
167 | __u8 dsp_exp; | |
168 | __u8 tc_exp; | |
169 | __u8 dspmmu_exp; | |
170 | ||
171 | per_exp = (newval >> CKCTL_PERDIV_OFFSET) & 3; | |
172 | lcd_exp = (newval >> CKCTL_LCDDIV_OFFSET) & 3; | |
173 | arm_exp = (newval >> CKCTL_ARMDIV_OFFSET) & 3; | |
174 | dsp_exp = (newval >> CKCTL_DSPDIV_OFFSET) & 3; | |
175 | tc_exp = (newval >> CKCTL_TCDIV_OFFSET) & 3; | |
176 | dspmmu_exp = (newval >> CKCTL_DSPMMUDIV_OFFSET) & 3; | |
177 | ||
178 | if (dspmmu_exp < dsp_exp) | |
179 | dspmmu_exp = dsp_exp; | |
180 | if (dspmmu_exp > dsp_exp+1) | |
181 | dspmmu_exp = dsp_exp+1; | |
182 | if (tc_exp < arm_exp) | |
183 | tc_exp = arm_exp; | |
184 | if (tc_exp < dspmmu_exp) | |
185 | tc_exp = dspmmu_exp; | |
186 | if (tc_exp > lcd_exp) | |
187 | lcd_exp = tc_exp; | |
188 | if (tc_exp > per_exp) | |
189 | per_exp = tc_exp; | |
190 | ||
191 | newval &= 0xf000; | |
192 | newval |= per_exp << CKCTL_PERDIV_OFFSET; | |
193 | newval |= lcd_exp << CKCTL_LCDDIV_OFFSET; | |
194 | newval |= arm_exp << CKCTL_ARMDIV_OFFSET; | |
195 | newval |= dsp_exp << CKCTL_DSPDIV_OFFSET; | |
196 | newval |= tc_exp << CKCTL_TCDIV_OFFSET; | |
197 | newval |= dspmmu_exp << CKCTL_DSPMMUDIV_OFFSET; | |
198 | ||
199 | return newval; | |
200 | } | |
201 | ||
202 | static int calc_dsor_exp(struct clk *clk, unsigned long rate) | |
203 | { | |
204 | /* Note: If target frequency is too low, this function will return 4, | |
205 | * which is invalid value. Caller must check for this value and act | |
206 | * accordingly. | |
207 | * | |
208 | * Note: This function does not check for following limitations set | |
209 | * by the hardware (all conditions must be true): | |
210 | * DSPMMU_CK == DSP_CK or DSPMMU_CK == DSP_CK/2 | |
211 | * ARM_CK >= TC_CK | |
212 | * DSP_CK >= TC_CK | |
213 | * DSPMMU_CK >= TC_CK | |
214 | */ | |
215 | unsigned long realrate; | |
216 | struct clk * parent; | |
217 | unsigned dsor_exp; | |
218 | ||
219 | if (unlikely(!(clk->flags & RATE_CKCTL))) | |
220 | return -EINVAL; | |
221 | ||
222 | parent = clk->parent; | |
c0fc18c5 | 223 | if (unlikely(parent == NULL)) |
3179a019 TL |
224 | return -EIO; |
225 | ||
226 | realrate = parent->rate; | |
227 | for (dsor_exp=0; dsor_exp<4; dsor_exp++) { | |
228 | if (realrate <= rate) | |
229 | break; | |
230 | ||
231 | realrate /= 2; | |
232 | } | |
233 | ||
234 | return dsor_exp; | |
235 | } | |
236 | ||
237 | static void omap1_ckctl_recalc(struct clk * clk) | |
238 | { | |
239 | int dsor; | |
240 | ||
241 | /* Calculate divisor encoded as 2-bit exponent */ | |
242 | dsor = 1 << (3 & (omap_readw(ARM_CKCTL) >> clk->rate_offset)); | |
243 | ||
244 | if (unlikely(clk->rate == clk->parent->rate / dsor)) | |
245 | return; /* No change, quick exit */ | |
246 | clk->rate = clk->parent->rate / dsor; | |
247 | ||
248 | if (unlikely(clk->flags & RATE_PROPAGATES)) | |
249 | propagate_rate(clk); | |
250 | } | |
251 | ||
252 | static void omap1_ckctl_recalc_dsp_domain(struct clk * clk) | |
253 | { | |
254 | int dsor; | |
255 | ||
256 | /* Calculate divisor encoded as 2-bit exponent | |
257 | * | |
258 | * The clock control bits are in DSP domain, | |
259 | * so api_ck is needed for access. | |
260 | * Note that DSP_CKCTL virt addr = phys addr, so | |
261 | * we must use __raw_readw() instead of omap_readw(). | |
262 | */ | |
10b55794 | 263 | omap1_clk_enable(&api_ck.clk); |
3179a019 | 264 | dsor = 1 << (3 & (__raw_readw(DSP_CKCTL) >> clk->rate_offset)); |
10b55794 | 265 | omap1_clk_disable(&api_ck.clk); |
3179a019 TL |
266 | |
267 | if (unlikely(clk->rate == clk->parent->rate / dsor)) | |
268 | return; /* No change, quick exit */ | |
269 | clk->rate = clk->parent->rate / dsor; | |
270 | ||
271 | if (unlikely(clk->flags & RATE_PROPAGATES)) | |
272 | propagate_rate(clk); | |
273 | } | |
274 | ||
275 | /* MPU virtual clock functions */ | |
276 | static int omap1_select_table_rate(struct clk * clk, unsigned long rate) | |
277 | { | |
278 | /* Find the highest supported frequency <= rate and switch to it */ | |
279 | struct mpu_rate * ptr; | |
280 | ||
281 | if (clk != &virtual_ck_mpu) | |
282 | return -EINVAL; | |
283 | ||
284 | for (ptr = rate_table; ptr->rate; ptr++) { | |
285 | if (ptr->xtal != ck_ref.rate) | |
286 | continue; | |
287 | ||
288 | /* DPLL1 cannot be reprogrammed without risking system crash */ | |
289 | if (likely(ck_dpll1.rate!=0) && ptr->pll_rate != ck_dpll1.rate) | |
290 | continue; | |
291 | ||
292 | /* Can check only after xtal frequency check */ | |
293 | if (ptr->rate <= rate) | |
294 | break; | |
295 | } | |
296 | ||
297 | if (!ptr->rate) | |
298 | return -EINVAL; | |
299 | ||
300 | /* | |
301 | * In most cases we should not need to reprogram DPLL. | |
302 | * Reprogramming the DPLL is tricky, it must be done from SRAM. | |
495f71db | 303 | * (on 730, bit 13 must always be 1) |
3179a019 | 304 | */ |
495f71db BS |
305 | if (cpu_is_omap730()) |
306 | omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val | 0x2000); | |
307 | else | |
308 | omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val); | |
3179a019 TL |
309 | |
310 | ck_dpll1.rate = ptr->pll_rate; | |
311 | propagate_rate(&ck_dpll1); | |
312 | return 0; | |
313 | } | |
314 | ||
315 | static int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate) | |
316 | { | |
317 | int ret = -EINVAL; | |
318 | int dsor_exp; | |
319 | __u16 regval; | |
320 | ||
321 | if (clk->flags & RATE_CKCTL) { | |
322 | dsor_exp = calc_dsor_exp(clk, rate); | |
323 | if (dsor_exp > 3) | |
324 | dsor_exp = -EINVAL; | |
325 | if (dsor_exp < 0) | |
326 | return dsor_exp; | |
327 | ||
328 | regval = __raw_readw(DSP_CKCTL); | |
329 | regval &= ~(3 << clk->rate_offset); | |
330 | regval |= dsor_exp << clk->rate_offset; | |
331 | __raw_writew(regval, DSP_CKCTL); | |
332 | clk->rate = clk->parent->rate / (1 << dsor_exp); | |
333 | ret = 0; | |
334 | } | |
335 | ||
336 | if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES))) | |
337 | propagate_rate(clk); | |
338 | ||
339 | return ret; | |
340 | } | |
341 | ||
342 | static long omap1_round_to_table_rate(struct clk * clk, unsigned long rate) | |
343 | { | |
344 | /* Find the highest supported frequency <= rate */ | |
345 | struct mpu_rate * ptr; | |
346 | long highest_rate; | |
347 | ||
348 | if (clk != &virtual_ck_mpu) | |
349 | return -EINVAL; | |
350 | ||
351 | highest_rate = -EINVAL; | |
352 | ||
353 | for (ptr = rate_table; ptr->rate; ptr++) { | |
354 | if (ptr->xtal != ck_ref.rate) | |
355 | continue; | |
356 | ||
357 | highest_rate = ptr->rate; | |
358 | ||
359 | /* Can check only after xtal frequency check */ | |
360 | if (ptr->rate <= rate) | |
361 | break; | |
362 | } | |
363 | ||
364 | return highest_rate; | |
365 | } | |
366 | ||
367 | static unsigned calc_ext_dsor(unsigned long rate) | |
368 | { | |
369 | unsigned dsor; | |
370 | ||
371 | /* MCLK and BCLK divisor selection is not linear: | |
372 | * freq = 96MHz / dsor | |
373 | * | |
374 | * RATIO_SEL range: dsor <-> RATIO_SEL | |
375 | * 0..6: (RATIO_SEL+2) <-> (dsor-2) | |
376 | * 6..48: (8+(RATIO_SEL-6)*2) <-> ((dsor-8)/2+6) | |
377 | * Minimum dsor is 2 and maximum is 96. Odd divisors starting from 9 | |
378 | * can not be used. | |
379 | */ | |
380 | for (dsor = 2; dsor < 96; ++dsor) { | |
381 | if ((dsor & 1) && dsor > 8) | |
b824efae | 382 | continue; |
3179a019 TL |
383 | if (rate >= 96000000 / dsor) |
384 | break; | |
385 | } | |
386 | return dsor; | |
387 | } | |
388 | ||
389 | /* Only needed on 1510 */ | |
390 | static int omap1_set_uart_rate(struct clk * clk, unsigned long rate) | |
391 | { | |
392 | unsigned int val; | |
393 | ||
394 | val = omap_readl(clk->enable_reg); | |
395 | if (rate == 12000000) | |
396 | val &= ~(1 << clk->enable_bit); | |
397 | else if (rate == 48000000) | |
398 | val |= (1 << clk->enable_bit); | |
399 | else | |
400 | return -EINVAL; | |
401 | omap_writel(val, clk->enable_reg); | |
402 | clk->rate = rate; | |
403 | ||
404 | return 0; | |
405 | } | |
406 | ||
407 | /* External clock (MCLK & BCLK) functions */ | |
408 | static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate) | |
409 | { | |
410 | unsigned dsor; | |
411 | __u16 ratio_bits; | |
412 | ||
413 | dsor = calc_ext_dsor(rate); | |
414 | clk->rate = 96000000 / dsor; | |
415 | if (dsor > 8) | |
416 | ratio_bits = ((dsor - 8) / 2 + 6) << 2; | |
417 | else | |
418 | ratio_bits = (dsor - 2) << 2; | |
419 | ||
420 | ratio_bits |= omap_readw(clk->enable_reg) & ~0xfd; | |
421 | omap_writew(ratio_bits, clk->enable_reg); | |
422 | ||
423 | return 0; | |
424 | } | |
425 | ||
df2c2e70 ID |
426 | static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate) |
427 | { | |
428 | u32 l; | |
429 | int div; | |
430 | unsigned long p_rate; | |
431 | ||
432 | p_rate = clk->parent->rate; | |
433 | /* Round towards slower frequency */ | |
434 | div = (p_rate + rate - 1) / rate; | |
435 | div--; | |
436 | if (div < 0 || div > 7) | |
437 | return -EINVAL; | |
438 | ||
439 | l = omap_readl(MOD_CONF_CTRL_1); | |
440 | l &= ~(7 << 17); | |
441 | l |= div << 17; | |
442 | omap_writel(l, MOD_CONF_CTRL_1); | |
443 | ||
444 | clk->rate = p_rate / (div + 1); | |
445 | if (unlikely(clk->flags & RATE_PROPAGATES)) | |
446 | propagate_rate(clk); | |
447 | ||
448 | return 0; | |
449 | } | |
450 | ||
3179a019 TL |
451 | static long omap1_round_ext_clk_rate(struct clk * clk, unsigned long rate) |
452 | { | |
453 | return 96000000 / calc_ext_dsor(rate); | |
454 | } | |
455 | ||
456 | static void omap1_init_ext_clk(struct clk * clk) | |
457 | { | |
458 | unsigned dsor; | |
459 | __u16 ratio_bits; | |
460 | ||
461 | /* Determine current rate and ensure clock is based on 96MHz APLL */ | |
462 | ratio_bits = omap_readw(clk->enable_reg) & ~1; | |
463 | omap_writew(ratio_bits, clk->enable_reg); | |
464 | ||
465 | ratio_bits = (ratio_bits & 0xfc) >> 2; | |
466 | if (ratio_bits > 6) | |
467 | dsor = (ratio_bits - 6) * 2 + 8; | |
468 | else | |
469 | dsor = ratio_bits + 2; | |
470 | ||
471 | clk-> rate = 96000000 / dsor; | |
472 | } | |
473 | ||
10b55794 | 474 | static int omap1_clk_enable(struct clk *clk) |
3179a019 TL |
475 | { |
476 | int ret = 0; | |
477 | if (clk->usecount++ == 0) { | |
478 | if (likely(clk->parent)) { | |
10b55794 | 479 | ret = omap1_clk_enable(clk->parent); |
3179a019 TL |
480 | |
481 | if (unlikely(ret != 0)) { | |
482 | clk->usecount--; | |
483 | return ret; | |
484 | } | |
485 | ||
486 | if (clk->flags & CLOCK_NO_IDLE_PARENT) | |
6f9c92f1 | 487 | omap1_clk_deny_idle(clk->parent); |
3179a019 TL |
488 | } |
489 | ||
548d8495 | 490 | ret = clk->ops->enable(clk); |
3179a019 TL |
491 | |
492 | if (unlikely(ret != 0) && clk->parent) { | |
10b55794 | 493 | omap1_clk_disable(clk->parent); |
3179a019 TL |
494 | clk->usecount--; |
495 | } | |
496 | } | |
497 | ||
498 | return ret; | |
499 | } | |
500 | ||
10b55794 | 501 | static void omap1_clk_disable(struct clk *clk) |
3179a019 TL |
502 | { |
503 | if (clk->usecount > 0 && !(--clk->usecount)) { | |
548d8495 | 504 | clk->ops->disable(clk); |
3179a019 | 505 | if (likely(clk->parent)) { |
10b55794 | 506 | omap1_clk_disable(clk->parent); |
3179a019 | 507 | if (clk->flags & CLOCK_NO_IDLE_PARENT) |
6f9c92f1 | 508 | omap1_clk_allow_idle(clk->parent); |
3179a019 TL |
509 | } |
510 | } | |
511 | } | |
512 | ||
10b55794 | 513 | static int omap1_clk_enable_generic(struct clk *clk) |
3179a019 TL |
514 | { |
515 | __u16 regval16; | |
516 | __u32 regval32; | |
517 | ||
c0fc18c5 | 518 | if (unlikely(clk->enable_reg == NULL)) { |
3179a019 TL |
519 | printk(KERN_ERR "clock.c: Enable for %s without enable code\n", |
520 | clk->name); | |
6f9c92f1 | 521 | return -EINVAL; |
3179a019 TL |
522 | } |
523 | ||
524 | if (clk->flags & ENABLE_REG_32BIT) { | |
525 | if (clk->flags & VIRTUAL_IO_ADDRESS) { | |
526 | regval32 = __raw_readl(clk->enable_reg); | |
527 | regval32 |= (1 << clk->enable_bit); | |
528 | __raw_writel(regval32, clk->enable_reg); | |
529 | } else { | |
530 | regval32 = omap_readl(clk->enable_reg); | |
531 | regval32 |= (1 << clk->enable_bit); | |
532 | omap_writel(regval32, clk->enable_reg); | |
533 | } | |
534 | } else { | |
535 | if (clk->flags & VIRTUAL_IO_ADDRESS) { | |
536 | regval16 = __raw_readw(clk->enable_reg); | |
537 | regval16 |= (1 << clk->enable_bit); | |
538 | __raw_writew(regval16, clk->enable_reg); | |
539 | } else { | |
540 | regval16 = omap_readw(clk->enable_reg); | |
541 | regval16 |= (1 << clk->enable_bit); | |
542 | omap_writew(regval16, clk->enable_reg); | |
543 | } | |
544 | } | |
545 | ||
6f9c92f1 | 546 | return 0; |
3179a019 TL |
547 | } |
548 | ||
10b55794 | 549 | static void omap1_clk_disable_generic(struct clk *clk) |
3179a019 TL |
550 | { |
551 | __u16 regval16; | |
552 | __u32 regval32; | |
553 | ||
c0fc18c5 | 554 | if (clk->enable_reg == NULL) |
3179a019 TL |
555 | return; |
556 | ||
557 | if (clk->flags & ENABLE_REG_32BIT) { | |
558 | if (clk->flags & VIRTUAL_IO_ADDRESS) { | |
559 | regval32 = __raw_readl(clk->enable_reg); | |
560 | regval32 &= ~(1 << clk->enable_bit); | |
561 | __raw_writel(regval32, clk->enable_reg); | |
562 | } else { | |
563 | regval32 = omap_readl(clk->enable_reg); | |
564 | regval32 &= ~(1 << clk->enable_bit); | |
565 | omap_writel(regval32, clk->enable_reg); | |
566 | } | |
567 | } else { | |
568 | if (clk->flags & VIRTUAL_IO_ADDRESS) { | |
569 | regval16 = __raw_readw(clk->enable_reg); | |
570 | regval16 &= ~(1 << clk->enable_bit); | |
571 | __raw_writew(regval16, clk->enable_reg); | |
572 | } else { | |
573 | regval16 = omap_readw(clk->enable_reg); | |
574 | regval16 &= ~(1 << clk->enable_bit); | |
575 | omap_writew(regval16, clk->enable_reg); | |
576 | } | |
577 | } | |
578 | } | |
579 | ||
548d8495 RK |
580 | static const struct clkops clkops_generic = { |
581 | .enable = &omap1_clk_enable_generic, | |
582 | .disable = &omap1_clk_disable_generic, | |
583 | }; | |
584 | ||
3179a019 TL |
585 | static long omap1_clk_round_rate(struct clk *clk, unsigned long rate) |
586 | { | |
587 | int dsor_exp; | |
588 | ||
589 | if (clk->flags & RATE_FIXED) | |
590 | return clk->rate; | |
591 | ||
592 | if (clk->flags & RATE_CKCTL) { | |
593 | dsor_exp = calc_dsor_exp(clk, rate); | |
594 | if (dsor_exp < 0) | |
595 | return dsor_exp; | |
596 | if (dsor_exp > 3) | |
597 | dsor_exp = 3; | |
598 | return clk->parent->rate / (1 << dsor_exp); | |
599 | } | |
600 | ||
c0fc18c5 | 601 | if (clk->round_rate != NULL) |
3179a019 TL |
602 | return clk->round_rate(clk, rate); |
603 | ||
604 | return clk->rate; | |
605 | } | |
606 | ||
607 | static int omap1_clk_set_rate(struct clk *clk, unsigned long rate) | |
608 | { | |
609 | int ret = -EINVAL; | |
610 | int dsor_exp; | |
611 | __u16 regval; | |
612 | ||
613 | if (clk->set_rate) | |
614 | ret = clk->set_rate(clk, rate); | |
615 | else if (clk->flags & RATE_CKCTL) { | |
616 | dsor_exp = calc_dsor_exp(clk, rate); | |
617 | if (dsor_exp > 3) | |
618 | dsor_exp = -EINVAL; | |
619 | if (dsor_exp < 0) | |
620 | return dsor_exp; | |
621 | ||
622 | regval = omap_readw(ARM_CKCTL); | |
623 | regval &= ~(3 << clk->rate_offset); | |
624 | regval |= dsor_exp << clk->rate_offset; | |
625 | regval = verify_ckctl_value(regval); | |
626 | omap_writew(regval, ARM_CKCTL); | |
627 | clk->rate = clk->parent->rate / (1 << dsor_exp); | |
628 | ret = 0; | |
629 | } | |
630 | ||
3179a019 TL |
631 | return ret; |
632 | } | |
633 | ||
634 | /*------------------------------------------------------------------------- | |
635 | * Omap1 clock reset and init functions | |
636 | *-------------------------------------------------------------------------*/ | |
637 | ||
638 | #ifdef CONFIG_OMAP_RESET_CLOCKS | |
3179a019 | 639 | |
90afd5cb | 640 | static void __init omap1_clk_disable_unused(struct clk *clk) |
3179a019 | 641 | { |
3179a019 TL |
642 | __u32 regval32; |
643 | ||
90afd5cb TL |
644 | /* Clocks in the DSP domain need api_ck. Just assume bootloader |
645 | * has not enabled any DSP clocks */ | |
397fcaf7 | 646 | if (clk->enable_reg == DSP_IDLECT2) { |
90afd5cb TL |
647 | printk(KERN_INFO "Skipping reset check for DSP domain " |
648 | "clock \"%s\"\n", clk->name); | |
649 | return; | |
650 | } | |
3179a019 | 651 | |
90afd5cb TL |
652 | /* Is the clock already disabled? */ |
653 | if (clk->flags & ENABLE_REG_32BIT) { | |
654 | if (clk->flags & VIRTUAL_IO_ADDRESS) | |
655 | regval32 = __raw_readl(clk->enable_reg); | |
3179a019 | 656 | else |
90afd5cb TL |
657 | regval32 = omap_readl(clk->enable_reg); |
658 | } else { | |
659 | if (clk->flags & VIRTUAL_IO_ADDRESS) | |
660 | regval32 = __raw_readw(clk->enable_reg); | |
661 | else | |
662 | regval32 = omap_readw(clk->enable_reg); | |
663 | } | |
3179a019 | 664 | |
90afd5cb TL |
665 | if ((regval32 & (1 << clk->enable_bit)) == 0) |
666 | return; | |
3179a019 | 667 | |
90afd5cb TL |
668 | /* FIXME: This clock seems to be necessary but no-one |
669 | * has asked for its activation. */ | |
6e2d4107 DC |
670 | if (clk == &tc2_ck /* FIX: pm.c (SRAM), CCP, Camera */ |
671 | || clk == &ck_dpll1out.clk /* FIX: SoSSI, SSR */ | |
672 | || clk == &arm_gpio_ck /* FIX: GPIO code for 1510 */ | |
90afd5cb TL |
673 | ) { |
674 | printk(KERN_INFO "FIXME: Clock \"%s\" seems unused\n", | |
675 | clk->name); | |
676 | return; | |
3179a019 TL |
677 | } |
678 | ||
90afd5cb | 679 | printk(KERN_INFO "Disabling unused clock \"%s\"... ", clk->name); |
548d8495 | 680 | clk->ops->disable(clk); |
90afd5cb | 681 | printk(" done\n"); |
3179a019 | 682 | } |
3179a019 TL |
683 | |
684 | #else | |
90afd5cb | 685 | #define omap1_clk_disable_unused NULL |
3179a019 TL |
686 | #endif |
687 | ||
688 | static struct clk_functions omap1_clk_functions = { | |
10b55794 TL |
689 | .clk_enable = omap1_clk_enable, |
690 | .clk_disable = omap1_clk_disable, | |
3179a019 TL |
691 | .clk_round_rate = omap1_clk_round_rate, |
692 | .clk_set_rate = omap1_clk_set_rate, | |
90afd5cb | 693 | .clk_disable_unused = omap1_clk_disable_unused, |
3179a019 TL |
694 | }; |
695 | ||
696 | int __init omap1_clk_init(void) | |
697 | { | |
698 | struct clk ** clkp; | |
699 | const struct omap_clock_config *info; | |
700 | int crystal_type = 0; /* Default 12 MHz */ | |
90afd5cb TL |
701 | u32 reg; |
702 | ||
ef772f2e DB |
703 | #ifdef CONFIG_DEBUG_LL |
704 | /* Resets some clocks that may be left on from bootloader, | |
705 | * but leaves serial clocks on. | |
706 | */ | |
707 | omap_writel(0x3 << 29, MOD_CONF_CTRL_0); | |
708 | #endif | |
709 | ||
90afd5cb TL |
710 | /* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */ |
711 | reg = omap_readw(SOFT_REQ_REG) & (1 << 4); | |
712 | omap_writew(reg, SOFT_REQ_REG); | |
ef557d76 AZ |
713 | if (!cpu_is_omap15xx()) |
714 | omap_writew(0, SOFT_REQ_REG2); | |
3179a019 | 715 | |
3179a019 TL |
716 | clk_init(&omap1_clk_functions); |
717 | ||
718 | /* By default all idlect1 clocks are allowed to idle */ | |
719 | arm_idlect1_mask = ~0; | |
720 | ||
721 | for (clkp = onchip_clks; clkp < onchip_clks+ARRAY_SIZE(onchip_clks); clkp++) { | |
722 | if (((*clkp)->flags &CLOCK_IN_OMAP1510) && cpu_is_omap1510()) { | |
723 | clk_register(*clkp); | |
724 | continue; | |
725 | } | |
726 | ||
727 | if (((*clkp)->flags &CLOCK_IN_OMAP16XX) && cpu_is_omap16xx()) { | |
728 | clk_register(*clkp); | |
729 | continue; | |
730 | } | |
731 | ||
732 | if (((*clkp)->flags &CLOCK_IN_OMAP730) && cpu_is_omap730()) { | |
733 | clk_register(*clkp); | |
734 | continue; | |
735 | } | |
b824efae TL |
736 | |
737 | if (((*clkp)->flags &CLOCK_IN_OMAP310) && cpu_is_omap310()) { | |
738 | clk_register(*clkp); | |
739 | continue; | |
740 | } | |
3179a019 TL |
741 | } |
742 | ||
743 | info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config); | |
744 | if (info != NULL) { | |
99c658a6 | 745 | if (!cpu_is_omap15xx()) |
3179a019 TL |
746 | crystal_type = info->system_clock_type; |
747 | } | |
748 | ||
749 | #if defined(CONFIG_ARCH_OMAP730) | |
750 | ck_ref.rate = 13000000; | |
751 | #elif defined(CONFIG_ARCH_OMAP16XX) | |
752 | if (crystal_type == 2) | |
753 | ck_ref.rate = 19200000; | |
754 | #endif | |
755 | ||
756 | printk("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: 0x%04x\n", | |
757 | omap_readw(ARM_SYSST), omap_readw(DPLL_CTL), | |
758 | omap_readw(ARM_CKCTL)); | |
759 | ||
760 | /* We want to be in syncronous scalable mode */ | |
761 | omap_writew(0x1000, ARM_SYSST); | |
762 | ||
763 | #ifdef CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER | |
764 | /* Use values set by bootloader. Determine PLL rate and recalculate | |
765 | * dependent clocks as if kernel had changed PLL or divisors. | |
766 | */ | |
767 | { | |
768 | unsigned pll_ctl_val = omap_readw(DPLL_CTL); | |
769 | ||
770 | ck_dpll1.rate = ck_ref.rate; /* Base xtal rate */ | |
771 | if (pll_ctl_val & 0x10) { | |
772 | /* PLL enabled, apply multiplier and divisor */ | |
773 | if (pll_ctl_val & 0xf80) | |
774 | ck_dpll1.rate *= (pll_ctl_val & 0xf80) >> 7; | |
775 | ck_dpll1.rate /= ((pll_ctl_val & 0x60) >> 5) + 1; | |
776 | } else { | |
777 | /* PLL disabled, apply bypass divisor */ | |
778 | switch (pll_ctl_val & 0xc) { | |
779 | case 0: | |
780 | break; | |
781 | case 0x4: | |
782 | ck_dpll1.rate /= 2; | |
783 | break; | |
784 | default: | |
785 | ck_dpll1.rate /= 4; | |
786 | break; | |
787 | } | |
788 | } | |
789 | } | |
790 | propagate_rate(&ck_dpll1); | |
791 | #else | |
792 | /* Find the highest supported frequency and enable it */ | |
793 | if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) { | |
794 | printk(KERN_ERR "System frequencies not set. Check your config.\n"); | |
795 | /* Guess sane values (60MHz) */ | |
796 | omap_writew(0x2290, DPLL_CTL); | |
495f71db | 797 | omap_writew(cpu_is_omap730() ? 0x3005 : 0x1005, ARM_CKCTL); |
3179a019 TL |
798 | ck_dpll1.rate = 60000000; |
799 | propagate_rate(&ck_dpll1); | |
800 | } | |
801 | #endif | |
802 | /* Cache rates for clocks connected to ck_ref (not dpll1) */ | |
803 | propagate_rate(&ck_ref); | |
804 | printk(KERN_INFO "Clocking rate (xtal/DPLL1/MPU): " | |
805 | "%ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n", | |
806 | ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10, | |
807 | ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10, | |
808 | arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10); | |
809 | ||
495f71db | 810 | #if defined(CONFIG_MACH_OMAP_PERSEUS2) || defined(CONFIG_MACH_OMAP_FSAMPLE) |
3179a019 TL |
811 | /* Select slicer output as OMAP input clock */ |
812 | omap_writew(omap_readw(OMAP730_PCC_UPLD_CTRL) & ~0x1, OMAP730_PCC_UPLD_CTRL); | |
813 | #endif | |
814 | ||
90afd5cb TL |
815 | /* Amstrad Delta wants BCLK high when inactive */ |
816 | if (machine_is_ams_delta()) | |
817 | omap_writel(omap_readl(ULPD_CLOCK_CTRL) | | |
818 | (1 << SDW_MCLK_INV_BIT), | |
819 | ULPD_CLOCK_CTRL); | |
820 | ||
3179a019 | 821 | /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */ |
495f71db BS |
822 | /* (on 730, bit 13 must not be cleared) */ |
823 | if (cpu_is_omap730()) | |
824 | omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL); | |
825 | else | |
826 | omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL); | |
3179a019 TL |
827 | |
828 | /* Put DSP/MPUI into reset until needed */ | |
829 | omap_writew(0, ARM_RSTCT1); | |
830 | omap_writew(1, ARM_RSTCT2); | |
831 | omap_writew(0x400, ARM_IDLECT1); | |
832 | ||
833 | /* | |
834 | * According to OMAP5910 Erratum SYS_DMA_1, bit DMACK_REQ (bit 8) | |
835 | * of the ARM_IDLECT2 register must be set to zero. The power-on | |
836 | * default value of this bit is one. | |
837 | */ | |
838 | omap_writew(0x0000, ARM_IDLECT2); /* Turn LCD clock off also */ | |
839 | ||
840 | /* | |
841 | * Only enable those clocks we will need, let the drivers | |
842 | * enable other clocks as necessary | |
843 | */ | |
10b55794 TL |
844 | clk_enable(&armper_ck.clk); |
845 | clk_enable(&armxor_ck.clk); | |
846 | clk_enable(&armtim_ck.clk); /* This should be done by timer code */ | |
3179a019 | 847 | |
b824efae | 848 | if (cpu_is_omap15xx()) |
3179a019 TL |
849 | clk_enable(&arm_gpio_ck); |
850 | ||
851 | return 0; | |
852 | } | |
853 |