projects / mirror_ubuntu-eoan-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| 3179a019 TL |
1 | /* |
| 2 | * linux/arch/arm/mach-omap1/clock.h | |
| 3 | * | |
| 52650505 | 4 | * Copyright (C) 2004 - 2005, 2009 Nokia corporation |
| 3179a019 TL |
5 | * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> |
| 6 | * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc | |
| 7 | * | |
| 8 | * This program is free software; you can redistribute it and/or modify | |
| 9 | * it under the terms of the GNU General Public License version 2 as | |
| 10 | * published by the Free Software Foundation. | |
| 11 | */ | |
| 12 | ||
| 13 | #ifndef __ARCH_ARM_MACH_OMAP1_CLOCK_H | |
| 14 | #define __ARCH_ARM_MACH_OMAP1_CLOCK_H | |
| 15 | ||
| 52650505 PW |
16 | #include <linux/clk.h> |
| 17 | ||
| 18 | #include <plat/clock.h> | |
| 19 | ||
| e9b7086b TL |
20 | int omap1_clk_init(void); |
| 21 | void omap1_clk_late_init(void); | |
| 52650505 PW |
22 | extern int omap1_clk_enable(struct clk *clk); |
| 23 | extern void omap1_clk_disable(struct clk *clk); | |
| 24 | extern long omap1_clk_round_rate(struct clk *clk, unsigned long rate); | |
| 25 | extern int omap1_clk_set_rate(struct clk *clk, unsigned long rate); | |
| 26 | extern unsigned long omap1_ckctl_recalc(struct clk *clk); | |
| 27 | extern int omap1_set_sossi_rate(struct clk *clk, unsigned long rate); | |
| 28 | extern unsigned long omap1_sossi_recalc(struct clk *clk); | |
| 29 | extern unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk); | |
| 30 | extern int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate); | |
| 31 | extern int omap1_set_uart_rate(struct clk *clk, unsigned long rate); | |
| 32 | extern unsigned long omap1_uart_recalc(struct clk *clk); | |
| 33 | extern int omap1_set_ext_clk_rate(struct clk *clk, unsigned long rate); | |
| 34 | extern long omap1_round_ext_clk_rate(struct clk *clk, unsigned long rate); | |
| 35 | extern void omap1_init_ext_clk(struct clk *clk); | |
| 36 | extern int omap1_select_table_rate(struct clk *clk, unsigned long rate); | |
| 37 | extern long omap1_round_to_table_rate(struct clk *clk, unsigned long rate); | |
| 38 | extern int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate); | |
| 39 | extern long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate); | |
| 40 | extern unsigned long omap1_watchdog_recalc(struct clk *clk); | |
| 41 | ||
| 42 | #ifdef CONFIG_OMAP_RESET_CLOCKS | |
| 5838bb67 | 43 | extern void omap1_clk_disable_unused(struct clk *clk); |
| 52650505 PW |
44 | #else |
| 45 | #define omap1_clk_disable_unused NULL | |
| 46 | #endif | |
| 3179a019 TL |
47 | |
| 48 | struct uart_clk { | |
| 49 | struct clk clk; | |
| 50 | unsigned long sysc_addr; | |
| 51 | }; | |
| 52 | ||
| 53 | /* Provide a method for preventing idling some ARM IDLECT clocks */ | |
| 54 | struct arm_idlect1_clk { | |
| 55 | struct clk clk; | |
| 56 | unsigned long no_idle_count; | |
| 57 | __u8 idlect_shift; | |
| 58 | }; | |
| 59 | ||
| 60 | /* ARM_CKCTL bit shifts */ | |
| 61 | #define CKCTL_PERDIV_OFFSET 0 | |
| 62 | #define CKCTL_LCDDIV_OFFSET 2 | |
| 63 | #define CKCTL_ARMDIV_OFFSET 4 | |
| 64 | #define CKCTL_DSPDIV_OFFSET 6 | |
| 65 | #define CKCTL_TCDIV_OFFSET 8 | |
| 66 | #define CKCTL_DSPMMUDIV_OFFSET 10 | |
| 67 | /*#define ARM_TIMXO 12*/ | |
| 68 | #define EN_DSPCK 13 | |
| 69 | /*#define ARM_INTHCK_SEL 14*/ /* Divide-by-2 for mpu inth_ck */ | |
| 70 | /* DSP_CKCTL bit shifts */ | |
| 71 | #define CKCTL_DSPPERDIV_OFFSET 0 | |
| 72 | ||
| 73 | /* ARM_IDLECT2 bit shifts */ | |
| 74 | #define EN_WDTCK 0 | |
| 75 | #define EN_XORPCK 1 | |
| 76 | #define EN_PERCK 2 | |
| 77 | #define EN_LCDCK 3 | |
| 78 | #define EN_LBCK 4 /* Not on 1610/1710 */ | |
| 79 | /*#define EN_HSABCK 5*/ | |
| 80 | #define EN_APICK 6 | |
| 81 | #define EN_TIMCK 7 | |
| 82 | #define DMACK_REQ 8 | |
| 83 | #define EN_GPIOCK 9 /* Not on 1610/1710 */ | |
| 84 | /*#define EN_LBFREECK 10*/ | |
| 85 | #define EN_CKOUT_ARM 11 | |
| 86 | ||
| 87 | /* ARM_IDLECT3 bit shifts */ | |
| 88 | #define EN_OCPI_CK 0 | |
| 89 | #define EN_TC1_CK 2 | |
| 90 | #define EN_TC2_CK 4 | |
| 91 | ||
| 92 | /* DSP_IDLECT2 bit shifts (0,1,2 are same as for ARM_IDLECT2) */ | |
| 93 | #define EN_DSPTIMCK 5 | |
| 94 | ||
| 95 | /* Various register defines for clock controls scattered around OMAP chip */ | |
| 90afd5cb | 96 | #define SDW_MCLK_INV_BIT 2 /* In ULPD_CLKC_CTRL */ |
| 3179a019 TL |
97 | #define USB_MCLK_EN_BIT 4 /* In ULPD_CLKC_CTRL */ |
| 98 | #define USB_HOST_HHC_UHOST_EN 9 /* In MOD_CONF_CTRL_0 */ | |
| 99 | #define SWD_ULPD_PLL_CLK_REQ 1 /* In SWD_CLK_DIV_CTRL_SEL */ | |
| 100 | #define COM_ULPD_PLL_CLK_REQ 1 /* In COM_CLK_DIV_CTRL_SEL */ | |
| 101 | #define SWD_CLK_DIV_CTRL_SEL 0xfffe0874 | |
| 102 | #define COM_CLK_DIV_CTRL_SEL 0xfffe0878 | |
| 103 | #define SOFT_REQ_REG 0xfffe0834 | |
| 104 | #define SOFT_REQ_REG2 0xfffe0880 | |
| 105 | ||
| 52650505 PW |
106 | extern __u32 arm_idlect1_mask; |
| 107 | extern struct clk *api_ck_p, *ck_dpll1_p, *ck_ref_p; | |
| 3179a019 | 108 | |
| 52650505 PW |
109 | extern const struct clkops clkops_dspck; |
| 110 | extern const struct clkops clkops_dummy; | |
| fb2fc920 | 111 | extern const struct clkops clkops_uart_16xx; |
| 52650505 | 112 | extern const struct clkops clkops_generic; |
| 90afd5cb | 113 | |
| 3179a019 | 114 | #endif |