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1a59d1b8 | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
8d72c796 JK |
2 | /* |
3 | * arch/arm/mach-omap1/include/mach/lcdc.h | |
4 | * | |
5 | * Extracted from drivers/video/omap/lcdc.c | |
6 | * Copyright (C) 2004 Nokia Corporation | |
7 | * Author: Imre Deak <imre.deak@nokia.com> | |
8d72c796 JK |
8 | */ |
9 | #ifndef __MACH_LCDC_H__ | |
10 | #define __MACH_LCDC_H__ | |
11 | ||
12 | #define OMAP_LCDC_BASE 0xfffec000 | |
13 | #define OMAP_LCDC_SIZE 256 | |
14 | #define OMAP_LCDC_IRQ INT_LCD_CTRL | |
15 | ||
16 | #define OMAP_LCDC_CONTROL (OMAP_LCDC_BASE + 0x00) | |
17 | #define OMAP_LCDC_TIMING0 (OMAP_LCDC_BASE + 0x04) | |
18 | #define OMAP_LCDC_TIMING1 (OMAP_LCDC_BASE + 0x08) | |
19 | #define OMAP_LCDC_TIMING2 (OMAP_LCDC_BASE + 0x0c) | |
20 | #define OMAP_LCDC_STATUS (OMAP_LCDC_BASE + 0x10) | |
21 | #define OMAP_LCDC_SUBPANEL (OMAP_LCDC_BASE + 0x14) | |
22 | #define OMAP_LCDC_LINE_INT (OMAP_LCDC_BASE + 0x18) | |
23 | #define OMAP_LCDC_DISPLAY_STATUS (OMAP_LCDC_BASE + 0x1c) | |
24 | ||
25 | #define OMAP_LCDC_STAT_DONE (1 << 0) | |
26 | #define OMAP_LCDC_STAT_VSYNC (1 << 1) | |
27 | #define OMAP_LCDC_STAT_SYNC_LOST (1 << 2) | |
28 | #define OMAP_LCDC_STAT_ABC (1 << 3) | |
29 | #define OMAP_LCDC_STAT_LINE_INT (1 << 4) | |
30 | #define OMAP_LCDC_STAT_FUF (1 << 5) | |
31 | #define OMAP_LCDC_STAT_LOADED_PALETTE (1 << 6) | |
32 | ||
33 | #define OMAP_LCDC_CTRL_LCD_EN (1 << 0) | |
34 | #define OMAP_LCDC_CTRL_LCD_TFT (1 << 7) | |
35 | #define OMAP_LCDC_CTRL_LINE_IRQ_CLR_SEL (1 << 10) | |
36 | ||
37 | #define OMAP_LCDC_IRQ_VSYNC (1 << 2) | |
38 | #define OMAP_LCDC_IRQ_DONE (1 << 3) | |
39 | #define OMAP_LCDC_IRQ_LOADED_PALETTE (1 << 4) | |
40 | #define OMAP_LCDC_IRQ_LINE_NIRQ (1 << 5) | |
41 | #define OMAP_LCDC_IRQ_LINE (1 << 6) | |
42 | #define OMAP_LCDC_IRQ_MASK (((1 << 5) - 1) << 2) | |
43 | ||
44 | #endif /* __MACH_LCDC_H__ */ |