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Commit | Line | Data |
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1da177e4 | 1 | /* |
7c38cf02 | 2 | * linux/arch/arm/mach-omap1/irq.c |
1da177e4 LT |
3 | * |
4 | * Interrupt handler for all OMAP boards | |
5 | * | |
6 | * Copyright (C) 2004 Nokia Corporation | |
7 | * Written by Tony Lindgren <tony@atomide.com> | |
96de0e25 | 8 | * Major cleanups by Juha Yrjölä <juha.yrjola@nokia.com> |
1da177e4 LT |
9 | * |
10 | * Completely re-written to support various OMAP chips with bank specific | |
11 | * interrupt handlers. | |
12 | * | |
13 | * Some snippets of the code taken from the older OMAP interrupt handler | |
14 | * Copyright (C) 2001 RidgeRun, Inc. Greg Lonnon <glonnon@ridgerun.com> | |
15 | * | |
16 | * GPIO interrupt handler moved to gpio.c by Juha Yrjola | |
17 | * | |
18 | * This program is free software; you can redistribute it and/or modify it | |
19 | * under the terms of the GNU General Public License as published by the | |
20 | * Free Software Foundation; either version 2 of the License, or (at your | |
21 | * option) any later version. | |
22 | * | |
23 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | |
24 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | |
25 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | |
26 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | |
27 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | |
28 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | |
29 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | |
30 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
31 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | |
32 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
33 | * | |
34 | * You should have received a copy of the GNU General Public License along | |
35 | * with this program; if not, write to the Free Software Foundation, Inc., | |
36 | * 675 Mass Ave, Cambridge, MA 02139, USA. | |
37 | */ | |
38 | ||
1da177e4 LT |
39 | #include <linux/init.h> |
40 | #include <linux/module.h> | |
41 | #include <linux/sched.h> | |
42 | #include <linux/interrupt.h> | |
fced80c7 | 43 | #include <linux/io.h> |
1da177e4 | 44 | |
a09e64fb | 45 | #include <mach/hardware.h> |
1da177e4 LT |
46 | #include <asm/irq.h> |
47 | #include <asm/mach/irq.h> | |
a09e64fb | 48 | #include <mach/gpio.h> |
ce491cf8 | 49 | #include <plat/cpu.h> |
1da177e4 | 50 | |
1da177e4 LT |
51 | #define IRQ_BANK(irq) ((irq) >> 5) |
52 | #define IRQ_BIT(irq) ((irq) & 0x1f) | |
53 | ||
54 | struct omap_irq_bank { | |
55 | unsigned long base_reg; | |
56 | unsigned long trigger_map; | |
3b59b6be | 57 | unsigned long wake_enable; |
1da177e4 LT |
58 | }; |
59 | ||
120db2cb | 60 | static unsigned int irq_bank_count; |
1da177e4 LT |
61 | static struct omap_irq_bank *irq_banks; |
62 | ||
63 | static inline unsigned int irq_bank_readl(int bank, int offset) | |
64 | { | |
65 | return omap_readl(irq_banks[bank].base_reg + offset); | |
66 | } | |
67 | ||
68 | static inline void irq_bank_writel(unsigned long value, int bank, int offset) | |
69 | { | |
70 | omap_writel(value, irq_banks[bank].base_reg + offset); | |
71 | } | |
72 | ||
73 | static void omap_ack_irq(unsigned int irq) | |
74 | { | |
75 | if (irq > 31) | |
76 | omap_writel(0x1, OMAP_IH2_BASE + IRQ_CONTROL_REG_OFFSET); | |
77 | ||
78 | omap_writel(0x1, OMAP_IH1_BASE + IRQ_CONTROL_REG_OFFSET); | |
79 | } | |
80 | ||
81 | static void omap_mask_irq(unsigned int irq) | |
82 | { | |
83 | int bank = IRQ_BANK(irq); | |
84 | u32 l; | |
85 | ||
86 | l = omap_readl(irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET); | |
87 | l |= 1 << IRQ_BIT(irq); | |
88 | omap_writel(l, irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET); | |
89 | } | |
90 | ||
91 | static void omap_unmask_irq(unsigned int irq) | |
92 | { | |
93 | int bank = IRQ_BANK(irq); | |
94 | u32 l; | |
95 | ||
96 | l = omap_readl(irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET); | |
97 | l &= ~(1 << IRQ_BIT(irq)); | |
98 | omap_writel(l, irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET); | |
99 | } | |
100 | ||
101 | static void omap_mask_ack_irq(unsigned int irq) | |
102 | { | |
103 | omap_mask_irq(irq); | |
104 | omap_ack_irq(irq); | |
105 | } | |
106 | ||
3b59b6be TL |
107 | static int omap_wake_irq(unsigned int irq, unsigned int enable) |
108 | { | |
109 | int bank = IRQ_BANK(irq); | |
110 | ||
111 | if (enable) | |
112 | irq_banks[bank].wake_enable |= IRQ_BIT(irq); | |
113 | else | |
114 | irq_banks[bank].wake_enable &= ~IRQ_BIT(irq); | |
115 | ||
116 | return 0; | |
117 | } | |
118 | ||
119 | ||
1da177e4 LT |
120 | /* |
121 | * Allows tuning the IRQ type and priority | |
122 | * | |
123 | * NOTE: There is currently no OMAP fiq handler for Linux. Read the | |
124 | * mailing list threads on FIQ handlers if you are planning to | |
125 | * add a FIQ handler for OMAP. | |
126 | */ | |
127 | static void omap_irq_set_cfg(int irq, int fiq, int priority, int trigger) | |
128 | { | |
129 | signed int bank; | |
130 | unsigned long val, offset; | |
131 | ||
132 | bank = IRQ_BANK(irq); | |
133 | /* FIQ is only available on bank 0 interrupts */ | |
134 | fiq = bank ? 0 : (fiq & 0x1); | |
135 | val = fiq | ((priority & 0x1f) << 2) | ((trigger & 0x1) << 1); | |
136 | offset = IRQ_ILR0_REG_OFFSET + IRQ_BIT(irq) * 0x4; | |
137 | irq_bank_writel(val, bank, offset); | |
138 | } | |
139 | ||
559663b9 | 140 | #if defined (CONFIG_ARCH_OMAP730) || defined (CONFIG_ARCH_OMAP850) |
7c006926 | 141 | static struct omap_irq_bank omap7xx_irq_banks[] = { |
120db2cb TL |
142 | { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3f8e22f }, |
143 | { .base_reg = OMAP_IH2_BASE, .trigger_map = 0xfdb9c1f2 }, | |
1da177e4 LT |
144 | { .base_reg = OMAP_IH2_BASE + 0x100, .trigger_map = 0x800040f3 }, |
145 | }; | |
146 | #endif | |
147 | ||
3179a019 | 148 | #ifdef CONFIG_ARCH_OMAP15XX |
1da177e4 | 149 | static struct omap_irq_bank omap1510_irq_banks[] = { |
120db2cb TL |
150 | { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3febfff }, |
151 | { .base_reg = OMAP_IH2_BASE, .trigger_map = 0xffbfffed }, | |
1da177e4 | 152 | }; |
3179a019 | 153 | static struct omap_irq_bank omap310_irq_banks[] = { |
120db2cb TL |
154 | { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3faefc3 }, |
155 | { .base_reg = OMAP_IH2_BASE, .trigger_map = 0x65b3c061 }, | |
3179a019 | 156 | }; |
1da177e4 LT |
157 | #endif |
158 | ||
159 | #if defined(CONFIG_ARCH_OMAP16XX) | |
160 | ||
161 | static struct omap_irq_bank omap1610_irq_banks[] = { | |
120db2cb TL |
162 | { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3fefe8f }, |
163 | { .base_reg = OMAP_IH2_BASE, .trigger_map = 0xfdb7c1fd }, | |
3b59b6be | 164 | { .base_reg = OMAP_IH2_BASE + 0x100, .trigger_map = 0xffffb7ff }, |
1da177e4 LT |
165 | { .base_reg = OMAP_IH2_BASE + 0x200, .trigger_map = 0xffffffff }, |
166 | }; | |
167 | #endif | |
168 | ||
38c677cb DB |
169 | static struct irq_chip omap_irq_chip = { |
170 | .name = "MPU", | |
2be863c9 RK |
171 | .ack = omap_mask_ack_irq, |
172 | .mask = omap_mask_irq, | |
173 | .unmask = omap_unmask_irq, | |
174 | .set_wake = omap_wake_irq, | |
1da177e4 LT |
175 | }; |
176 | ||
177 | void __init omap_init_irq(void) | |
178 | { | |
03a9e512 | 179 | extern unsigned int omap_irq_flags; |
1da177e4 LT |
180 | int i, j; |
181 | ||
559663b9 AB |
182 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
183 | if (cpu_is_omap7xx()) { | |
03a9e512 | 184 | omap_irq_flags = INT_7XX_IH2_IRQ; |
7c006926 AB |
185 | irq_banks = omap7xx_irq_banks; |
186 | irq_bank_count = ARRAY_SIZE(omap7xx_irq_banks); | |
1da177e4 LT |
187 | } |
188 | #endif | |
3179a019 | 189 | #ifdef CONFIG_ARCH_OMAP15XX |
1da177e4 | 190 | if (cpu_is_omap1510()) { |
03a9e512 | 191 | omap_irq_flags = INT_1510_IH2_IRQ; |
1da177e4 LT |
192 | irq_banks = omap1510_irq_banks; |
193 | irq_bank_count = ARRAY_SIZE(omap1510_irq_banks); | |
194 | } | |
3179a019 | 195 | if (cpu_is_omap310()) { |
03a9e512 | 196 | omap_irq_flags = INT_1510_IH2_IRQ; |
3179a019 TL |
197 | irq_banks = omap310_irq_banks; |
198 | irq_bank_count = ARRAY_SIZE(omap310_irq_banks); | |
199 | } | |
1da177e4 LT |
200 | #endif |
201 | #if defined(CONFIG_ARCH_OMAP16XX) | |
202 | if (cpu_is_omap16xx()) { | |
03a9e512 | 203 | omap_irq_flags = INT_1510_IH2_IRQ; |
1da177e4 LT |
204 | irq_banks = omap1610_irq_banks; |
205 | irq_bank_count = ARRAY_SIZE(omap1610_irq_banks); | |
206 | } | |
207 | #endif | |
208 | printk("Total of %i interrupts in %i interrupt banks\n", | |
209 | irq_bank_count * 32, irq_bank_count); | |
210 | ||
211 | /* Mask and clear all interrupts */ | |
212 | for (i = 0; i < irq_bank_count; i++) { | |
213 | irq_bank_writel(~0x0, i, IRQ_MIR_REG_OFFSET); | |
214 | irq_bank_writel(0x0, i, IRQ_ITR_REG_OFFSET); | |
215 | } | |
216 | ||
217 | /* Clear any pending interrupts */ | |
218 | irq_bank_writel(0x03, 0, IRQ_CONTROL_REG_OFFSET); | |
219 | irq_bank_writel(0x03, 1, IRQ_CONTROL_REG_OFFSET); | |
220 | ||
221 | /* Enable interrupts in global mask */ | |
59185eee | 222 | if (cpu_is_omap7xx()) |
1da177e4 | 223 | irq_bank_writel(0x0, 0, IRQ_GMR_REG_OFFSET); |
1da177e4 LT |
224 | |
225 | /* Install the interrupt handlers for each bank */ | |
226 | for (i = 0; i < irq_bank_count; i++) { | |
227 | for (j = i * 32; j < (i + 1) * 32; j++) { | |
228 | int irq_trigger; | |
229 | ||
230 | irq_trigger = irq_banks[i].trigger_map >> IRQ_BIT(j); | |
231 | omap_irq_set_cfg(j, 0, 0, irq_trigger); | |
232 | ||
233 | set_irq_chip(j, &omap_irq_chip); | |
10dd5ce2 | 234 | set_irq_handler(j, handle_level_irq); |
1da177e4 LT |
235 | set_irq_flags(j, IRQF_VALID); |
236 | } | |
237 | } | |
238 | ||
239 | /* Unmask level 2 handler */ | |
3179a019 | 240 | |
559663b9 | 241 | if (cpu_is_omap7xx()) |
372b1c32 | 242 | omap_unmask_irq(INT_7XX_IH2_IRQ); |
ef557d76 | 243 | else if (cpu_is_omap15xx()) |
3179a019 TL |
244 | omap_unmask_irq(INT_1510_IH2_IRQ); |
245 | else if (cpu_is_omap16xx()) | |
246 | omap_unmask_irq(INT_1610_IH2_IRQ); | |
1da177e4 | 247 | } |